FETbias.

doc INTRO

FET BIASING Richard Lee to be completed. References & loadsa important stuff missing.

?nov11

This note is about biasing junction FETs at the front end of condensor microphone circuits. The principles are universally applicable. But if line level rather than low level microphone signals are your interest, other techniques may be better. Or you need more accurate assumptions than what Ive used. > I need to bias a 2sk170BL FET for use in a microphone. ... ~10V > I'd like to use a source follower. Yus gurus, please excuse the simplifications .. 8>D In most amps including a simple source follower, you want the output DC voltage to sit about 1/2 way between the low & high supply rails. In this case, 0V & 10V. This give the most output before distortion. So you want the Source to be at about 5V. You do this by adjusting the Source Resistor. The FET current through this gives a voltage. Because your Gate resistor (1G) is connected to the earthy side, this voltage makes the Gate negative (Vgs) which tends to drop the current. This is a feedback mechanism which stabilizes the FET current at a value which depends on the Source Resistor and the characteristics of the FET. Old timers will recognise this as Cathode Biasing. Tubes have very consistent characteristics so you had tables of Cathode Resistor vs Tube current. There's a graphical method to get these values and I've been trying to find a simple internet explanation of this without success; either for tubes or FETs. But with 2sk170, there is another problem. The Gate Source Cutoff Voltage Vgs(off) varies between 0.3 & 0.8V. This is the voltage that nearly drops the FET current to zero so it is the highest Source voltage you can get by simply adjusting the Source resistor. You don't want to be running the FET near Cutoff. You get best dynamic range from the FET when running about 1/2 Idss. Toshiba 2sk170 come in 3 Idss groups; 2.6-6.5mA, 6-12mA & 10-20mA. Because this is a mike application, you probably don't need the full (well nearly full) 10V peak to peak output from having the Source at 5V. Here is a quick method which gives good results if you are making one or two mikes and can adjust things individually. 1) Find Idss (the FET current when the Gate & Source are at the same voltage) for your FET. - connect Gate to Source and connect your FET to a 9V battery via a milli-ammeter. - Drain to +9V. Gate & Source to 0V

FETbias.doc

FET BIASING Richard Lee

?nov11

2) Find a Source resistor which reduces the FET current to 1/2 Idss - On the set up for finding Idss, introduce a (2k2) resistor between Gate & Source. Adjust until current drops to 1/2 Idss as found in 1) - Drain to +9V. Gate & one end of Source resistor to 0V. Other end of resistor to Source - Measure the voltage across this resistor. This will be about the maximum peak voltage that this simple circuit can deliver. About 1/2 Vgs(off) - This single Source resistor scheme is good for most applications and used by most mike manufacturers. - If you look at Fig ? which shows the variation in Vgs vs Id curves, youll also see that for a given FET (or FET family), the same resistor will give about the same proportion of Idss. So if you are after 1/2 Idss, the same resistor can be used in production for all FETs of the same batch, manufacturer & serial number. If you want a specific FET current though, you will have to adjust Rs individually - Another good approximation for this (1/2 Idss) resistor is Vgs(off) / Idss which you can get from the FET datasheet. If you are not happy with this maximum peak voltage ... 3) introduce a resistor below the junction of Gate (1G) & Source (2k2) resistors to 0V. This will raise the Source to 5V or whatever you want. (In this scheme, the 'Source' resistor is in 2 parts; one part determined by 2) and the other determined by 3). The Gate (1G) resistor is taken, not to 0V, but to the junction of these 2 resistors.) This is called gate feedback in [1]. SCHOEPS PHASE SPLITTER to be completed

Section 2) shows how to find a Source Resistor to get 1/2 Idss. This sets the Current and is a good choice. For the Voltage conditions we have to consider that both the Source & the Drain need to have enough room to swing the maximum possible voltage. If the FET was "ideal" (and still gives good gain when Vds=0), then it would be best to have the source at 1/4 Vcc and the drain at 3/4 Vcc. When the FET is passing maximum current current, both the drain & source will move close to 1/2 Vcc. When it is nearly off, the drain moves to Vcc while the source goes near 0V. The swing at both drain & source will be near 1/2 Vcc peak to peak ie the maximum possible for 2 outputs from the phase splitter. So you pass your design current (1/2 Idss) through the source resistor & your drain resistor of the same value and see if you have these Voltage conditions. If not, you may want to change Vcc or select a design current somewhat less than 1/2 Idss. If you are a guru, please excuse the huge simplifications I've made for the above especially about saturation of the FET.

FETbias.doc

FET BIASING Richard Lee

?nov11

There is no need to make the source & drain resistor the same but it is usual. If they are different, things are more complicated especially if you want to do the distortion cancelling that Goran & Scott describe. After all this rigmarole, I'll just comment that the usual 2k2 - 4k7 Source resistor gets you close enough with the usual FETs ... unless you are a perfectionist. This is Goran Hahnes explanation of how to bias a REAL Schoeps CMC3/5 according to Dip. Ing. Jo Wuttke who invented the circuit in the 1960s. The fine tuning is done with a distortion meter but Goran points out that this method also gives close (within 1dB) to maximum undistorted output. The CMC5 circuit is in our Files/Schematics as Schoeps.pdf
In the original Schoeps CMC 3/5 amplifier circuit no matter what FET you stuck in there, the phase splitter, will be operated at around 0.8 mA of standing class A bias current. You use P1 to adjust the proper operating point so you can stuck almost any suitable FET with a IDSS greater than 2 mA in there and you can set it to the correct operating point reagrdless. This adjustment is best done by using a low distortion oscillator having less than 0.001 percent distortion at 1 kHz. You will then find that the distortion at 0,3 volt @ 1 kHz input to the gate of the FET through a 43 pF capacitor to simulate the capsule source impedance will give a distortion of typical 0.015 percent with the AC feedback active in the Schoeps schematic. With this AC feedback to the floating capsule disabled the distortion rises to around 0.03 percent which is still excellent for such a simple circuit. The distortion is almost all composed of third harmonic and the 2nd is generally below 0.005 percent, -86 dB using a suitable FET. This operating point gives almost symmetrical clipping. 0.3 volt input corresponds to around 124 dB SPL at a typical Schoeps capsule and the CMC amp will accept around 1 volt for around 134 dB maximum SPL for the preamp alone near clipping. At least to me a FET with an IDSS of 6 mA run at 0.5 mA can easily supply the 1.5 mA (??) necessary at max peak input at around 1.4 V peak and will not go into cutoff as you state. Schoeps Engineering Director Emeritus, Jurg Wttke, should be commended for engineering such a very simple very high performance circuit in the mid 60s.

Guru Scott Wurcer analyses this distortion reduction mechanism in his series on LN mike circuits in Linear Audio. Magazine Vol 1. REFERENCES [1]
http://www.colorado.edu/physics/phys3330/phys3330_fa06/pdfdocs/AN102FETbiasing.pdf

FETbias.doc HISTORY ?nov 8nov11

FET BIASING Richard Lee

?nov11

1st incomplete version to MicBuilders