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SDL v SCA, vi ngun cung cp 5v nu bn s dng PWM, khi khng c in tr ko ln cc chn ny. Pin 5 c s dng ch ra kch c ca la bn, ghi gi tr 255 ( 0xFF ) cho thanh ghi command. Cc ch dn y cho vic ghi kch thc th nhiu hn y. Ng vo xc nh c in tr ko ln ngay trn bo mch v c th b ra sau khi nh c. Pin 7 v 8 thc t khng s dng. N gn trn bo v c th khng cn phi kt ni. Pin 9 chn t , cp ngun 0 v.
Chc nng S phin bn phn mm, phin bn 14 hoc cao hn cho phin bn sm hn Ly d liu la bn dng byte, 0-255 cho mt vng Ly d liu dng Word, 0-3599 cho mt vng tng trng cho 0-359.90 Kim tra bn trong- cm bin 1 x l cc tn hiu khc nhau-16 bit signed word Kim tra bn trong- cm bin 2 x l cc tn hiu khc nhau-16 bit signed word Kim tra bn trong-d liu th ca cm bin 1-16 bit signed word Kim tra bn trong-d liu th ca cm bin 2-16 bit signed word M m kha 1- m m kha c yu cu cho a ch I2C thay i hay lu tr s xc nh kch c. M m kha 2
14 15
Thanh ghi 0 l s phin bn phn mm ( 14 ti thi im ca bi vit ny ). Thanh ghi 1 xut ra vic chuyn i t 0-255 gi tr. N c th d dng hn cho 1 vi ng dng nh l 0-360 yu cu 2 byte. Cho cc ng dng khc yu cu nhiu gii php hn th thanh ghi 2,3 ( byte cao trc ) l 16 bit unsigned integer trong tm t 0-3599. Thanh ghi 4 n 11 l thanh ghi kim tra bn trong. Thanh ghi 8,9 v 10,11 bao gm cc d liu cm bin th. Cc tn hiu ny n trc tip t cc cm bin v im bt u cho cc tnh tan cc gi tr trc khi xut ra. Thanh ghi 12,13 v 14 cho vic ghi m m kha cho a ch I2C thay i hay lu tr vic xc nh kch thc. Thanh ghi 15 l thanh ghi lnh. Giao tip I2C khng c in tr ko ln no trn bo mch, n phi c cung cp t bn ngai hu ht l vi bus master. Chng c cung cp c 2 ng SDA v SCL nhng ch 1 cho c bus, khng phi cho tng module. Ti khuyn bn nn s dng gi tr 1k8 nu bn lm vic vi tn s 400khz v 1k2 nu lm vic tn s trn 1Mhz. La bn c thit k lm vic tc tiu chun ( SCL ) l 100khz mc d tc xung clock c th ln ti 1 Mhz. tc trn 160khz, CPU khng p ng nhanh c d liu t I2C. Do 1 delay c 50us c th c thm vo bng cch ghi vo thanh ghi a ch. Khng delay c yu cu bt c ni no khc trong chui. Bng cch ny, ti kim tra la bn in t t ti tc 1.3 Mhz SCL. C driver tham kho s dng HITECH PICC compiler cho PIC 16F877. La bn in t lun iu khin nh l 1 slave, n khng bao gi l 1 bus master.
Ch rng m m kha th khc vi cc m khc dnd lu tr calibration. Rea12 Rea13 Rea14 Rea15 0xA0 0xAA 0xA5 0xC2 V d trn thay i a ch 0xC2 v a ch mi s c nh hng ngay lp tc. ng qun nhn CMPS03 cho a ch mi. Bn c th lm iu ny trong 1 ng truyn I2C , thit lp a ch thanh ghi l 12 v ghi vo 4 byte. Con tr a ch thanh ghi c tng 1 cch t ng.
Lu tr gi tr Calibration
Vi phin bn 14, gi c th lu tr vic thit lp calibration. Bn lm iu ny bng cch ghi m m kha cho thanh ghi 12,13 v 14 v yu cu lu tr ( 0xF2) cho thanh ghi 15. Ch rng m m kha th khc so vi cc m khc cho vic thay i a ch I2C. Rea12 Rea13 Rea14 Rea15 0x55 0x5A 0xA5 0xF2 Bn c th lm c trn 1 ng truyn, thit lp a ch thanh ghi l 12 v ghi 4 byte. Con tr a ch thanh ghi ni bn trong c tng gi tr 1 cch t ng.
Calibration
Khng bao gi th cho n khi la bn ca bn ang hat ng. c bit nu bn s dng giao tip I2C th n phi han tan hat ng trc . Module sn sng calibration , c ngha l lc n 670. Nu v tr ca bn th khng ging nh vy, bn c th th la bn in t m khng c vic calibration li. Calibration ch cn lm 1 ln d liu calibration c lu trong EEPROM trong con chip PIC18F2321. Bn khng cn phi calibration li mi ln module hat ng. S nh hng ca la bn in t xut ra gi tr 00. Trc khi calib la bn, bn phi bit chnh xc hng ng , Ty , Nam, Bc. Nh l cc t trng ca cc hng ny ch khng phi l cc a l. ng an m. Ly 1 la bn t trng v kim tra th. Khi calib, chc chn rng la bn ang phng ngang, khng c nghing. Gi yn v gi vt liu st trnh xa la bn trong sut qu trnh calib- bao gm c ng h eo tay.
Phng php I2C: calib s dng bus I2C, bn ch cn ghi gi tr 255(0xff) cho thanh ghi 15, 1 ln cho mi hng chnh ca la bn: ng,Ty,Nam,Bc. Gi tr 255 c xa 1 cch t ng sau khi mi im c calib. Cc im la bn c th c thit lp cc thi im ring nhng c 4 im phi c calib. V d: 1. Thit lp mt la bn in t, ch hng Bc. Ghi gi tr 255 cho thanh ghi 15. Chn calibrating ( chn 5 ) mc thp.
1. Thit lp mt la bn in t, ch hng ng. Ghi gi tr 255
cho thanh ghi 15. 2. Thit lp mt la bn in t, ch hng Nam. Ghi gi tr 255 cho thanh ghi 15. 3. Thit lp mt la bn in t, ch hng Ty. Ghi gi tr 255 cho thanh ghi 15. Chn calibrating ( chn 5 ) mc cao. Pin method: Chn s 6 c s dng chnh la bn. Ng vo calibrate ( chn s 6 ) c in tr ko ln ngay trn bo mch v c th ngt ra sau khi chnh. chnh la bn bn ch phi ly chn calibrate mc thp v sau li mc cao ln na cho mi im chnh trong 4 im ng,Ty,Nam,Bc. 1 ci kha n gin a chn 6 xung 0v ( ni t )l c. Cc im la bn c th c thit lp cc thi im khc nhau nhng c 4 im phi c chnh. V d: 1. Thit lp mt la bn in t, ch hng Bc. Nhn 1 thi gian ri nh switch. Chn calibrating ( chn 5 ) mc thp.
5
2. Thit lp mt la bn in t, ch hng ng. Nhn 1 thi gian ri nh switch. 3. Thit lp mt la bn in t, ch hng Nam. Nhn 1 thi gian ri nh switch. 4. Thit lp mt la bn in t, ch hng Ty. Nhn 1 thi gian ri nh switch. Chn calibrating ( chn 5 ) mc cao. Vic chnh phi c thc hin ng 4 bc, mi bc cho 1 im chnh ca la bn ng,Ty,Nam,Bc. Cc phin bn trc y din t tng bc ca vic chnh v bn c th quay li v lm cc im li 1 ln na, c 5 bc hoc nhiu hn. Ch vic c hu ht t 1 im l c s dng. Phin bn 14 hat ng han tan khc. Bc1: ( ko chn 6 xung 0v hoc ghi gi tr 255 vo thanh ghi 15) thit lp cu trc thanh ghi ban u v thu thp d liu thit lp th 1. Cc bc sau ch l thu thp d liu. Sau n bc th 4, b x l cc tng pht ra v lu tr trong EEPROM gi tr chnh bn trong. Khi bn thc hin bc 1, chn 5 mc thp. Sau bc 4 chn 5 li mc cao. Bn c th kt ni LED t chn 5 ln 5v vi in tr 390 ohm xc nh vic chnh. N s mc cao ( LED tt ) trc khi bn bt u.