EXPERIMENT NO.

1 SINGLE STAGE CE AMPLIFIER

I. INTRODUCTION: The analysis and design of a transistor amplifier requires knowledge of both the AC and DC response of the system. In actuality, the improved output AC power level is the result of a transfer of energy from the applied DC supplies. In the DC analysis of amplifiers, the proper biasing is determined. Biasing is very important in amplifier design as it establishes the correct operating point of the transistor amplifier ready to receive signals, thereby reducing any distortion to the output signal. The operating point is called the quiescent point, or simply the Q point. In the AC analysis, the actual gain of the amplifier is computed. The most common circuit configuration for an NPN transistor is that of the Common Emitter Amplifier. The Common Emitter Voltage Divider Bias Amplifier circuit is shown below. This type of biasing arrangement uses two resistors as a potential divider network and is commonly used in the design of bipolar transistor amplifier circuits. This method of biasing the transistor greatly reduces the effects of varying Beta, ( ) by holding the Base bias at a constant steady voltage level allowing for best stability.

Figure 1. Common Emitter VDB Amplifier To compute for the DC values of current and voltages, use: IB = Eth VBE Rth + ( + 1)RE where Eth = Vcc( R2) and Rth = R1//R2 R1 + R2 IC = IB IE = IC + IB VCE = VCC Ic(RC + RE) ICSAT = VCC RC+RE

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In the AC analysis of amplifiers, the circuit is first converted to a suitable model for easy analysis, like the re model. ` Figure 2. CE VDB Amplifier re model To compute for the input impedance Zi and output impedance Zo, use: Zi = R1//R2//re Zo = RC//ro or Zo = RC if ro10RC Where: re = 26 mV/ IE (DC) The no load voltage gain is computed as: AVNL = - RC/re if ro10RC and ro is ignored And as AVNL = -RC//ro if ro is considered re In the presence of an AC source with corresponding internal resistance, Rs and load connected at the output, the amplifier voltage gain differs. The computation becomes: AVL = input loading factor,ILF X No load voltage gain, AVNL X output loading factor,OLF Or that would be, AVL = Zi . (Rc) . RL Zi+Rs re RL+Zo because of the effect of the loading at the input and output of the amplifier. II. GENERAL OBJECTIVE: To develop an understand of the DC and AC operations of a single-stage CE VDB Amplifier and design such amplifiers under certain constraints

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EXPERIMENT NO. 1 SINGLE STAGE CE AMPLIFIER (PART 1- PRELAB)

______________________________________________________________________ NAME (leader): SECTION: GROUP NO.: II-1. SPECIFIC OBJECTIVES: 1. Perform theoretical DC signal analysis to a single-stage CE VDB amplifier. 2. Perform theoretical AC signal analysis to a single-stage CE VDB amplifier. III. EQUIPMENTS AND MATERIALS NEEDED: Calculator Pen IV. PROCEDURE: 1. Consider a single stage CE VDB Amplifier below, assume that = 150. NOTE: Transistors of the same type and part number will have large variations in their Beta value. For example, the BC107 NPN Bipolar transistor has a DC current gain Beta values of between 110 and 450 (data sheet value) this is because Beta is a characteristic of their construction and not their operation. DATE PERFORMED: DATE SUBMITTED: INSTRUCTOR:

VCC 10V R1 10k C1 R6 620 1F 100mVrms 1kHz 0 Q1 2N3904 R3 2.2k R4 1k C3 10F R2 3.3k C2 1F R5 10k

V1

Figure 3. CE VDB amplifier with source and load resistance

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2. Calculate the following: A. DC values of: IB, IC, IE, VCE, VB, VC, VE, VBE and VBC. Record your answers in table 1A. B. Zi, Zo and the loaded Voltage gain of the circuit (with source at the input and load at the output). Record your answers in table 1B. V. DATA AND RESULTS: Table 1A. Single Stage CE VDB Amplifier DC Analysis Ib Vb Vce Ic Vc Vbe Ie Ve Vbc Table 1B. Single Stage CE VDB Amplifier AC Analysis, loaded condition Zi Zo AVL SOLUTION:

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EXPERIMENT NO. 1 SINGLE STAGE CE AMPLIFIER (PART 2 - LAB PROPER)

NAME (leader): SECTION: GROUP NO.: II-2. SPECIFIC OBJECTIVES: 1. Construct a single stage CE VDB Amplifier in a breadboard. 2. Measure the AC and DC values of the single stage CE VDB Amplifier parameters using laboratory equipments. III. EQUIPMENTS AND MATERIALS NEEDED: Multitester Breadboard Function generator DC source, 10 V Transistor: 2N3904 W Resistors: 600, 10k , 2.2k, 3.6 k, 1 k, 10 k Capacitor: 0.47uF, 10uF, 2.2pF IV. PROCEDURE: 1. Connect the single stage CE VDB Amplifier below. Figure 4. CE VDB DATE PERFORMED: DATE SUBMITTED: INSTRUCTOR:

amplifier with source and load 3. Measure the following: A. DC values of IB, IC, IE, VCE, VB, VC, VE, VBE and VBC. Record your answers in table 1C.

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B. Vin, Vout and the loaded Voltage gain of the loaded circuit (with source at the input and load at the output). Record your answers in table 1D. Note: the ohmmeter cannot be used to measure the small signal ac input and output impedance since the ohmmeter operates in the dc mode.

V. DATA AND RESULTS: Table 1C. Single Stage CE VDB Amplifier DC Analysis Ib Vb Vce Ic Vc Vbe Ie Ve Vbc Table 1D. Single Stage CE VDB Amplifier AC Analysis, loaded condition Vs VL AVL

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EXPERIMENT NO. 1 SINGLE STAGE CE AMPLIFIER (PART 3 DESIGN/SIMULATION)

NAME(leader): SECTION: GROUP NO.: II-3. SPECIFIC OBJECTIVES: 1. Construct a single stage CE VDB amplifier using multisim 11 student edition software. 2. Troubleshoot some circuit problems related to CE VDB amplifier using multisim 11 student edition software. 3. Design a CE VDB amplifier under certain constraints using multisim 11 student edition software. III. EQUIPMENTS AND MATERIALS NEEDED: 1 PC with multisim 11 - student edition installed Printer IV. PROCEDURE: 1. Refer to the specification sheet to complete table 1E. Note: hie = re, hfe = and hoe = 1/ro 2. Design a single stage CE VDB using N3904 with the following specifications: Rin = 300 ohms Av = 150 Complete table 1F. 3. Connect the circuit design using multisim and observe the input and output voltages to verify if the specification is met. Complete table 1G. DATE PERFORMED: DATE SUBMITTED: INSTRUCTOR:

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V. DATA AND RESULTS Table 1E. N3904 specifications Hie

hfe

hoe

Table 1F. Single Stage CE VDB Amplifier Design R1 C1 R2 C2 Rc Ce Re Vcc Table 1G. Voltage gain of the Single Stage CE VDB Amplifier Design Input voltage, Vin Output voltage, Vout Voltage gain, Av

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EXPERIMENT NO. 1 SINGLE STAGE CE AMPLIFIER

NAME: SECTION: GROUP NO.: VI. CONCLUSION: NOTE: Base your conclusion on the specific objectives stated in parts 1, 2 and 3 of the experiment. Part 1. ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ Part 2. ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ Part 3. ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ VII. BIBLE VERSE: Instruction: Write a bible verse below which you think guided you in finishing the task given to you by your group or your instructor. ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ DATE PERFORMED: DATE SUBMITTED: INSTRUCTOR:

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