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A Voltage-Mode PWM Buck Regulator With End-Point Prediction

Man Siu, Philip K. T. Mok, Senior Member, IEEE, Ka Nang Leung, Member, IEEE, Yat-Hei Lam, Student Member, IEEE, and Wing-Hung Ki, Member, IEEE

AbstractThe end-point prediction (EPP) scheme for voltage-mode buck regulators is proposed. Internal nodal voltages of the regulator controller are predicted and set automatically by the proposed algorithms and circuits. The settling time of the regulator can therefore be signicantly reduced for faster dynamic responses, even with dominant-pole compensation. Proven experimentally by a voltage-mode buck regulator implemented in a 0.35- m CMOS technology, the reference-tracking speed using the EPP scheme is faster than the conventional buck regulator by about six times. Index TermsAdaptive supply, buck regulator, dominant-pole frequency compensation, reference tracking.

I. INTRODUCTION

DAPTIVE power supply is an effective power-management solution for performance-power optimization in both digital and mixed-signal systems [1][10]. Therefore, switched-mode regulators with fast reference tracking to provide fast change of regulated supply voltages are becoming important for future integrated circuit (IC) systems [6]. The pulsewidth-modulated (PWM) switched-mode regulator is well-accepted in many mixed-signal systems, as the switching period is xed and can be designed so that switching noise will not seriously degrade the signal-to-noise ratio of mixed-signal systems. However, PWM regulators generally have slower reference tracking due to the large off-chip compensation capacitors for the regulators stability. As a result, extensive parametric design on power stage and compensation network is generally required to improve the tracking speed, and therefore the robustness of this approach is not high. In this paper, a simple and efcient voltage-mode control scheme, end-point prediction (EPP), is proposed. Internal nodal voltages of the feedback controller are predicted and set automatically by the proposed algorithms and circuits. Therefore,
Manuscript received March 22, 2005; revised June 22, 2005. This work was supported by the Research Grant Council of Hong Kong SAR Government under Project HKUST 6150/03E. This paper was recommended by Associate Editor S. Banerjee. M. Siu was with Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong. She is currently with Fujitsu Microelectronics Pacic Asia Ltd., World Commerce Centre, Tsim Sha Tsui, Hong Kong (e-mail: eesman@ee.ust.hk). P. K. T. Mok, Y.-H. Lam, and W.-H. Ki are with Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong (e-mail: eemok@ee.ust.hk; hylas@ee.ust.hk; eeki@ee.ust.hk). K. N. Leung was with Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong. He is currently with Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong (e-mail: knleung@ee.cuhk.edu.hk). Digital Object Identier 10.1109/TCSII.2005.862024

Fig. 1. Generic voltage-mode PWM buck regulator.

the settling time of the converter can be signicantly reduced for faster dynamic responses. The proposed EPP scheme will be demonstrated and proven by a voltage-mode buck regulator. Problems on the slow tracking speed of conventional buck converter will rstly be addressed in Section II, and then the proposed EPP scheme will be introduced in Section III with theoretical analysis and required circuit implementation. The improved tracking speed will nally be proven by experimental results included in Section IV. II. TRACKING SPEED OF VOLTAGE-MODE BUCK REGULATOR A generic voltage-mode PWM buck regulator to provide a from an unregulated voltage is regulated voltage shown in Fig. 1. The power stage is formed by two power tranand a ltering capacsistors (MP and MN), an inductor . The error amplier compares the reference voltage itor with scaled generated by and . Thus, (1) . An error voltage is then where in a generated to PWM controller to determine duty cycle switching period for voltage regulation, according to [11]. A buck regulator operated in continuous-conduction mode (CCM) has a conversion relationship given by (2) where and are upper and lower bounds of the ramp signal is changed, in the PWM controller. As in Fig. 2, when is changed by changing with different according to is connected at (2). Since a large compensation capacitor

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Fig. 2. Transient response at reference tracking. Fig. 4. Fixed-frequency VCO with supply-controlled ramp and clock signals amplitude.

there is nearly no large-signal transient at tracking is much improved. B. Loop Gain

, the reference

Stability of power converters is studied by loop-gain analysis. of a voltage-mode buck converter in The open-loop gain CCM is given by [11], [12] (5) where and are the transfer functions of the error amis plier and power stage, respectively. As used in the proposed EPP scheme, the loop gain of the proposed structure is given by (6) The stability of the voltage-gain buck regulator is independent . Stability of the proposed buck regulator can be achieved of by dominant-pole compensation. A low frequency pole, which ensures complex poles from the power stage located after the unity-gain frequency of the loop gain, is created at the erroramplier output. C. Circuit Implementation Advanced circuit implementation is needed to achieve the EPP scheme successfully. The circuit implementation involves designs of voltage-controlled oscillator (VCO) to provide a , and a constant switching ramp signal with and to frequency, voltage summation circuit to sum form , and over-current protection circuit. The circuit designs of these three important building blocks are introduced below. 1) VCO: The VCO design is the key of the EPP scheme. to The ramp signal amplitude needs to change from with a constant switching frequency. The proposed VCO design is shown in Fig. 4. When the resistor is designed as , as stated in (1), is ratio given by (7) This current is copied by the current mirror into two current branches. One is to charge a capacitor to form the ramp

Fig. 3. Proposed buck regulator with EPP.

the error-amplier output for dominant-pole compensation, the is slow. large-signal response of is poor and the change of III. PROPOSED EPP SCHEME The proposed voltage-mode buck converter with the EPP scheme is shown in Fig. 3. A voltage adder is used to sum and to form , the error-amplier output voltage , a node inputting into the PWM controller. In this case, connected with a large compensation capacitor, needs not to experience large voltage transients during reference tracking. A. Structure and Operational Principle From (1) and (2), the required to determine is given by (3) is designed such that When of and is given by , the relation (4) Referring to Fig. 3, the error-amplier output voltage is . During reference tracking, and will equal to will change rapidly while the error-amplier output voltage be constant. However, the relationship stated in (2) occurs only with ideal power transistors and ideal inductor. As a result, there during tracking in practice, and this is a small change on will be shown by experimental results in the next section. Since

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Fig. 5. Inverted linear regulator to generate V independent of current level.

signal, while another is converted to . The hysteretic comand parator compares the amplitude of the ramp signal with to turn on and off the nMOS transistor that is connected in to discharge the ramp voltage back to . The parallel with is given by charge stored in (8) where is the switching frequency of the designed buck converter, and hence (9) to give the relationship of switching frequency of (10) and From (8), the switching frequency is independent of is xed by the design of and , and the ramp amplitude and . changes between is set to about 0.2 V so that V In the design, to allow the error amplier to operate in the high-gain region. that is independent of injected current Moreover, to provide , an inverted linear regulator is used, as shown in Fig. 5. The output voltage is dened by the input of the error amplier, while regulation is continuously achieved by negative feedback. Since there are two high-impedance nodes, Miller compensation , can is used. The design of the compensation capacitor used, be evaluated by [13] (11) where and are transconductance of the error amplier and the nMOS transistor, respectively, at minimum , and is the worst-case parasitic capacitance at the drain of the nMOS transistor. Since this circuit is to provide a stable DC voltage, provides more stable the speed is not important and large operation. 2) Voltage Summation Circuit: The proposed current-mode voltage summation circuit is shown in Fig. 6. The input is from the error-amplier output, while at is generated is converted into given by by the circuit in Fig. 5. Thus, , and is copied to another current branch to by form (12)

Fig. 6. Current-mode voltage adder.

Fig. 7. Inductor-current sensing circuit for over-current protection [14].

3) Over-Current Protection Circuit: During reference may change to a higher voltage. A higher output tracking, current is needed to charge the output ltering capacitor and an over-current protection circuit is required to avoid damages of the buck regulator. The over-current protection circuit used is shown in Fig. 7. Instead of using a series sensing-resistor , the drain current of power to sense the inductor current pMOS transistor is sensed during the on-period for better of both power pMOS power-conversion efciency. The ) using a highly-acand sensing pMOS are equal (i.e., curate voltage clamping circuit [14]. The sensed current is thus proportional to determined by the transistor ratio. In the proposed design, a ratio of 2000 is used. With a small bias is approximately equal to and inputs current , into control logics of the PWM controller. IV. EXPERIMENTAL RESULTS A voltage-mode PWM buck converter with the EPP scheme has been implemented in AMS (Austria Mikro System Group, Austria) double-poly triple-metal 0.35- m CMOS technology. The micrograph is shown in Fig. 8, and the chip area is m m, including the chip area of test pads.

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Fig. 8. Micrograph of the buck regulator with EPP control.

Fig. 10. Measured response of regulated output voltage (V ) at reference tracking. (a) Step up. (b) Step down.

Fig. 9. Measured ramp signals of the buck regulator with EPP by the proposed VCO in Fig. 4 at different input voltages.

The measured ramp signals at V and V are shown in Fig. 9. The preset is 0.2 V and is set to 1/3. is 1.2 V and 1.5 V, respectively, which agrees Therefore, with the experimental results well using the stated algorithm. A comparison of reference tracking is made using two voltage-mode buck converters. One uses conventional control, while another uses the EPP scheme. As a remark, all circuits are the same in the same technology except the added circuits for the EPP control. The input voltage of the measurement is 2.4 V at 500 kHz. The load current is kept at 160 mA by electronic load. The reference voltage is then changed from 0.1 to 0.7 V from 0.3 to 2.1 V (noted that ). Fig. 10 to provide shows the reference tracking of both positive and negative for both of the conventional and the EPP edges of controls. The tracking speed by EPP, which is measured at less by 10%, is faster than the conventional control by about 6 times.

Fig. 11 shows (input of the PWM controller) for the conventional and the EPP controls. As predicted, is slowed down slowly. by the large compensation capacitor to generate new quickly. However, in EPP changes much faster to provide It is noted that there is a small change on due to the nonideal power transistors and inductor on nonzero on-resistance and series-equivalent resistance. Since the change is small, it does not degrade the tracking speed signicantly. V. CONCLUSION Fast reference tracking feature is very important for systems powered up by adaptive supply voltages. Voltage-mode PWM power converters compensated by dominant-pole approach has slow dynamic response, which is mainly limited by the large off-chip compensation capacitor. In this paper, this problem is solved by the proposed End-Point Prediction scheme and circuit implementation. With the EPP scheme, the simplicity and the robustness of a voltage-mode buck converter with dominantpole compensation are retained, while the dynamic response is greatly improved by just an additional adder circuit. Moreover, a buck converter using the proposed idea and implementation method has been designed and fabricated. Measurement results support the proposed idea.

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Fig. 11. Measured responses of the error-amplier output (V ) at reference tracking. (a) Conventional. (b) EPP.

ACKNOWLEDGMENT The authors would like to thank S. F. Luk and F. Kwok for their technical support.