1. Cc ng ngun nui. C 3 chn: Chn 40 - ni ngun nui, c gi tr +5V, k hiu l +Vcc. Chn 1, 20: ni t. 2. Cc ng a ch, trng thi.

Tng cng c c 20 chn a ch, l cc chn 2 16, 35 - 39 C 5 chn kt hp chn thng tin trng thi trn ng a ch, l: Chn 35 -38: A19_A16/S6-S3 Multiplex: Kt hp v chen thng tin trn 1 knh truyn tin: 4 bit a ch cao hoc 4 tn hiu trng thi ch th hot ng hin ti ca CPU. Cc trng thi nh sau: S4, S3 cho bit thanh ghi no ang c s dng thm nhp b nh. S4 0 0 1 1 S3 0 1 0 1 Thanh ghi c truy xut D liu ES Ngn xp SS M lnh CS D liu DS

S5 ch trng thi c Interrupt (Interrupt Enable). S6 lun lun l 0 /S7 - Bus high enable (chn 34). V 8086 c bus d liu ngoi 16 bit, do vy cn phn bit c byte cao v byte thp ca d liu. thc hin nhim v ny B E H kt hp vi A0 cung cp cc thng tin nh sau:
B E H B E H

0 0

A0 0 1

Trng thi bus d liu Truyn 16 bit d liu trn D0-D15 Truyn mt byte phn cao ca bus d

1 1

0 1

liu D8-D15 Truyn mt byte phn thp ca bus d liu D0-D7 D tr (bus d liu ngh)

Bng 2.6 Cc trng thi ca chu k BUS DT/ R SS0 Chc nng chu k I /M O bus 1 0 0 Nhn lnh 1 0 1 c b nh 1 1 0 Ghi b nh 1 1 1 Th ng (Passive) 0 0 0 Bo nhn lnh 0 0 1 ngt 0 1 0 c cng I/O 0 1 1 Ghi cng I/O Dng (Halt) 3. Cc ng d liu C 8 ng d liu. gm t chn 9-16: Multiplex - va a ch va d liu. 4. Cc ng iu khin a ch/d liu C 7 ng iu khin a ch d liu, l cc chn: 25-29, 32, 34. c dng iu khin v bo trng thi di chuyn ca thng tin trn bus d liu v a ch. * Chn 25: ALE (Address Latch Enable- cht a ch) chn ra mc cao xc nhn c a ch ang n nh trn bus a ch. * Chn 26 DEN (Data Enable) Li ra 3 trng thi. mc

thp tn hiu cho php truyn d liu gia b vi x l v B nh/Vo ra. * Chn 27 DT/R (Data Transmit/Receive) Li ra 3 trng thi, dng xc nh chiu truyn s liu. * Chn 28 IO/M (Input Output/Memory) Li ra 3 trng thi xc nh bus a ch c ni vi IO hay Memory. * Chn 29 WR (Write) Li ra 3 trng thi xc nhn b VXL ghi thng tin ln IO hoc Memory. * Chn 32 RD (Read) Li ra 3 trng thi tch cc m. Xc nhn vic c d liu. * Chn 34 SS0 (Status Line 0) Li ra 3 trng thi. Kt hp vi IO/M v DT/R cho thng tin v chu k bus 5. Cc ng iu khin ngt C 5 ng iu khin ngt, l cc chn 17, 18, 21, 23 v 24 cho php dng hot ng ca MP. * Chn 17 NMI (Non Maskable Interrupt) Ngt khng che mt n - tn hiu vo hiu lc mc cao dng ngt qu trnh x l ca CPU. L tn hiu khng th b b qua (b che mt n) bi CPU. * Chn 18 INTR (Interrupt Request) Tn hiu vo ngt qa trnh x l ca CPU, c th che c (masakable) tc CPU c th b qua bng s iu khin ca phn mm. * Chn 24 INTA (Interrupt Acknowledge) Tn hiu ra bo MP nhn 1 lnh ngt. * Chn 21 RESET. Khi ng li MP. * Chn 23 TEST (Test Interrupt) Tn hiu vo. Khi MP ang thc hin lnh WAIT th MP s kim tra chn TEST. Nu TEST=1 th my tip tc ch cho n khi TEST=0. 6. Cc chn iu khin thao tc C 5 chn iu khin thao tc. * Chn 19: CLK (Clock Input) Tn hiu ng h ch,

ng b mi hot ng ca MP. * Chn 22: READY l tn hiu tr li ca I/O hoc MEMORY bo chu k chuyn s liu hon tt. * Chn 31 HOLD v 30 HOLDA (Hold Request) Bo c yu cu lm ch bus t bn ngoi. Khi MP tip nhn yu cu ny th a ra tn hiu HLDA (Hold Acknowledge). * Chn 33 MN/MX (Minimum/Maximum Mode) Tn hiu li vo bo MP lm vic mode ti a (0) hay ti thiu (1)