Handouts Stanford

1
STANFORD UNIVERSITY
Department of Electrical Engineering
Prof. Boris Murmann
EE214: Analog Integrated Circuit Design
- Autumn 2007/08 -
http://eeclass.stanford.edu/ee214/
Table of Contents
Introduction 3
Lecture 1 CMOS Technology, Long Channel MOS Model 10
Lecture 2 Common Source Amplifier 16
Lecture 3 Technology Characterization: gm/ID 30
Lecture 4 Technology Characterization: fT, gm/gds 42
Lecture 5 gm/ID-based Design 56
Lecture 6 Extrinsic Capacitance 68
Lecture 7 Miller Approximation, ZV Time Constant Analysis 85
Lecture 8 Electronic Noise 96
Lecture 9 Electronic Noise (Continued) 109
Lecture 10 Backgate Effect, Common Gate Stage 118
Lecture 11 Common Drain Stage 130
Lecture 12 Differential Pair 141
Lecture 13 Current Mirrors, Offset Voltage 152
Lecture 14 Process Variations, Feedback 165
Lecture 15 Fully Differential Amplifiers, SC Circuits 175
Lecture 16 Stability, Analysis of Feedback Circuits 185
Lecture 17 Loop Gain Simulation 197
Lecture 18 Two-Stage OTA 209
Lecture 19 Compensation, Noise in Feedback OTAs 218
Lecture 20 OTA Design Considerations 233
Lecture 21 Step Response 258
Lecture 22 Slewing 275
Lecture 23 Feedback and Port Impedances, OTA Variants 285
Lecture 24 Single Ended OTAs, Output Stage Examples 298
Lecture 25 Supply Insensitive Biasing 307
Lecture 26 Bandgap Reference 317
Lecture 27 Bandgap Reference (Continued) 323
Lecture 28 Technology Scaling 332
Lecture 29 Class Summary 348
2
3
EE214
Analog Integrated Circuit Design
Boris Murmann
Stanford University
murmann@stanford.edu
Copyright © 2007 by Boris Murmann
B. Murmann EE 214 Introduction 1
A Few Words About Your Instructor
• Assistant Professor in EE since 2004

• PhD, UC Berkeley 2003
– Digitally assisted A/D conversion
– Use "minimalistic" analog circuits (low power, fast)
– Correct errors using digital post-processor
• ~ 4 years work experience in IC industry
– Mixed signal IC design, low power, high voltage
• Current research
– Digital correction techniques for data converters
– Sensor interfaces
– Circuit design in new technologies
• Post-CMOS devices, organic devices

4
EE214 Basics (1)
• Teaching assistants
– Mohammad Hekmat, Bob Wiser, Ross Walker
• Administrative support
– Ann Guerra, CIS 207
• Lectures are televised
– But please come to class to keep the discussion interactive!
• Web page: http://eeclass.stanford.edu/ee214
– Check regularly, especially bulletin board
– Register for online access to grades and solutions
• Only enrolled students can register; we manually control the
access list based on Axess data
EE214 Basics (2)
• Required text
– Analysis and Design of Analog Integrated Circuits, 4th
Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001. (On
reserve in Engineering Library)
• Course prerequisites
– EE101B or equivalent
– Basic device physics and models
• PN junctions, MOSFETs, BJTs
– Basic linear systems
• Frequency response, poles, zeros
– Some exposure to a circuit simulator, basic Unix commands
– May consider concurrent enrollment in EE114X to brush up
on the above (primarily for undergraduates)

5
Assignments
• Homework (20%)
– Handed out on Mondays, due following Monday in class
– Late policy
• Score drops 0.5 dB per hour after deadline
– Lowest HW score will be dropped
– Policy for off-campus students: Fax/email to SCPD before
deadline stated on handout
• Midterm Exam (30%)
• Project (20%)
– Design of an amplifier using HSpice (no layout)
– Work in teams of two
• OK to discuss with other teams, but no file exchange!
• Final Exam (30%)
Honor Code
• Please remember you are bound by the honor code

– I will trust you not to cheat
– I will try not to tempt you
• But if you are found cheating it is very serious
– There is a formal hearing
– You can be thrown out of Stanford
• Save yourself and me a huge hassle and be honest
• For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/
honorcode.pdf

6
Be Reasonable When Asking TAs
• The TAs will not give you "the answer times two"…
• They will also NOT debug your Spice deck
– Figuring out what's wrong with your circuit is an essential
component of this class
Circuit Simulation
• We will HSpice for circuit simulation

– You can use other tools at "own risk"
– "CAD Basics" document and example simulation files are provided
on course web site and in course directory
• Plot HSpice results using Matlab ("HSpice Toolbox")
– Toolbox is installed in course directory
• See "CAD Basics" document for setup info
– Can download toolbox from Mike Perrott's homepage (MIT)
• EE214 Technology
– 0.35μm CMOS
– BSIM3v3 models provided on web site and in course directory
• First review session (this week) will focus on simulation basics

7
The Spice Monkey Problem (1)
• What most people know

– Even a very large number of
monkeys randomly
arranging characters will
never manage to write an
interesting book
• What some people tend to
forget
– Even a very large number of
"Spice Monkeys" randomly
tweaking circuits will never [Courtesy Isaac Martinez]
manage to design a robust,
optimized IC
The Spice Monkey Problem (2)

• Simply put
– Spice is nothing but a "calculator" that lets you evaluate and
test your ideas
– There is no need to simulate anything unless you already
know the (approximate) answer!
– Must always be aware of modeling limitations
• Especially in the integrated circuits arena, uneducated, purely
simulator driven design can be costly
– Mask sets cost up to $2 Million (90 nm production)
– Turnaround time is on the order of months
– If your chip doesn't work, you cannot simply send the
customer a "patch"…

8
Analysis versus Design

• Unlike common perception, analog circuit analysis and design is
not "black magic"
• Circuit analysis
– The art of decomposing a circuit into manageable pieces
– Based on the simple, but sufficiently accurate model
• "Just-in-time" modeling; do not use a complex model unless
you know why it's needed…
– One circuit ⇒ one solution
• Circuit design
– The art of synthesizing circuits based on experience from
extensive analysis
– One set of specifications ⇒ Many solutions
– Design skills are best acquired through "learning by doing"
• This is why we'll have a design project…
Learning Goals
• Develop deeper understanding of MOS device behavior relevant

to analog design
• Develop a feel for limits and tradeoffs in analog circuits (speed,
noise, power dissipation)
• Learn to bridge the gap between complex device
models/behavior and basic hand calculations
– Design using look-up tables, "gm/ID methodology"
• Develop a systematic, non-spice-monkey design style
• Solidify the above aspects in a hands-on design project
– Design and optimization of a high performance feedback
amplifier used in many industrial circuits/applications

9
Preview - Design Example of Lecture 20
Cf
Cs CL
- +
Vsd Vid Vod
+ -
Cs
CL
M4a,b
Cf
M1a,b
Specs:
Loop bandwidth (fc) = 200MHz
Phase margin = 75 degrees
M3a,b M2a,b DR = 72dB
Closed-loop gain =2
Static gain error < 0.5%
Course Topics
• CMOS technology and device models

• Electronic noise
• Single-stage amplifiers
• Current mirrors, active loads
• Differential pairs
• Operational transconductance amplifiers (OTAs)
• Feedback, stability and compensation
• Temperature and supply independent biasing

10
Lecture 1
CMOS Technology
Long Channel MOS Model
Boris Murmann
Stanford University
B. Murmann EE 214 Lecture 1 1
Overview
• Reading
– 2.8 (MOS fabrication), 2.9 (Active MOS devices)
– 2.10.1 (Resistors), 2.10.2 (Capacitors)
– 1.1, 1.5.0, 1.5.1, 1.5.2, 1.5.3 (Large signal MOS model)
• Introduction
– In this first lecture, we will cover some of the background
that positions EE214 as an introductory course on circuit
design using CMOS technology. In the lectures to come, we
will focus on the problem of amplifier design as a vehicle to
establish a set of considerations that apply to more complex
circuits and also other technologies. At first, we will review
the "long channel model" of a MOS transistor. Driven by
circuit examples, we will later augment this simple model to
include additional effects that are relevant in practice.

11
The Big Picture
• Most modern electronic information processing systems rely on

amplification of "small" physical signals
– E.g. signal from RF antenna, disk drive head, microphone, …
• EE214 uses amplifiers as a vehicle to teach you the basics of
analog integrated circuit analysis and design
– Material forms basis for other and/or more complex circuits
Technological Progress
Vacuum Tube Transistor Modern Discrete

1906 1947 Transistors
Integrated Circuit
1958 Modern
CMOS

12
45nm CMOS (Intel)
Steve Cowden
THE ORGONIAN
July 2007
Economics
[European
Nanotechnology
Roadmap]

13
Future Applications
Discrete vs. Integrated Circuits
Discrete Audio Amplifier Integrated CMOS Audio Amplifier
• Minimize transistor count • "Unlimited" number of transistors

• Devices usually don't match • Devices match well
• Arbitrary resistor values • Keep resistors < 10…100k
• Capacitors 1pF…10mF • Keep capacitors < 10…50pF

14
Modern Integrated Circuit Technologies
Parameter CMOS Si BJT SiGe BJT

Device Speed High High High
Noise Poor Good Good
Transconductance Poor Good Good
Intrinsic gain Poor Better Best
• Why use CMOS for analog integrated circuits?

– Low cost, driven by high volume digital ICs
– Integration with high density digital circuits
• BiCMOS tends to be expensive
Basic MOS Operation (1)
0V VD (>0V)
0V
0V
• With zero voltage at the gate, device is "off"

– Back-to-back reverse biased pn junctions

15
Basic MOS Operation (2)
>0
• With a positive gate bias applied, electrons are pulled toward

the positive gate electrode
• Given a large enough bias, the electrons start to "invert" the
surface (p→n); a conductive channel forms
– Magic "threshold voltage" Vt (more later)
Basic Operation (3)
ID=?
>0
VDS>0
• If we now apply a positive drain voltage, current will flow

• How can we calculate this current as a function of VGS, VDS?

16
Lecture 2
Common Source Amplifier
Small-Signal Model
Boris Murmann
Stanford University
Overview
• Reading
– 3.0 (Amplifier basics), 3.1 (Model selection)
– 3.3.2 (Common source amplifer)
– 1.6.0 - 1.6.5 (Small signal MOS model)
• Introduction
– Today we'll complete our derivation of the basic long-
channel MOSFET I-V characteristics. As a next step, we'll
use this simple model to construct our first amplifier – a
common source stage. Looking at its transfer function, we'll
find that treating signals as "small" with respect to the bias
conditions allows us to linearize the circuit. Next, we
generalize this approach and develop a more universal
"plug-and-play" small-signal model for MOS devices that are
biased in the active region.

17
Basic MOS Operation
ID=?
>0
VDS>0
• How can we calculate ID as a function of VGS, VDS?
Assumptions
>0
VDS>0
1) Current is controlled by the mobile charge in the channel. This is a very

good approximation.
2) "Gradual Channel Assumption" - The vertical field sets channel charge,
so we can approximate the available mobile charge through the voltage
difference between the gate and the channel
3) The last and worst assumption (we will fix it later) is that the carrier
velocity is proportional to lateral field (ν = μE). This is equivalent to Ohm's
law: velocity (current) is proportional to E-field (voltage)

18
First Order IV Characteristics (1)
• What we know:
Qn ( y ) = Cox [VGS − V ( y ) − Vt ]
I D = Qn ⋅ v ⋅ W
v = μ⋅E
∴ I D = Cox [VGS − V ( y ) − Vt ] ⋅ μ ⋅ E ⋅ W
First Order IV Characteristics (2)
dV ( y )
I D = Cox [VGS − V ( y ) − Vt ] ⋅ μ ⋅ E ⋅ W E=
dy
I D dy = WμCox [VGS − V ( y ) − Vt ] ⋅ dV
L VDS
I D ∫ dy = WμCox ∫ [VGS − V ( y ) − Vt ] ⋅ dV
0 0
W ⎡ VDS ⎤
I D = μCox (
⎢ GSV − Vt ) − ⎥ ⋅ VDS
L ⎢⎣ 2 ⎥⎦
• For VDS/2 << VGS-Vt, this looks a lot like a linear resistor: I=1/R × V
• Lets plot this IV relationship...

19
Plot of First Order IV Curves
ID
VGS-Vt
VDS
• Something is wrong here...

– Current should never decrease with increasing VDS
• What happens when VDS>VGS-Vt?
– VGD = VGS-VDS becomes less than Vt, i.e. no more
channel or "pinch off"
Pinch-Off
– VGS +
+ VDS –
N N
Qn(y), V(y)
Voltage at the end of channel

y
Is fixed at VGS-Vt
y=0 y=L
• Effective voltage across channel is VGS - Vt

– After channel charge goes to 0, there is a high lateral field
that ‘sweeps’ the carriers to the drain, and drops the extra
voltage (this is a depletion region of the drain junction)
• To first order, current becomes independent of VDS

20
Modified Plot and Equations
Triode Active
Region Region
ID
VGS-Vt
VDS
W ⎡ V ⎤
Triode Region: I D = μCox ⎢(VGS − Vt ) − DS ⎥ ⋅ VDS
L ⎢⎣ 2 ⎥⎦
W ⎡ (VGS − Vt ) ⎤ 1 W
Active Region: I D = μCox
L ⎢⎣(VGS − Vt ) − 2 ⎥
⎦
⋅ (VGS − Vt ) = μCox (VGS − Vt ) 2
2 L
First-Order MOS Model Summary
VDS
1 W
I D ≅ μCox (VGS − Vt )2 ≅
2 L
old "VCCS"
e sh ACTIVE
VGS-Vt hr ...)
b-T
at er
Su re
l
TRIODE
o
(m
I D ≅ μCox
W
L
⎡ VDS ⎤
⎢⎣(VGS − Vt ) − 2 ⎥⎦ ⋅ VDS ≅
Vt VGS

21
Model Accuracy
• The above equations constitute the most basic MOS IV model

– "Long channel model", "quadratic model", "low field model"
• Unfortunately this model doesn't describe modern CMOS
devices accurately
– Pushing towards extremely small geometries has resulted in
very high electric fields
• Some of the assumptions on slide 4 become invalid
• Other second order dependencies arise
• Nevertheless, we will use this simple model in the first few
lectures to develop some basic circuit intuition
– Will fix and refine as we go…
– "Just-in-time" modeling
Let's Build Our First Amplifier
• One way to amplify

– Convert input voltage to current using voltage controlled
current source (VCCS)
– Convert back to voltage using a resistor (R)
• "Voltage gain" = ΔVout/ΔVin
– Product of the V-I and I-V conversion factors

22
Common Source Amplifier
• MOS device acts as VCCS
1 W 1 W
I D = μCox (Vi − Vt )2 Vo = VDD − μCox (Vi − Vt )2 ⋅ R
2 L 2 L
Biasing
• Need some sort of "battery" that brings input voltage into useful
operating region
• Define VOV=VI-Vt, "quiescent point gate overdrive"
– VOV=VGS-Vt with no input signal applied
VO ΔVo
ΔVi
"Signal" VOV
"Bias"
VI

23
Relationship Between Incremental Voltages
• What is ΔVo as a function of ΔVi?

1 W
VO + ΔVo = VDD − μCox (VOV + ΔVi )2 ⋅ R
2 L
1
2
W
[
ΔVo = − μCox R ⋅ (VOV + ΔVi )2 − VOV 2
L
]
1
2
W
[
= − μCox R ⋅ 2VOV ΔVi + ΔVi 2
L
]
2I ⎡ ΔVi ⎤
= − D ⋅ R ⋅ ΔVi ⎢1 + ⎥
VOV ⎣ 2VOV ⎦
• As expected, this is a nonlinear relationship
• Nobody likes nonlinear equations; we need a simpler model
– Fortunately, a linear approximation to the above expression
is sufficient for 90% of all analog circuit analysis
Small Signal Approximation (1)
2I D ⎡ ΔVi ⎤
ΔVo = − ⋅ R ⋅ ΔVi ⎢1 + ⎥
VOV ⎣ 2VOV ⎦
• Assuming ΔVi << 2VOV, we have

2I D
ΔVo ≅ − ⋅ R ⋅ ΔVi
VOV
• If we further pretend that the input voltage increment is infinitely

small, we can find this result directly by taking the derivative of
the large signal transfer function at the "operating point" VI
dVo 2I
= − D ⋅R
dVi V =V VOV
i I

24
Small Signal Approximation (2)
• Graphical illustration:
dVo/dVi
VO
VOV
VI
• The slope of the above tangent is the so called "small signal

gain" of our amplifier
Small Signal MOS Model

• Fortunately we don't have to repeat this analysis for every single
circuit we build
• Instead, we derive a linearized circuit model for the MOS
transistor and plug it into arbitrary circuits

25
Transconductance
• The parameter that relates small signal gate voltage to drain
current is called transconductance (gm), or y21 in two-port
nomenclature
• The transconductance is found by differentiating the large signal
I-V characteristic of the transistor in its operating point
1 W
I D = μCox (VGS − Vt )2
2 L
id ∂I W W
gm = = D = μCox (VGS − Vt ) = μCox VOV
vgs ∂VGS L L
2I D
gm =
VOV
Additional Model Components

• Now that we've decided to move on using "small signal"
approximations, it also becomes easier to refine our model and
make it more realistic
• Let's first take a look at "intrinsic gate capacitance"
– Intrinsic means that these capacitances are unavoidable and
required for the operation of the device
– Note that there are plenty of extrinsic, technology related
capacitances
• We'll talk about some of those later
• When talking about gate capacitance, we must distinguish
several operating regions
– Transistor on
• Triode and active regions
– Transistor "off"
• Subthreshold operation

26
Transistor in Triode Region

G
S W D
L
C GC
C CB
• Gate terminal and conductive channel form a parallel plate

capacitor across gate oxide CGC= WLεox/tox= WLCox
– We can approximately model this using lumped capacitors of size
½ CGC each from gate-source and gate-drain
• Changing either voltage will change the channel charge
• The depletion capacitance CCB adds extra capacitance from
drain and source to substrate
– Usually negligible
Transistor in Active Region
• Assuming a long channel model, if we change the the source

voltage in the forward active region
– The voltage difference between the gate and channel at the
drain end remains at Vt, but the voltage at the source end
changes
– This means that the "bottom plate" of the capacitor does not
change uniformly
• Detailed analysis shows that in this case Cgs=2/3WLCox
– See text, section1.6.2
• In the long channel model for forward active operation, the drain
voltage does not affect the channel charge
– This means Cgd=0 in the forward active region!
• Neglecting second order effects and extrinsic caps, of course

27
Transistor Off
G
S W D
L
C GC
C CB
• There is no conductive channel

– Gate sees a capacitor to substrate, equivalent to the series
combination of the gate oxide capacitor and the depletion
capacitance
• If the gate voltage is taken negative, the depletion region
shrinks, and the gate-substrate capacitance grows
– With large negative bias, the capacitance approaches CGC
Intrinsic MOS Capacitor Summary
Forward
Subthreshold Triode
Active
Cgs 0 ½ WLCox 2/
3 WLCox
Cgd 0 ½ WLCox 0
−1
⎛ 1 1 ⎞
Cgb ⎜⎜ + ⎟⎟ 0 0
⎝ CCB WLCox ⎠
ε Si
CCB = WL
xd

28
Finite dID/dVDS (1)
• In the simple model considered so far, the drain current was

independent of VDS (active region)
• In reality, the drain current has a weak dependence on VDS
Triode Active
Region Region
Finite dID/dVDS
ID
VGS-Vt
VDS
Finite dID/dVDS (2)

• "Channel length modulation" is outdated nomenclature for a
combination of several physical effects (DIBL, SCBE, …) that
cause finite dID/dVDS
• The precise dependence of ID on VDS is very hard to model
– You can convince yourself by looking at the BSIM3 manual
• The simplest and most popular model for hand analysis
assumes that the large signal current ID increases linearly with
VDS and lumps all dependencies into a single "fudge factor" λ
– λ is inversely proportional to channel length; i.e., longer
channels exhibit smaller dID/dVDS
1 W
ID = μCox ( VGS − Vt )2 ( 1 + λVDS )
2 L

29
Small Signal Output Conductance

• From a small signal perspective, finite dID/dVDS translates into an
output conductance that depends on the operating point
Slope = gds
ID
Operating Point
VDS
dI D d ⎡1 W ⎤
g ds = = ⎢ μCox ( VGS − Vt )2 ( 1 + λVDS )⎥
dVDS dVDS ⎣ 2 L ⎦
1 W
= μCox ( VGS − Vt )2 ⋅ λ
2 L
λI D
= ≅ λI D
1 + λVDS
1st Order Small Signal Model (Active Region)
2I D
gm =
VOV
2
C gs = WLCox
3
g ds ≅ λ ⋅ I D
• Sometimes ro=1/gds is used to denote finite output resistance

30
Lecture 3
Common Source Amplifier Performance
Technology Characterization: gm/ID
Boris Murmann
Stanford University
Overview
• Reading
– 1.6.8 (Transit Frequency)
– 1.8 (Weak Inversion)
• Introduction
– Having established some basic modeling tools, we will now
begin to look at the performance of our common source stage:
bandwidth, power dissipation and maximum gain. We'll find that
these metrics are proportionally related to fundamental
performance measures of the MOS device: transit frequency
(gm/Cgs), current efficiency (gm/ID) and "intrinsic gain" (gm/gds) .
After looking at gm/ID in our EE214 0.35-μm technology, we find
that additional modeling is needed to explain the behavior of this
parameter as a function of the gate overdrive VOV. As a first
refinement, we discuss the behavior at subthreshold bias, i.e.
VOV<0.

31
Common Source Amplifier Revisited
• Consider a generic common source stage driven by a "transducer"
vo ( s ) 1
H( s ) = = − gm R ⋅
vi ( s ) 1 + sRi C gs
Performance Measures
• DC voltage gain
¾ ADC specification and R set ADC = − g m R
required gm
• Bandwidth
1 1
¾ Want small Cgs to maximize f −3dB =
bandwidth
2π Ri C gs
• Power dissipation
¾ Want small ID to minimize power P = VDD ⋅ I D
dissipation

32
Device Perspective (1)

• What we really want from our MOS transistor
– Some gm without investing much current (ID)
– Some gm without introducing large Cgs
• To quantify how good of a job our transistor does, we can
therefore define the following "figures of merit"
gm gm
and
ID C gs
• Using long channel MOS equations, we find

gm 2 g m 3 μVOV
= and =
I D VOV C gs 2 L2
• VOV is the "knob" that let's us trade power efficiency (gm/ID) for
speed (gm/Cgs)!
Device Perspective (2)
gm/I D
gm/Cgs
VOV
• Part of your job as a designer is to choose VOV such that

– You get sufficient bandwidth
– And use as little power as possible to accomplish this
• Even though we've come to this graph using a very simple
example, the observed tradeoff tends to hold in general
– Of course, second order considerations will factor in as you
learn more about circuit design…

33
Product
• In cases where we want to get the "best of both worlds", it is

interesting to look at the product of our two figures of merit
g m g m 3μ
⋅ =
I D C gs L2
gm/I D
gm/I D*gm/Cgs
gm/Cgs
VOV
• While this result looks boring, it shows that using smaller
channel lengths improves circuit performance
– Either or both speed and power efficiency
Scaling Impact
• Thanks to "Moore's Law" feature sizes and thus the available
minimum channel lengths have been shrinking continuously
– Lmin decreases roughly 2x every 5 years
– Lmin=10μm in 1970, Lmin=45nm in 2007
• From the above discussion, it is clear that we can exploit
technology scaling in different ways
– Build faster circuits (gm/Cgs), while keeping power efficiency
constant (gm/ID)
• E.g. A/D converter for a disk drive - want to maximize
bandwidth/throughput
– Build more power efficient circuits (gm/ID), while keeping the
bandwidth constant (gm/Cgs)
• E.g. A/D converter for video signals - bandwidth fixed by a
certain standard

34
Transit Frequency (ωT)

• The transit frequency of a transistor has "historically" been
defined as the frequency where the magnitude of the common
source current gain (|io/ii|) falls to unity
• Ignoring extrinsic capacitance, it follows that

g m 3 μVOV
ωT = =
C gs 2 L2
• Incidentally, this metric is identical to the figure of merit we

considered earlier in the context of a CS amplifier…
Transit Frequency Interpretation
• The transit frequency is only useful as a figure of merit in the

sense that it quantifies gm/Cgs
• It does not accurately predict up to which frequency you can use
the device
– At high frequencies, many assumptions in our "lumped"
transistor model become invalid
– Rule of thumb: lumped model is good up to about ωT/5
• At higher frequencies, device modeling becomes more
challenging and many effects depend on how exactly you layout
and connect the device
– These effects are covered in more detail in EE314
– In EE214, we will assume that we "care" only about
frequencies up to ωT/5

35
+ ωmax
• A step into the right direction for quantifying the high frequency
capability of a MOSFET is to look at its power gain with gate
sheet resistance effects included
– The quantity ωmax is defined as the frequency at which the
magnitude of the common source power gain falls to unity
– Also known as "maximum frequency of oscillation"
• Can show that
1 ωT
ωmax =
2 rgateC gd
(more in EE314…)
Intrinsic Gain
• With RL→∞, the basic common source stage achieves its
maximum possible voltage gain or "intrinsic gain"
– This is yet another interesting figure of merit for a transistor
ADC = g m R = g m (RL || ro )
gm
ADC ,max = g m ro =
g ds
1 gm 2
≅ =
λ I D λVOV
• Interestingly, it will turn out that the voltage gain of other, more
complicated circuits (e.g. op-amps) is fundamentally linked to
the intrinsic device gain gm/gds

36
"Level 1" Figures of Merit for Transistors
Long Channel Model
gm 2
=
• Current Efficiency ID V OV
gm 3 μ V OV
• Transit Frequency =
C gs 2 L2
gm 2
• Intrinsic Gain ≅
g ds λ V OV
• Can characterize any technology (MOS, BJT, …) with respect to

these basic quantities
• Big question
– Does the long channel model accurately describe these FOM?
gm/ID Simulation
$ gm/id vs. gate overdrive
.param gs=1
vds d 0 dc 1.5V
vgs g 0 dc 'gs'
mn1 d g 0 0 nch214 L=0.35um W=10um
.op
.dc gs 0.4V 1.2V 10mV
.probe ov = par('gs-vth(mn1)')
.probe gm_id = par('gmo(mn1)/i(mn1)')
.options post brief

.lib './ee214_hspice.txt' nominal
.end

37
Result
40
35 EE214 technology
2/VOV
30
BJT (q/kT)
25
gm/I D [S/A]
20
15
10
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
V [V]
OV
Observations
• Our long channel predication is fairly close for VOV > 150mV
• Unfortunately gm/ID does not approach infinity for VOV → 0
• It also seems that we cannot do better than a BJT, even though
the long channel equation would predict that for 0 < VOV < 2kT/q
≅ 52mV at room temperature
• For further analysis, it helps to identify three distinct operating
regions
– Strong inversion: VOV > 150mV
• Deviations due to short channel effects
– Subthreshold: VOV < 0
• Behavior similar to a BJT, gm/ID nearly constant
– Moderate Inversion: 0 < VOV < 150mV
• Transition region, an interesting mix of the above

38
Subthreshold Operation
• A plot of the device current in our previous simulation:
0
1 10
-1
0.8 10
-2
0.6 10
I D [mA]
I D [mA]
-3
0.4 10
-4
0.2 10
-5
0 10
-0.5 0 0.5 1 -0.5 0 0.5 1
VOV [V] VOV [V]
• Questions:
– What determines the current when VOV< 0, i.e. VGS< Vt?
– What is the definition of Vt?
Definition of Vt
• Vt is defined as the VGS at which the number of electrons pulled

to the surface equals the number of doping atoms
• Seems somewhat arbitrary, but makes sense in terms of surface
charge control

39
Mobile Charge versus VOV

6.E-07
Fixed Charge
5.E-07 Mobile Charge
Total Charge
4.E-07
Charge [C]
3.E-07
2.E-07
1.E-07
0.E+00
-1.0 -0.5 0.0 0.5 1.0
VOV [V]
• Around Vt (VOV=0), the relationship between mobile charge in the

channel and gate voltage becomes linear (Qn ~ Cox[VGS-Vt])
– Exactly what we assumed to derive the long channel model
Mobile Charge on a Log Scale

• On a log scale, we see that there are mobile charges before we
reach the threshold voltage
– Fundamental result of solid-state physics, not short channels
1.E-06
1.E-07
1.E-08
Mobile Charge [C]
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
1.E-14
1.E-15
1.E-16
-1.00 -0.50 0.00 0.50 1.00
VOV [V]

40
BJT Similarity
• We have
– An NPN sandwich, mobile minority carriers in the P region
• This is a BJT!
– Except that the base potential is here controlled through a
capacitive divider, and not directly an electrode
Subthreshold Current
• We know that for a BJT
I C ≅ I S ⋅ eVBE /( kT / q )
• In our case we have

I D ≅ I 0 ⋅ e(VGS −Vt ) /( nkT / q )
• n is given by the capacitive divider

C js + Cox C js
n= = 1+
Cox Cox
where Cjs is the depletion layer capacitance
• In our technology n ≅ 1.5

41
Subthreshold Transconductance
dI D 1 I D ⋅ q g m dI D 1 q
gm = = = =
dVGS n kT I D dVGS n kT
• Similar to BJT, but unfortunately n (≅1.5) times lower
40
35 EE214 technology
30
~1.5x 2/VOV
BJT (q/kT)
25
gm/I D [S/A]
20
15
10
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

42
Lecture 4
Short Channel Effects
Technology Characterization: fT, gm/gds
Boris Murmann
Stanford University
Overview
• Reading
– 1.7 (Short Channel Effects)
• Introduction
– Today, we continue our discussion on gm/ID modeling in a
MOS device. We explain the remaining discrepancies with
the long channel model and then move on to an examination
of gm/Cgs (fT) and gm/gds. In conclusion, we find that the long
channel model cannot accurately predict either performance
metric we care about (gm/ID, gm/Cgs and gm/gds). As a solution
to this problem, we will explore a chart-based design
methodology in the remainder of this course.

43
Re-cap
40
35 EE214 technology
2/VOV
30
BJT (q/kT)
Subthreshold
25 Operation
gm/I D [S/A]
20
?
15
10
?
5
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
V [V]
OV
Moderate Inversion
• In the transition region between subthreshold and strong
inversion, we have two different current mechanisms
Drift (MOS) - ν = μ E
dn kT dn
Diffusion (BJT) - ν = D = μ
dx q dx
• Both current components are always present
– Neither one clearly dominates around Vt
• Can show that ratio of drift/diffusion current ~(VGS-Vt)/(kT/q)
– MOS equation becomes dominant at several kT/q
• One way to close the gap between the two regimes is to work
with a mathematical fit
– Sometimes useful for computer optimization, not so great for
hand analysis…
44
A Curve Fitting Attempt

⎧1 q
⎪ ; VOV → 0
gm 2 q 1 ⎪ m kT
= ≅⎨
I D m kT ⎛ VOV ⋅ q ⎞
2
⎪ 2
1+ 1+ ⎜ ⎟ ⎪V ; VOV → ∞
⎝ mkT ⎠ ⎩ OV
40
EE214 technology
35 2/V
OV
Fitted Equation (m=1.7)
30
[1/V]
25
20
m D
g /I
15
10
0
0 0.1 0.2 0.3 0.4 0.5
V [V]
OV
A Closer Look at Strong Inversion
15
EE214 technology
2/V
OV
g /I [1/V]
10
m D
0
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
VOV [V]
• Long channel model overestimates gm/ID by roughly 10…20%

– Something worth looking into…

45
• Velocity saturation due to high lateral field

• Mobility degradation due to high vertical field
• Vt dependence on channel length and width
• ro = f(VDS)
• …
• We will limit the discussion in EE214 to the first two aspects of

the above list
– Focus on qualitative understanding, since we will not factor
these effects into our hand calculations
Velocity Saturation (1)

• In lecture 2, we assumed that the carrier velocity is proportional
to the lateral E-field, v=μE
• Unfortunately, the speed of carriers in silicon is limited
– At very high fields (high voltage drop across the conductive
channel), the carrier velocity saturates
μE
ν=
E
Approximation: 1+
Ec
E>>Ec ⇒ v=vscl=μEc
E=Ec ⇒ v=vscl/2

46
Velocity Saturation (2)

• It is important to distinguish various regions in the above plot
– Low field, the long channel equations still hold
– Moderate field, the long channel equations become
somewhat inaccurate
– Very high field across the conducting channel – the velocity
saturates completely and becomes essentially constant (vscl)
• To get some feel for latter two cases, let's first estimate the E
field using simple long channel physics
• In the forward active region, at pinch-off, the lateral field across
the channel is
VOV 200mV V
E= e.g. = 0.57 ⋅106
L 0.35μm m
Field Estimates
• In our 0.35μm technology, we have for an NMOS device
m
1.73 ⋅ 10 5
vscl s = 6.2 ⋅106 V
Ec = =
μ m2 m
0.028
Vs
• The above example shows that an 0.35μm NMOS device at

VOV=200mV does not operate anywhere near the critical field
(E=0.57·106 << Ec)
• How about, e.g., 0.13μm?
200mV V
E= = 1.5 ⋅106
0.13μm m
• Still not too bad…

47
Short Channel Equation

• Bottom line is that most existing and future MOS analog circuits
are impaired, but not completely limited by velocity saturation
– The digital folks will tell you a different story
• Why?
• A simple equation that captures the moderate deviation from the
long channel forward active drain current is (see text)
1 W 2 1
I D ≅ μCox VOV ⋅
2 L ⎛ VOV ⎞
⎜⎜1 + ⎟⎟
⎝ Ec L ⎠
1 W E L ⋅ VOV
≅ μCox VOV ⋅ c
2 L (Ec L + VOV )
"Parallel Combination"
Typical Values for EcL
NMOS PMOS
0.35μm 2V 8V
0.13μm 0.6V 2.4V
• As long as VOV is "much less" than these voltages, the above

simplified equation holds with reasonable accuracy
• We can use these numbers to check our earlier simulation data
for gm/ID. With the correction factor, we have
gm 2 1 2 1 2
≅ ⋅ e.g . ⋅ ≅ ⋅ 0.9
I D VOV ⎛ VOV ⎞ VOV ⎛ 0.2 ⎞ VOV
⎜⎜1 + ⎟⎟ ⎜1 + ⎟
⎝ Ec L ⎠ ⎝ 2 ⎠
(Note that this expression is found by using 1.223 and 1.233 in the text,
and not from the approximate ID expression on the previous slide)
• Reasonable agreement with simulation data on slide 6

48
Mobility Degradation due to Vertical Field
• In short channel MOSFETS, the oxide thickness has been

continuously scaled down with feature sizes
– 6.5nm in 0.35μm, 2.2nm in 0.13μm technology
• As a result, there is a large vertical electric field that tries to pull
the carriers closer to the "dirty" silicon surface
– Imperfections impede movement and thus mobility
• This effect can be included by replacing the mobility term with
an "effective mobility"
μ 1
μeff ≅ θ = 0.1...0.4
(1 + θVOV ) V
• Yet another "fudge factor"

– Possible to lump with EcL parameter
Summary – gm/ID
• The long channel model does not predict gm/ID with reasonable
accuracy in any operating regime
– Accuracy also tends to get worse in newer technology
• Once again, we'll find a way to deal with this in practice
• Simple trick: Change of design variables
– Instead of "thinking", in terms of VOV, we will use gm/ID as a
design variable, and not as an unknown that is determined
from our choice of VOV (or other long channel model
parameters)
• "gm/ID design methodology" - more later…

49
fT Simulation
* ft versus gate overdrive
.param gs=1
vds d 0 dc 1.5V
vgs g 0 dc 'gs'
mn1 d g 0 0 nch214 L=0.35um W=10um
.op
.dc gs 0.4V 1.2V 10mV
.probe ov = par('gs-vth(mn1)')
.probe ft = par('1/2/3.142*gmo(mn1)/(-cgsbo(mn1))')
.options post brief dccap

* Note: "dccap" forces HSpice to recalculate caps in
* each simulation step (instead of using constant .op
* value). See HSpice manual for additional info.

.end
Result
NMOS W/L=10/0.35
30
EE214 technology
25 Long Channel Fit
20
f [GHz]
15
T
10
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]
1 3 μVOV
Long channel model: fT =
2π 2 L2

50
Observations - fT
• Again, a simple long channel model doesn't do a very good job

– Large fT discrepancy in subthreshold operation and in strong
inversion (large VOV)
• The reasons for these discrepancies are exactly the same as
the ones we came across when looking at gm/ID
– Bipolar action in subthreshold operation and moderate
inversion
– Short channel effects at large VOV
• Less gm, hence lower gm/Cgs
• Same conclusion, we won't be able to make good predictions
with a simple long channel relationship
gm/ID· fT
NMOS W/L=10/0.35
160
140 EE214 technology

Long Channel
120
gm/I D*f T [GHz/V]
100
80 Sweet spot (?)

60
40 Short channel
Long channel predicts effects
20 too much gm/ID
0
-0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]
gm 1 3μ
Long Channel: ⋅ fT =
ID 2π L2

51
Intrinsic Gain Simulation (VOV)

* gm/gds versus gate overdrive
.param gs=1.5
mn1 d g 0 0 nch214 L=0.35um W=10um
vg g 0 dc 'gs'
vd d 0 dc 1.5
.op 1.5V
.dc gs 0 1.5 10m
.probe ov1 = par('gs-vth(mn1)')

.probe av1 = par('gmo(mn1)/gdso(mn1)')
.options post brief

.end
Result
NMOS, W/L=10/0.35, V =1.5V
DS
100
80
60
gm/gds
40
20 EE214 Technology
Long Channel Model, λ=0.1
0
-0.2 0 0.2 0.4 0.6 0.8
V [V]
OV
• Impossible to approximate with long channel model equation!

52
Using a Longer Channel

NMOS, W/L=10/0.7, VDS=1.5V
1500
EE214 Technology
Long Channel Model, λ=0.01
1000
gm/gds
500
0
-0.2 0 0.2 0.4 0.6 0.8
VOV [V]
• Curve is also closer to long channel model, but still far off for small VOV…
• Also, as expected, gm/gds is larger for a device with longer channel length
Dependence on VDS
• The long channel model predicts that gds and gm/gds are independent
of VDS
– As long as device is biased in active region
• This is also no longer true in modern devices
– gds (and therefore gm/gds) shows a significant dependence on VDS
Slope = gds1 OP2

ID
Slope = gds2
OP1
VDS

53
Intrinsic Gain Simulation (VDS)

* gm/gds versus vds
.param vt1=571.5m
mn1 d g 0 0 nch214 L=0.35um W=10um
vg g 0 dc 'vt1+0.2'
vd d 0 dc 1.5
.op
.dc vd 0 3 10m
.probe gm1 = par('gmo(mn1)')

.probe gds1 = par('gdso(mn1)')
.options post brief

.end
Result
NMOS, W/L=10/0.35, VOV=200mV

-3
80 x 10
1.5
70
1
gm [S]
60
0.5
50
0
0 1 2 3
gm/gds
40 VDS [V]
4
x 10
30 6
4
1/gds [Ω]
20
10 2
0 0
0 0.5 1 1.5 2 2.5 3 0 1 2 3
VDS [V] VDS [V]

54
Gradual Onset
NMOS, W/L=10/0.35, VOV=200mV -3

x 10
80 1.5
70 1
gm [S]
Triode "Active"
60 0.5
50 0
0 0.2 0.4 0.6 0.8 1
gm/gds
VDS [V]
40
4
x 10
6
30
4
1/gds [Ω]
20
2
10
0
0 0 0.2 0.4 0.6 0.8 1
0 0.2 0.4 0.6 0.8 1 VDS [V]
VDS [V]
Observations – Intrinsic Gain

• gm/gds shows a strong dependence on VDS bias
– Mostly due to varying gds
• There is a gradual transition from triode to active
– Long channel model would have predicted an abrupt change
to large intrinsic gain at VDS = VOV
– Typically need VDS > VOV + 4kT/q to ensure at least
moderate intrinsic gain
• At high VDS, gds increases due to SCBE (substrate current
induced body-effect); this causes a decrease in gm/gds
– Highly technology dependent, and usually not present in
PMOS devices
– If you are interested in more details, please refer to EE316
or a similar course

55
+ gds nonlinearity
• Is vds really a "small signal"?
• The small signal approximation for gds becomes somewhat
inappropriate when the vds swing spans a large fraction of a
nonlinear ID-VDS characteristic
• Luckily, in most practical situations, other (well understood)
sources of nonlinearity dominate (e.g. transconductance)
ID
OP
OP1
VDS
Why care about the Long Channel Model?
• By now, it should be clear that the long channel model does not
accurately predict the performance of a modern MOS device
– There is no simple expression that accurately links gm/ID, fT and
gm/gds to "long channel design parameters" such as VOV
– VOV also doesn't predict the onset of active operation ("Vdsat") all
that well
• In EE214, we will use the long channel model only to understand trends
and proportionalities
– For design and optimization, we'll need a more accurate approach
• Key idea
– The primary variables we care about from a performance
perspective are gm/ID, fT and gm/gds
– So why not work directly with these variables?
• Using Spice-generated design charts and/or look-up tables
• We'll look at this idea using a few design examples

56
Lecture 5
gm/ID-Based Design
Boris Murmann
Stanford University
Overview
• Introduction
– In the past two lectures, we have learned that the long
channel model does not accurately predict the performance
of modern MOS devices. Hence, we switch toward a
strategy in which circuit-oriented performance metrics (such
as gm/ID) are used directly for design and optimization. For a
chosen operating point (gm/ID), other relevant parameters
(such as the device width) are determined using Spice-
generated design charts that serve as a replacement for
(inaccurate) model equations.

57
Overview
• References
– F. Silveira et. al. "A gm/ID based methodology for the design
of CMOS analog circuits and its application to the synthesis
of a silicon-on-insulator micropower OTA," IEEE Journal of
Solid-State Circuits, Sept. 1996, pp. 1314-1319.
– D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS
transistor via the inversion coefficient and the continuum of
gms/Id," Proc. Int. Conf. on Electronics, Circuits and Systems,
pp. 1179-1182, Sept. 2002.
– Denis Flandre's Notes: "Méthodologie gm/ID: un chaînon
entre l'analyse symbolique et la synthèse de circuits
analogiques basse puissance," available at
http://www.comelec.enst.fr/taisa/Presentations/DenisFlandre.pps
– B. E. Boser, "Analog Circuit Design with Submicron
Transistors," IEEE SSCS Meeting, Santa Clara Valley, May
19, 2005, http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
Design Example 1
3V
IB
Vo
RL CL
vi
1.5V
VB
• Given specifications
– DC gain=-2, IB ≤ 2mA, f-3dB=100MHz, CL=10pF
– Minimize transistor area (L=Lmin, W as small as possible)

58
Does ro Matter?
ADC = g m (RL || ro )
−1
⎛ 1 1⎞
= g m ⎜⎜ + ⎟⎟
⎝ RL ro ⎠
1 1 1
= +
ADC g m RL g m ro
1 1 1
= +
2 g m RL g m ro
• Even at L=Lmin= 0.35μm, we have gmro > 50 (see slide 23 of

lecture 4 )
• ro will be negligible in this design problem
Hand Calculations (1)

1 1 1 1
f −3dB = ⇒ RL = = 159Ω
2π RLC L 2π 100 MHz ⋅ 10 pF
2
ADC ≅ − g m RL = −2 ⇒ gm = = 12.6 mS
159Ω
g m 12.6mS 1
• Using all the available current, we have = = 6.3
ID 2mA V
• How about using less current?

W
– Using less current means that we'll g m ~ 2 I D μCox
L
need a device with larger W
– But specifications asked to minimize W fixed ↓↓ ↑↑

59
Hand Calculations (2)
• To complete the design, we need to find the actual device width

• As we know, using long channel equations will be very
inaccurate
• This is where the idea of chart-based design comes in
• Current density chart
– Plot of current density ID/W as a function of gm/ID
– Can generate this chart once and use it throughout the
design process
Current Density Chart

NMOS L=0.35um (VDS=1.5V)
90
80
70
60
ID /W [μA/μm]
50
40
30
20
10
0
0 5 10 15 20 25
gm /ID [S/A]

60
A Better Current Density Chart

NMOS L=0.35um(V(V =1.5V)
=1.5V)
DSDS
23μA/μm
I /W [μA/μm]
1
10
D
0
10
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
gm /ID [S/A]
6.3 1/V
Spice Verification
I 2000
• So, the device width is W= D
ID
= μm = 87 μm
23
W
• How to set VB? 3V

– E.g. using a replica
device (MN2) IB IB
VB Vo
vi
MN2 MN1 RL CL
1.5V

61
DC Operating Point
*** mosfets beta 60.5903m 60.6023m

element 0:mn1 0:mn2
gam eff 894.1238m 894.1238m
model 0:nch214 0:nch214
gm 13.0740m 12.5695m
region Saturati Saturati
id 2.1548m 2.0000m gds 236.3211u 280.4581u
ibs 0. 0. gmb 2.8628m 2.7961m

ibd 0. 0. cdtot 116.2472f 130.8667f
vgs 859.4584m 859.4584m cgtot 154.7093f 154.7008f
vds 1.4754 859.4584m cstot 295.0430f 295.3025f
vbs 0. 0.
cbtot 304.1593f 318.7492f
vth 573.1479m 583.4011m
cgs 107.8492f 108.1404f
vdsat 206.8747m 201.7080m
vod 286.3105m 276.0573m cgd 19.7902f 19.7903f
g m 13.074 mS 1
= = 6.1
I D 2.1548 mA V
AC Response
7
6.03dB = 2.003
6
5
|vo/vi| [dB]
0 0 1 2
10 10 10
f [MHz]

62
Does VDS matter?

NMOS L=0.35um
VDS=0.5V
VDS=1.5V
VDS=2.5V At gm/ID = 6.3 1/V:
VDS=2.5V
1
VDS=0.5V ID/W = 21.8 A/m (VDS=0.5V)
10
I D/W [uA/um]
ID/W = 23.3 A/m (VDS=1.5V)

ID/W = 23.6 A/m (VDS=2.5V)
∴ Insignificant dependence
on VDS; OK to use a single
chart for design (e.g.
VDS=1.5V)
0
10
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
gm/I D [1/V]
Observations and Remarks (1)

• The design is essentially "right on" target!
– No need for any Spice tweaking
• We accomplished this by focusing on a performance related
parameter (gm/ID) in the design process
– Note that strictly speaking, device width is not a design
parameter, since it does not directly relate to any of the
electrical specs (gain, bandwidth, current) that we were
given

63
Observations and Remarks (2)
• The key advantage of gm/ID based design is that it allows you to

transition from hand analysis to Spice without much of the
"usual" modeling uncertainties
– Simply because we are incorporating relevant simulation
data into the design process
– Enables you to optimize your circuit without even running a
Spice simulation
• To see why this is good, let's compare with some popular
alternatives, as seen in many labs and cubicles around the
country…
Design Methodology 1 (Worst)
• Have an existing design that somehow works for a different

process, different specs, …
• Port this design over and tweak all 137 transistor geometries
until I meet the specs…
• 500 Spice runs later, I am approaching the deadline with a
design that somehow works, god knows how/why

64
Design Methodology 2 (Better)
• Remember the square law transistor model from class

• Go through the pain of estimating μCox, and do some hand
calculations
• Plug my design into Spice and realize that everything is about
20…80% off
• Throw away my hand analysis and revert back to the "Spice
Monkey" design flow from here
Design Methodology 3 (Much Better)
• Spend some time to characterize your technology using Spice

– E.g. intrinsic gain and current density as a function of gm/ID
• Do hand calculations using the generated technology data
– Use Matlab, MathCAD or Excel script
– Quickly iterate through tens of different designs, if necessary
• Implement and verify in Spice
– Only minor tweaking necessary (if any)
– Done!

65
Intrinsic Gain, NMOS

EE214 technology, NMOS, 0.35...0.7um
3
10
gm/gds
2
10
5 10 15 20
gm/I D [S/A]
Intrinsic Gain, PMOS

EE214 technology, PMOS, 0.35...0.7um
2
10
gm/gds
1
10
5 10 15 20
gm/I D [S/A]

66
Current Density, NMOS

1
10
I D/W [A/m]
0
10
5 10 15 20
gm/I D [S/A]
Current Density, PMOS

1
10
I D/W [A/m]
0
10
-1
10
5 10 15 20
gm/I D [S/A]

67
+ A Note on Current Density Charts

• Designing with current density charts in a normalized, width-
independent space works because
– Current density and gm/ID are independent of W
• ID/W ~ W/W
• gm/ID ~ W/W
– There is a one-to-one mapping from gm/ID to current density
−2
gm 2 ID 1 1 2 1⎛ I ⎞
Long channel: = = μCox VOV = μCox ⎜⎜ 2 D ⎟⎟
I D VOV W 2 L L ⎝ gm ⎠
gm ID ⎛ ⎛ g ⎞⎞
General case: = f (VOV ) = g (VOV ) = g ⎜⎜ f −1 ⎜⎜ m ⎟⎟ ⎟⎟
ID W ⎝ ⎝ ID ⎠⎠

68
Lecture 6
Extrinsic Capacitance
Boris Murmann
Stanford University
Overview
• Reading
– 1.6.7 (Parasitic Elements)
• Introduction
– In today's lecture, we'll look at another CS amplifier design
example – this time with an input source that has a relatively
large resistance. Through this example, we find that we need
more modeling to accurately predict the resulting pole at the
gate node. Our discussion leads to a discussion of parasitic
extrinsic capacitors around the MOSFET - overlap and
junction capacitance.

69
Design Example 2
VDD
IB
Vo + +
Transducer Ri
vi vgs Cgs gmvgs ro RL vo
RL - -
Ri
vi
1.5V
VB v (s) 1
H( s ) = o = − g m ( ro || RL ) ⋅
vi ( s ) 1 + sRi C gs
DC gain Frequency
• Given specifications Dependence
– DC gain=-4, IB ≤ 0.5mA
– RL=1k, Ri=10k
– Maximize and estimate bandwidth
Hand Calculation
• Just as in the previous design example, we know that
gm/gds >> |ADC|. Hence we simply find
ADC ≅ − g m RL = −4
4
gm = = 4 mS
1kΩ
• In order to maximize bandwidth, we need to make Cgs (and
hence W) as small as possible. Again, this is the case for using
up all the available current
gm 4mS 1
= =8
I D 0.5mA V
• In order to estimate the circuit's bandwidth, we need to know Cgs

– Solution: transit frequency chart

70
Transit Frequency Chart

NMOS L=0.35um
30
25
20
16GHz
f T [GHz]
15
10
0
0 5 10 15 20 25
gm/I D [1/V]
Bandwidth
• Using the transit frequency chart, we find
1 gm 1 4mS
C gs = = = 40 fF
2π fT 2π 16GHz
1 1 1 1
f −3dB = = = 398MHz
2π Ri C gs 2π 10k ⋅ 40 fF
• As a last step, we use the current density chart to find the device
width

71
Current Density Chart

NMOS L=0.35um
15.5μA/μm
1
10
I D/W [uA/um]
0
10
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
gm/I D [1/V]
Spice Verification
I 500
• Device width W= D = = 32μm
ID 15.5
W
• Simulation circuit

72
DC Operating Point
**** mosfets
element 0:mn2 0:mn1 beta 22.1486m 22.1424m
model 0:nch214 0:nch214 gam eff 894.1238m 894.1238m
region Saturati Saturati gm 3.9889m 4.2006m
id 500.0000u 549.5104u
gds 84.1846u 73.4138u
ibs 0. 0.
gmb 894.3095u 927.0356u
ibd 0. 0.
vgs 806.0164m 806.0164m cdtot 49.1459f 43.2542f
vds 806.0164m 1.4505 cgtot 56.5600f 56.5745f
vbs 0. 0. cstot 108.9160f 108.8336f
vth 584.0239m 573.2955m cbtot 118.8806f 113.0007f
vdsat 172.3376m 178.0416m
cgs 39.4669f 39.3691f
vod 221.9925m 232.7209m
cgd 7.2418f 7.2416f
g m 4.2mS S
= = 7.65 C gs = 39.4 fF Good agreement.
I D 549 μA A
Frequency Response
15
11.85dB = 3.91
3dB
10
|vo/vi| [dB]
0 0 1 2 3
10 10 10 10
f [MHz]
• Simulation result: f-3dB=184MHz; hand analysis: f-3dB=398MHz (!)

73
Interpretation
• Even though the estimated value of Cgs matches simulation data

very well, there is a large error in the estimated bandwidth
– Means that our simple bandwidth expression is quite
inaccurate
• The reason for this discrepancy is that we have neglected
"extrinsic" capacitances that affect the frequency response of
our circuit in a significant way
• This example motivates the need for a more accurate
capacitance model
Extrinsic Capacitance
Cjsb Cjdb
• Overlap capacitance
– Gate to source and gate to drain
• Junction capacitance
– Source to bulk and drain to bulk
74
Overlap Capacitance
• Two components
– Direct overlap ~ CoxWLoverlap
– Additional component due to fringing field
• Non-negligible in modern technology (gate thickness is large
compared to other feature sizes)
• EE214 technology parameters (capacitance per width)
– NMOS: Col= 0.23fF/μm
– PMOS: Col= 0.48fF/μm
Junction Capacitance
• Two components
– Area (AS, AD) and Perimeter (PS, PD)
AD ⋅ C j PD ⋅ C jsw
C jdb = mj
+ mjsw
⎛ VDB ⎞ ⎛ VDB ⎞
⎜1 + ⎟ ⎜1 + ⎟
⎝ PB ⎠ ⎝ PB ⎠
EE214
Cj Cjsw mj, mjsw PB
Technology
NMOS 0.85 fF/μm2 0.49 fF/μm 0.39 0.51V
PMOS 1.11 fF/μm2 0.48 fF/μm 0.48 0.93V
• HSpice automatically calculates junction capacitance based on

W and a geometry factor ("hdif")
– May need specify AS, AD, PS, PD in other simulators

75
Layout Dependence (hdif=0.5μm)
AS = AD = 1μm ⋅ W
PS = PD = 2 μm + 2W
(1μm=2*hdif)
AS = 1μm ⋅W
W
AD = 1μm ⋅
2
PS = 4 μm + 2W
PD = 2 μm + W
MOS Capacitor Summary
Subthreshold Triode Active
Cgs Col ½ WLCox+ Col 2/ WLCox + Col

3
Cgd Col ½ WLCox+Col Col

−1
⎛ 1 1 ⎞
Cgb ⎜⎜ + ⎟⎟ "small" "small"
⎝ CCB WLCox ⎠
Csb Cjsb Cjsb+ CCB/2 Cjsb+ 2/3CCB
Cdb Cjdb Cjdb+ CCB/2 Cjdb

76
A Closer Look at Gate Capacitance (Simulation)
NMOS W/L=10/0.35, VDS =0.5V

14
12
Cgs
Capacitance [fF]
10
8
Cgd
6
4
Cgb
2
0
0 0.5 1 1.5 2 2.5 3 3.5
V [V]
GS
Observations
• Cgs, Cgd show gradual transitions

– From subthreshold to active
– From active to triode
• Cgb is non-zero and significant across all operating regions
– Cgb is significant even in active and triode regions since
channel is not a perfect shield; it allows gate field lines to pass
through and terminate at the bulk
• In our 0.35μm technology, Cgd is approximately constant across
active region and ~10-20% of Cgs
– In ≤ 90nm technologies Cgd can be as large as Cgs (!)

77
Improved Definition of fT
• So far, we had
1 gm
fT =
2π C gs
• Taking extrinsic capacitances into account, we redefine
1 gm 1 gm
fT = =
2π C gs + C gb + C gd 2π C gg
• The curve on the following slide was generated with the HSpice
deck shown on slide 15, lecture 4, using the following command
– .probe ft = par('1/2/3.142*gmo(mn1)/cggbo(mn1)')
Improved Transit Frequency Chart

NMOS L=0.35um
30
Improved estimate using C
gg
Previous estimate
25
20
fT [GHz]
15
11.25
10
0
0 5 10 15 20 25
gm /ID [S/A]

78
Transit Frequency, NMOS

14
12
10
f T [GHz]
5 10 15 20
gm/I D [S/A]
Transit Frequency, PMOS

5
f T [GHz]
5 10 15 20
gm/I D [S/A]

79
(gm/ID)*fT, NMOS
90
80
70
gm/I D*f T [GHz*S/A]
60
50
40
30
20
5 10 15 20
gm/I D [S/A]
(gm/ID)*fT, PMOS
40
35
30
gm/I D*f T [GHz*/A]
25
20
15
10
5 10 15 20
gm/I D [S/A]

80
PMOS Well Capacitance

• In the EE214 (N-well) technology, the PMOS transistor is a 5
terminal device
– G, D, S, B, Substrate
• N-well forms a PN junction with the substrate
– Often "AC shorted" when N-well=VDD, Substrate=GND
– Not shorted when we connect N-well to source!
• Resulting capacitance ~ 0.05 fF/μm2
• Not modeled in Spice! Must add extra diode manually in this case
Model for PMOS Well Capacitance
• Model available in ee214_hspice.txt:
* well-to-substrate diode
* example instantiation (area = 10um*10um = 100pm^2)
* (anode) (cathode) (model) (area)
* d1 sub_node well_node dwell 100p
.model dwell d cj0=1e-4 is=1e-5 m=0.5 bv=40

81
Complete Small Signal Model (Active Region)
+ A Note on Transcapacitance
• It turns out that this complicated model still doesn't describe the
parasitics with 100% accuracy
– Since MOSFETS are 4-terminal devices, we are really
dealing with a "4-terminal capacitor" and not with a network
of simple two-terminal capacitors
• In practice, such "transcapacitance" effects are rarely relevant
for design & hand analysis
– Model based on two-terminal capacitors is usually good to
within a few percent
– We'll simply ignore transcapacitance and use Spice as a
final check to see if this was OK…
• In case you are curious about more details, please refer to
section "Introducing Transcapacitance" in the HSpice manual

82
HSpice .OP Output Variables
HSpice (.OP) Corresponding Small Signal

Model Elements
cdtot 43.2542f cdtot ≡ Cgd + Cdb

cgtot 56.5745f cgtot ≡ Cgs + Cgd + Cgb
cstot 108.8336f cstot ≡ Cgs + Csb
cbtot 113.0007f cbtot ≡ Cgb + Csb+ Cdb
cgs 39.3691f
cgs ≡ Cgs
cgd 7.2416f
cgd ≡ Cgd
Cgd and Cdb Calculations (1)
• Cgd and Cdb can be calculated accurately using the data on

slides 13 and 14
– But we need to know the device width (and VDS)
• For design in a "normalized" space, it is often desirable to have
width-independent estimates for these caps
– E.g. Cdg/Cgg and Cdb/Cgg
• The next slide shows simulated values for these ratios at
L=0.35μm and VDS=1.5V

83

NMOS, L=0.35um, VDS=1.5V PMOS, L=0.35um, VDS=1.5V
1 1
C /C
db gg
0.8 C /C 0.8
gd gg
0.6 0.6 Cdb/Cgg

Cgd/Cgg
0.4 0.4
0.2 0.2
0 0
5 10 15 20 5 10 15 20
g /I [S/A] gm/I D [S/A]
m D
NMOS: PMOS:
kgdn=Cgd/Cgg ≅0.13 kgdp=Cgd/Cgg ≅0.26
kdbn=Cdb/Cgg ≅0.65 kdbp=Cdb/Cgg ≅0.80

• For lengths other than 0.35μm, we can use
C gd 0.35 μm Cdb 0.35 μm

≅ k gd ⋅ ≅ k db ⋅
C gg Lx C gg Lx
L = Lx L = Lx
• For a drain bias other than 1.5V, we would in principle need

another adjustment factor for Cdb
– But, since the dependence on VDS is weak (square root), it is
often not worth the effort
• Cdb can be significant, but it is often not the dominant
capacitance

84
"Level 2" Figures of Merit
gm
ID
C gd
C gg
gm
C gg
Cdb
C gg
gm
g ds

85
Lecture 7
Miller Approximation
Zero-Value Time Constant Analysis
Boris Murmann
Stanford University
Overview
• Reading
– 7.1, 7.2.0, 7.2.1 (Miller Effect in CS Stage, only pp. 488-493)
– 7.3.0, 7.3.1 7.3.2 (Zero-Value Time Constant Analysis)
– 7.3.3 (Cascade Amplifier Frequency Response)
– Supplementary document "Bandwidth estimation techniques," by
Tom Lee (optional, see website).
• Introduction
– Last lecture, we found that using a simple circuit model based on
intrinsic capacitance only is not sufficient for accurate bandwidth
prediction in our CS stage. Having learned about the involved
extrinsic capacitances, we are now in a position to improve our
hand analysis and match the Spice result with good precision. To
simplify the analysis, we will utilize the so-called "Miller
Approximation." Next, we will take at look at the the "Zero-Value
Time Constant Analysis" as an alternative method, which is useful
for a much broader class of circuits.

86
Design Example 2 Revisited
H( s ) = ?
≅ RL
Bandwidth Estimation (1)

• To simplify the problem, let's first neglect Cdb
– We'll need to check later if this assumption was OK
• Next, we cut the circuit as shown below and calculate the
equivalent admittance seen looking into the right side of the cut
i( s )
Y( s ) =
vgs ( s )

87
Bandwidth Estimation (2)
i = (vgs − vo )⋅ sC gd + (vo − vgs )⋅ sC gd = 0

vo
g m vgs +
RL
⎛ C ⎞
⎜ 1 − s gd ⎟
i( s ) gm
∴Y ( s ) = = (1 − Av ( s )) ⋅ sC gd with Av ( s ) = − g m RL ⎜⎜ ⎟
⎟
vgs ( s ) 1 + sRL C gd
⎜ ⎟
⎝ ⎠
Miller Approximation
• Assuming that the poles and zeros in Av(s) occur at much higher
frequencies than the bandwidth we are trying to estimate, it is
OK to replace Av(s) with its DC value
– This is known as the "Miller approximation"
– It is always a good idea to check (later) if the approximation
was indeed valid!
• With the Miller approximation, we have
Y ( s ) ≅ (1 + g m RL ) ⋅ sC gd
• This is the same as a capacitor to GND with a value of (1+gmRL)

times Cgd
– "Amplified capacitance"

88
Generalization
vtest vtest Z
Z in = = =
itest vtest − A v
v test 1 − Av
Z
Yin = Y (1 − Av )
• Interesting cases
– Av=0 ⇒ Zin=Z (no surprise…)
– Av=1 ⇒ Zin=∞
• "Bootstrapping"
– Av>1, e.g. Av=2 ⇒ Zin=-Z (negative!)
– Av<0, ⇒ Zin=Z/(1+|Av|)
• Impedance reduction
Modified Input Network
1 1
f −3dB ≅
[
2π Ri C gs + C gb + (1 + g m RL ) ⋅ C gd ]
• Very simple!
– At least much simpler than using exact expressions
• See e.g. equation 7.19 in the text
• Next, we'll verify if the involved assumptions hold in our example
circuit, and also see how accurately we can match Spice

89
Improved Bandwidth Estimate

• Using the transit frequency chart, we find
1 gm 1 4mS
C gg = = = 57 fF
2π fT 2π 11.25GHz
1 1
f −3 dB ≅
[
2π Ri C gs + C gb + (1 + g m RL )C gd ]
1 1 1 1
= =
[
2π Ri C gg + g m RL C gd ] [ (
2π Ri C gg 1 + g m RL k gdn )]
1 1
= = 184 MHz
2π 10 kΩ [57 fF (1 + 4 ⋅ 0.13)]
• Our simulation result from last lecture was

f −3 dB ,Spice = 184 MHz
Assumption Check (1)

• It is interesting (and necessary in general) to check how good
the Miller assumption was in this analysis
• We assumed that ⎛ C
⎜ 1 − s gd
⎞
⎟
gm ⎟ ≅ −g R
Av ( s ) = − g m RL ⎜⎜ ⎟ m L
1 + sRLC gd
⎜ ⎟
⎝ ⎠
up to the frequency of interest (~184MHz)
• Let's check this by calculating the magnitudes of the pole and
zero in Av(s)
1 1 1 1
= = 21.5GHz
2π RL C gd 2π 1kΩ ⋅ 7.4 fF
1 gm 1 4mS
= = 86GHz
2π C gd 2π 7.4 fF

90

• We had also assumed that the impact of Cdb is negligible
– How can we make sure this is OK?
• One possible solution: Re-derive Av(s) with Cdb present
Cgd
Ri
+ i(s) +
vi vgs Cgs+Cgb Y(s) gmvgs RL Cdb vo
- -
+ (vo − vgs )⋅ sC gd + v0 ⋅ sCdb = 0

vo
g m vgs +
RL
vo ( s )
Av ( s ) =
vgs ( s )
⎛ C ⎞
⎜ 1 − s gd ⎟
v (s) gm ⎟
∴ Av ( s ) = o = − g m RL ⎜⎜
vgs ( s ) 1 + sRL ( C gd + Cdb ) ⎟
⎜ ⎟
⎝ ⎠
• Zero is unchanged, but Cdb lowers pole frequency
• Using Cdb ≅ Cgg·0.65, we find Cdb ≅ 37fF, and hence
1 1 1 1
= = 3.6 GHz
2π RL ( C gd + Cdb ) 2π 1kΩ ⋅ ( 7.4 fF + 37 fF )
• Still not too bad, since 3.6GHz >> 180MHz

– But what if we now add some load capacitance at the output
of the amplifier?
• Will appear in parallel with Cdb

91
Effect of Output Loading (1)
⎛ C ⎞
⎜ 1 − s gd ⎟
vo ( s ) ⎜ gm ⎟
Av ( s ) = = − g m RL ⎜
vgs ( s ) 1 + sRL ( C gd + Cdb + CL ) ⎟
⎜ ⎟
⎝ ⎠
• Suppose CL=10pF, then
1 1 1 1
≅ = 16MHz << 180MHz !
2π RL ( C gd + Cdb + C L ) 2π 1kΩ ⋅10 pF
Effect of Output Loading (2)

• Obviously, with the added CL=10pF, the Miller approximation
does not hold any more
• So what is going on in this modified circuit, with large CL?
– Cgd is "amplified" only at low frequencies, before CL
"destroys" the gain from vgs to vo
– The pole caused by Cgd no longer impairs the 3-dB
bandwidth of the circuit
– Intuitively, the bandwidth must now be somehow set by CL
• After all, it destroys the gain from vgs to vo, which implies that
the gain from vi to vo must also roll off
• With very large CL, it is intuitively clear that the approximate
bandwidth of the circuit should be ~1/(2πRLCL)
– But how about other cases and circuits that don't have a
straightforward Miller approximation?

92
Zero-Value Time Constant Analysis

• Fortunately, there is a more general method that allows us to
estimate the bandwidth of arbitrary circuits (within limits)
– Without going though the pain of deriving the complete s-
domain transfer function
• "ZVTC Analysis," or "Open Circuit Time Constant Analysis"
• Here's how it works
– Remove all but one capacitor. Short independent voltage
sources, remove independent current sources
– Calculate resistance seen by capacitor and compute τj=RjoCj
– Repeat for all capacitors in the circuit
– Sum all time constants and calculate bandwidth estimate
1
ω−3dB ≅
∑τ j
Example (1)
• Step 1:
τ 1 = Ri C1

93
Example (2)
• Step 2:
vtest vgs + RL ( g m vgs + itest ) itest Ri + RL ( g mitest Ri + itest )

R2o = = = = Ri + RL + g m RL Ri
itest itest itest
τ 2 = ( Ri + RL + g m RL Ri )C2
• Step 3: R3o = RL
τ 3 = RLC3
Bandwidth Estimate Based on ZVTC
1 1 1 1
∴ f −3dB ≅ =
2π τ 1 + τ 2 + τ 3 2π Ri C1 + ( Ri + RL + g m RL Ri )C2 + RL C3
• Reality check using numbers from design example 2
C1 = C gs + C gb = 49.6 fF τ 1 = 10kΩ ⋅ 49.6 fF = 496 ps

C2 = C gd = 7.4 fF τ 2 = ( 5 ⋅10kΩ + 1kΩ ) ⋅ 7.4 fF = 377 ps
C3 = Cdb = 35.8 fF τ 3 = 1kΩ ⋅ 35.8 fF = 36 ps
1 1
∴ f −3dB ≅ = 175MHz
2π τ 1 + τ 2 + τ 3
• Not bad!
– Spice simulation gave 184MHz
– Miller approximation result was 184MHz

94
Inclusion of CL
• What happens if again, we consider adding a large load
capacitance (CL)?
C1 = C gs + C gb = 49.6 fF τ 1 = 10kΩ ⋅ 49.6 fF = 496 ps
C2 = C gd = 7.4 fF τ 2 = ( 5 ⋅10kΩ + 1kΩ ) ⋅ 7.4 fF = 377 ps
C3 = Cdb + C L ≅ 10 pF τ 3 = 1kΩ ⋅10 pF = 10,000 ps
1 1
∴ f −3dB ≅ = 14.6MHz
2π τ 1 + τ 2 + τ 3
• Now the third time constant dominates and significantly reduces
our bandwidth estimate
• Looks like this is a powerful method
– Miller effect is taken care of, output loading effect is included
• Most importantly though, the method provides us with insight
about the limiting elements in our circuit!
How ZVTCs Work

• Intuition
– Each time constant relates to the bandwidth that we would
get if no other capacitors were present
• "Local bandwidth bottleneck"
– For simplicity, the ZVTC method linearly combines the local
bottlenecks to estimate the overall bandwidth
• Mathematically, the ZVTC method is based on the
approximation
K K
H( s ) = ≅
bn s n + bn −1s n −1 + ... + b1s + 1 b1s + 1
• Can show that
– b1 corresponds to the sum of all time constants in the circuit
– This approximation is OK unless there are "undamped"
complex poles, or several limiting poles with comparable
magnitude
95
A Simple Example
Exact bandwidth: ZVTC Method:
1 0.644 0.5
ω−3dB = ⋅ 2 −1 = ω−3dB =
RC RC RC
• Roughly -22% error

• ZVTC estimates tend to be conservative
– Actual bandwidth will almost always be at least as high as
estimate
ZVTC Accuracy and Other Caveats

• Accuracy tends to be OK when there is a single dominant pole
– Not surprising, since the "approximation" shown on slide 20
makes no error for a single pole system
– Fortunately, many practical circuits indeed have a somewhat
dominant pole
• Some elements, like AC coupling caps, must be eliminated
before applying the ZVTC method
– These caps are meant to be shorts at high frequencies, and
do not degrade the signal bandwidth
– Can use method of "short circuit time constants" to
determine coupling cap sizes
• See supplementary handout "Bandwidth Estimation
Techniques"
• The ZVTC method tells us nothing about zeros in the transfer
function!

96
Lecture 8
Electronic Noise
Boris Murmann
Stanford University
Overview
• Reading
– 11.1 (Noise Introduction)
– 11.2.2 (Thermal Noise)
– 11.3.3 (MOS Transistor Noise)
– Supplementary Handout: "Introduction to Noise" by Daniel Cooley
• Introduction
– Electronic noise is a significant and fundamental issue in the design
of high performance analog circuits. The noise level of a circuit
affects the "fidelity" or accuracy of the signals that are being
processed. As we shall see, minimizing electronic noise is costly;
there exists a steep tradeoff with power dissipation and bandwidth.
Today's lecture will provide an introduction to electronic noise at the
component level (resistors and MOSFETs). We will use these
results in the remainder of the course to analyze the impact of
noise in various circuits.

97
Types of Noise
• "Man made noise", interference noise
– Signal coupling
– Substrate coupling
– Finite power supply rejection
– Solutions
• Fully differential circuits
• Layout techniques
• "Electronic noise" or "device noise" (focus of this lecture)
– Fundamental
• E.g. "thermal noise" caused by random motion of carriers
– Technology related
• "Flicker noise" caused by material defects and "roughness"
Significance of Electronic Noise (1)
Signal-to-Noise Ratio
2
Psignal Vsignal
SNR = ∝
Pnoise Pnoise
"Signal" "Noise"

98

• Example: Noisy image
http://www.soe.ucsc.edu/~htakeda/kernelreg/kernelreg.htm

• The "fidelity" of electronic systems is often determined by their SNR
– Examples
• Audio systems
• Imagers, cameras
• Wireless and wireline transceivers
• Electronic noise directly trades with power dissipation and speed
– In most circuits, low noise dictates large capacitors (and/or small R,
large gm), which means high power dissipation
• Noise has become increasingly important in modern technologies with
reduced supply voltages
– SNR ~ Vsignal2/Pnoise ~ VDD2/Pnoise
• Designing a low power, high performance circuit requires good
understanding of electronic noise!

99
Topics/Questions
• How to model noise of circuit components

• How to calculate/simulate noise performance of a complete
circuit (e.g. SNR)
• Do we need to worry about electronic noise in all circuits?
– The answer must be no; digital folks never talk about this…
– Need to get a feel for situations where noise matters
Ideal Resistor
i(t)
1V/1kΩ
• Constant current, independent of time

• Non-physical
– In a physical resistor, carriers "randomly" collide with lattice
atoms, giving rise to small current variations over time

100
Physical Resistor
i(t)
1V/1kΩ
• "Thermal Noise" or "Johnson Noise"

– J.B. Johnson, "Thermal Agitation of Electricity in Conductors,"
Phys. Rev., pp. 97-109, July 1928.
• Can model random current component e.g. using a noise
current source in(t)
Properties of Thermal Noise

• Present in any conductor
• Independent of DC current flow
• Instantaneous noise value is unpredictable since it is a result of
a large number of random, superimposed collisions with
relaxation time constants of τ ≅ 0.17ps
– Consequences:
• Gaussian amplitude distribution
• Knowing in(t) does not help predict in(t+Δt), unless Δt is on the
order of 0.17ps (cannot sample signals this fast)
• The power generated by thermal noise is spread up to very
high frequencies (1/τ ≅ 6,000Grad/s)
• The only predictable property of thermal noise is its average
power!

101
Average Power
• For a deterministic current signal with period T, the average
power is given by
T/2
1
Pav = ∫ i 2 (t ) ⋅ R ⋅ dt
T −T / 2
• This definition can be extended to capture non-deterministic
random signals
– Assuming a real, stationary and ergodic random process
T/2
1
in2 (t ) ⋅ R ⋅ dt
T →∞ T ∫
Pn = lim
−T / 2
• For notational convenience, we typically drop R in the above

expression and work with "mean square" current (or voltages)
T/2
1
in2 (t ) ⋅ dt
T →∞ T ∫
i = lim
2
n
−T / 2
Thermal Noise Spectrum

• The so-called power spectral density (PSD) shows how much
power a signal caries at a particular frequency
• In the case of thermal noise, the power is spread uniformly up to
very high frequencies (about 10% drop at 2,000GHz)
PSD(f)
n0
f
• The total average noise power Pn in a particular frequency band
can be found by integrating the PSD
f2
Pn = ∫ PSD( f ) ⋅ df
f1

102
Thermal Noise Power

• Nyquist showed that the noise PSD of a resistor is
PSD( f ) = n0 = 4 ⋅ kT
• k is the Boltzmann constant and T is the absolute temperature

– 4kT = 1.66·10-20 Joules at room temperature
• The total average noise power of a resistor in a certain
frequency band is therefore
f2
Pn = ∫ 4 kT ⋅ df = 4 kT ⋅ ( f 2 − f 1 ) = 4 kT ⋅ Δf
f1
Equivalent Noise Generators

• Can model the noise using either an equivalent voltage or
current generator
Pn 1
vn2 = Pn ⋅ R = 4 kT ⋅ R ⋅ Δf in2 = = 4 kT ⋅ ⋅ Δf
R R
For R = 1kΩ : For R = 1kΩ :
vn2 V2 in2 A2
= 16 ⋅ 10 −18 = 16 ⋅ 10 − 24
Δf Hz Δf Hz
vn2 in2
= 4 nV / Hz = 4 pA / Hz
Δf Δf
Δf = 1MHz ⇒ vn2 = 4 μV Δf = 1MHz ⇒ in2 = 4 nA

103
Two Resistors in Series
(
vn2 = vn1 − vn 2 )
2
= vn21 + vn22 − 2 ⋅ vn1 ⋅ vn 2
• Since vn1(t) and vn2(t) are statistically independent, we have
vn2 = vn21 + vn22 = 4 ⋅ kT ⋅ (R1 + R2 ) ⋅ Δf
• Always remember to add independent noise sources using

mean squared quantities
– Never add RMS values!
MOSFET Thermal Noise (1)

• As one would expect, the noise of a MOSFET operating in the
triode region is equal to that of a resistor
• In the forward active region, the thermal noise of a MOSFET can
be modeled using a drain current source with spectral density
id2 = 4 kT ⋅ γ ⋅ g m ⋅ Δf
• For a long channel MOSFET γ=2/3

• For the past ten years, researchers have been debating over the
value of γ in short channels
– Preliminary (wrong) results had suggested that in short
channels γ can be as high as 2…5 due to hot carrier effects

104
MOSFET Thermal Noise (2)
[Scholten]
• Fortunately, these discussions have come to an end with the

conclusion that short channels have γ ≅ 1
– A. J. Scholten et al., "Noise modeling for RF CMOS circuit simulation," IEEE
Trans. Electron Devices, pp. 618-632, Mar. 2003.
– R. P. Jindal, "Compact Noise Models for MOSFETs," IEEE Trans. Electron
Devices, pp. 2051-2061, Sep. 2006.
Spice Simulation (1)
* EE214 MOS device noise simulation
vd dd 0 1.5
vm dd d 0
vg g 0 dc 0.8 ac 1 1.5V
mn1 d g 0 0 nch214 L=0.35u W=10u dd
h1 c 0 ccvs vm 1 c
0V
.op
d
.ac dec 100 10k 1gig CCVS
.noise v(c) vg 1V/A
.options post brief

.end

105
Spice Simulation (2)
HSpice ("outnoise")
4kT*2/3*gm
(gm=1.28mS)
-22
10
avg(id2)/df [A 2/Hz]
-23
10
-24
10 -2 -1 0 1 2 3
10 10 10 10 10 10
f [MHz]
1/f Noise
• Also called "flicker noise" or "pink noise"
• Caused by traps near Si/SiO2 interface that randomly capture and
release carriers
• Occurs in virtually any device, but is most pronounced in MOSFETS
• One (empirical) way to model flicker noise: Kf 2
gm Δf
– Known as "NLEV=2" HSpice model i12/ f =
Cox W ⋅L f
• For other models, see HSpice manual or
– D. Xie et al, "SPICE Models for Flicker Noise in n-MOSFETs from
Subthreshold to Strong Inversion," IEEE Trans. CAD, pp. 1293-
1303, Nov. 2000
• Kf is strongly dependent on technology; numbers for EE214 0.35μm
CMOS technology:
– Kf,NMOS = 0.5·10-25 V2F
– Kf,PMOS = 0.25·10-25 V2F

106
1/f Noise Corner
• By definition, the frequency at which the flicker noise density

equals the thermal noise density
Kf 2 Kf
gm Δf 1 gm
= 4 kTγ ⋅ g m ⋅ Δf ⇒ f co =
Cox W ⋅ L f co 4 kTγ Cox W ⋅ L
Kf 1 1 ⎛ gm ⎞⎛ I D ⎞
= ⎜ ⎟⎟⎜ ⎟
4 kTγ Cox L ⎜⎝ I D ⎠⎝ W ⎠
• Example: NMOS, L=0.35μm, gm/ID=10V-1 → ID/W=10A/m

⇒ fco = 244kHz
• In more recent technologies, 1/f corner frequencies can be on
the order of 10MHz
1/f Noise Contribution (1)

• Just as with white noise, the total 1/f noise contribution is found
by integrating its spectral density
f2 2
Kf
gm Δf
i12/ f ,tot = ∫ C W ⋅L f
f1 ox
2 2
Kf gm ⎛ f2 ⎞ K f gm ⎛ f ⎞
= ⎜
ln⎜ ⎟ =⎟ 2.3 log ⎜⎜ 2 ⎟⎟
Cox W ⋅ L ⎝ f 1 ⎠ Cox W ⋅ L ⎝ f1 ⎠
• Total flicker noise depends on number of frequency decades

– Same flicker noise power in 1…10 Hz as in 1…10 GHz
– RMS noise proportional to sqrt(# of frequency decades)
• So, does flicker noise matter?
– Look at noise integral to see its relative contribution to total
drain current noise
107
1/f Noise Contribution (2)
Spectrum [A2/Hz]
-20
10
-21
10
10
-22 • For circuits with
-23 "high bandwidth",
10
flicker noise is often
2 4 6 8
10 10 10 10 insignificant
f [Hz]
– Beware of
exceptions…
Sqrt(Integral) [nA]
100
50
0 2 4 6 8
10 10 10 10
f [Hz]
Lower Integration Limit

• Does the flicker noise PSD go to infinity for f→0? Fun
discussions in
– E. Milotti, "1/f noise: a pedagogical review," available at
http://arxiv.org/abs/physics/0204033
• Even if the PSD goes to infinity, do we care?
– Let's say we are sensing a signal for a very long time (down
to a very low frequency), e.g.
• 1 year ≅ 32 Msec, 1/year ≅ 0.03 μHz
– Number of frequency decades in 1/year to 100Hz ≅ 10
• Means instead of 7 decades, we'd now have 17 in the previous
example
• sqrt(17/7) = 1.56 → Only 56% more flicker noise!
• More fun reading on flicker noise
– H. Schmid, "Aaargh! I just loooove flicker noise," IEEE Circuits and
Systems Magazine, Vol.7, Issue 1, pp. 32-35, 2007.

108
MOS Model with Noise Generator
Noiseless!
Kf 2
gm Δf
id2 = 4 kT ⋅ γ ⋅ g m ⋅ Δf +
Cox W ⋅L f
Other MOSFET Noise Sources

• Gate noise
– "Shot noise" from gate leakage current
– Noise from to finite resistance of gate material
– Noise due to randomly changing potential/capacitance
between channel and bulk
• Relevant only at very high frequencies
• Bulk noise
• Source barrier noise in very short channels (Navid & Dutton)
– Shot noise from carriers injected across source barrier
• More in EE314…

109
Lecture 9
Electronic Noise (Continued)
Boris Murmann
Stanford University
Overview
• Reading
– 11.4 (Circuit Noise Calculations)
– 11.5 (Equivalent Input Noise Generators)
– 11.9 (Noise Bandwidth)
• Introduction
– Having established the basic noise mechanisms in
MOSFETS, today's lecture looks at noise in circuits. We will
learn how to calculate the signal-to-noise ratio in a basic RC
circuit and a common source amplifier. These examples are
useful prerequisites for analyzing more complicated circuits
(e.g. OTAs, later in this class). Furthermore, we will use
these simple examples to develop a basic feel for the
relevance of noise and associated tradeoffs.

110
Noise in Circuits (1)
• Most interesting circuits have more than one relevant noise

source
• In order to quantify the net effect of all noise sources, we must
refer the noise sources to a single "interesting" node pair of the
circuit
– Usually output or input
Noise in Circuits (2)
• Output referred noise • Input referred noise

– Refer noise to output via – Represent total noise via a
individual noise transfer fictitious input source that
functions captures all circuit-internal
– Physical concept, exactly noise sources
what one would measure in – Useful primarily for "fair"
the lab comparisons
• E.g. independent of circuit
gain

111
Datasheet Example
Circuit Example 1
• Let's calculate
– Output referred noise
– Input referred noise
– Signal-to-noise ratio at output

112
Output Referred Noise

• Short input voltage, add noise source
• Calculate transfer function from noise source to output
• Multiply noise PSD with squared transfer function to get output
PSD
2 2
vn2,out 1 1
= 4 kT ⋅ R ⋅ = (4 nV ) 2
Δf 1 + sRC 1 + j 2πf ⋅ 1ns
Input Referred Noise
• Input referred noise is simply the PSD of resistor (in this example)
v2 1k
R C
Vout
1pF
vn2,in
= 4 kT ⋅ R = (4 nV )2
Δf

113
+ A Note on Equivalent Input Noise Generators
• In general, input referred noise must be modeled by an

equivalent voltage and current source
– See section 11.5 in the text (optional)
• Modeling the noise with a voltage alone is sufficient when the
circuit is indeed driven by an ideal voltage source (always an
approximation)
– Or, when the input impedance of the circuit is large
• This is the case in MOS circuits at low to moderate frequencies
• Different story at RF frequencies
– You'll learn more about this in EE314
Spice Simulation
* EE214 RC circuit noise -16

10
vin in 0 ac 1 outnoise
r1 in out 1k innoise
c1 out 0 1pF
.ac dec 100 100 1gig

Noise [V2/Hz]
.noise v(out) vin

-17
.options post brief 10
.end
-18
10 4 6 8
10 10 10
f [Hz]

114
Signal-to-Noise Ratio
1 2
Vout , peak
Psignal
SNR = = 2
Pnoise f2 2
vn ,out
Δf ∫⋅ df
f1
• Over which bandwidth should we integrate the noise?

• Two interesting cases
– The output is measured or observed by a system with finite
bandwidth (e.g. human ear)
• Use frequency range of that system as integration limits
• Applies on a case by case basis
– "Total integrated noise"
Total Integrated Noise (1)

• Simply the integral over all frequencies (zero to infinity)
• Relevant metric when output is observed without (significant)
band limiting or when the output is sampled (e.g. switched
capacitor circuits)
• The total integrated noise in our circuit is
∞ 2
1 kT
vn2,out ,tot ∫
= 4 kT ⋅ R ⋅
1 + j 2πf ⋅ RC
df =
C
0
• Interesting result
– Total integrated noise at the output depends only on C (even
though R is generating the noise)

115
Total Integrated Noise (2)

-14
10
Spectrum [V2/Hz]
-16
• Increasing R increases 10
-18
the noise power 10
R=1k
-20
spectral density, but 10
-22
R=100k
also decreases the 10
bandwidth 10
2
10
4
10
6
10
8
10
10
f [Hz]
– R drops out in the
end result
Sqrt(Integral) [μV]
60 R=1k
R=100k
40
20
0 2 4 6 8 10
10 10 10 10 10
f [Hz]
SNR (1)
• Back to our example; plugging in numbers

1 2
Vout , peak
Psignal 0.5V 2 0.5V 2
SNR = = 2 = = = 122 ⋅ 10 6
Pnoise kT kT (64 μV )2
C 1 pF
• SNR in dB
(
10 log 122 ⋅ 10 6 = 81dB )
• Is this "good"?
• Typical system requirements
– Audio: SNR ≅ 100dB
– Video: SNR ≅ 60dB
– Gigabit Ethernet Transceiver: SNR ≅ 35dB

116
SNR (2)
• Assuming Vout,peak = 1V
SNR [dB] C [pF]
20 0.00000083
Hard to make such small capacitors…
40 0.000083
60 0.0083 Designer will definitely be concerned
80 0.83 about thermal noise, capacitor sizes
100 83 set by SNR
120 8300
"Hardcore" thermal noise battle…
140 830000
• General rules of thumb

– Up to SNR ~ 40dB, integrated circuits are usually not limited
by thermal noise
– Achieving SNR >100dB is extremely difficult
• Must usually rely on external components or "tricks" (such as
oversampling, see EE315)
MDS and DR
• Minimum detectable signal (MDS)
– A somewhat arbitrary definition
– Quantifies the signal level in a circuit that yields SNR=1; i.e.
noise power = signal power
• Dynamic range (DR)
Psignal ,max
DR =
MDS
• If the noise level in the circuit is independent of the signal level

(not always the case), it follows that the DR is equal to the "peak
SNR", i.e. the SNR with the maximum signal applied

117
Circuit Example 2: Common Source Amplifier
[Ignoring 1/f noise for simplicity]
vo2 ( f )
2
⎛1 ⎞ R
= 4 kT ⎜ + γg m ⎟ ⋅
df ⎝R ⎠ 1 + j 2πf ⋅ RC
∞ 2
⎛1 ⎞ R
vo2,tot ∫
= 4 kT ⎜ + γg m ⎟ ⋅
⎝R ⎠ 1 + j 2πf ⋅ RC
df
0
kT
= (1 + γg m R )
C
=
kT
(1 + γ Av )
C
kT
= ⋅α
C
CS Stage Noise/Power Tradeoff
• Assuming that we're already using the maximum available

signal swing, improving the SNR by 6dB means
– Increase C by 4x
– Decrease R by 4x to maintain bandwidth
– Increase gm by 4x to preserve gain
• Assuming that we can keep gm/ID constant, this means that we
must increase ID by 4x
• Bottom line
– Improving the SNR in a noise limited circuit by 6dB
("1bit") QUADRUPLES power dissipation !

118
Lecture 10
Backgate Effect
Common Gate Stage
Boris Murmann
Stanford University
Overview
• Reading
– 1.6.6 (Body Transconductance)
– 3.3.4, 7.2.4.2 (Common Gate Stage) Somewhat tedious
– 3.4.2.2, 7.3.4 (up to p. 526) (Cascode Stage) to read…
• Introduction
– Having completed our discussion of simple common source
amplifiers, we now continue by exploring alternative ways of
building single transistor stages. First, we will look at the
common gate (CG) stage, followed by a discussion of the
common drain (CD) stage in the next lecture. While CS
stages can usually be configured with source and bulk nodes
tied together, this is often not the case in the CG and CD
configurations. Hence, we'll first need to take a look at the so
called backgate effect (sometimes called "body effect")
which becomes relevant in this context.

119
The "Atoms" of Analog Circuit Design
• As we've seen from the discussion so far, a common source

stage is sufficient for building a simple amplifier
– How about the other two possible configurations?
• We'll find that common gate and drain stages can be
incorporated as valuable add-ons, for building "better" amplifiers
• Interestingly, many analog circuits can be decomposed into a
combination of the above three fundamental building blocks
Bulk Connection
• In the EE214 (N-well) technology, only the PMOS device has an

isolated bulk connection
• Newer technologies (e.g. 0.13μm CMOS) also tend to have
NMOS devices with isolated bulk ("twin-well" process)

120
Bulk Connection Scenarios
DD
DD
Backgate Effect (1)
VSB>0
• With positive VSB, depletion region around source grows

• Increasing amount of negative fixed charge in depletion region
tends to "repel" electrons coming from source
– Need larger VGS to compensate for this effect

121
Backgate Effect (2)
• This effect is usually factored in as an effective increase in Vt

• Detailed analysis shows
Vt = Vt 0 + γ ( 2φ f + VSB − 2φ f )
• A change in Vt also means a change in drain current
– Define small signal backgate transconductance
∂I D ∂I
g mb = =− D
∂VBS ∂VSB
g mb ∂V ∂I D ∂VGS ∂Vt γ
=− t = =
gm ∂VSB ∂Vt ∂I D ∂VSB 2 VSB + 2φ f
-1
gmb Simulation
NMOS W/L=10/0.35um, V -V =0.2V

GS t
24
Spice
22 Fit using 2φf=0.6V, γ=0.36V-1
20
gmb/gm [%]
18
16
14
12
10
0 0.5 1 1.5 2
VBS [V]

122
Modified Small Signal Model
Common Gate Stage
RL
Cgd+Cdb
Vo
-(gm+gmb)vi ro
+
ii RS v i Cgs+Csb
-
Define: CS = C gs + Csb g' m = g m + g mb

123
CG Current Transfer
io g' m
≅
ii g' + sC + 1
m S
RS
g' m RS 1
≅ ⋅
1 + g' m RS 1 + s RS CS
1 + g' m RS
io 1
≅ for g' m RS >> 1
ii 1 + s CS
g' m
CG Input Impedance (1)
vo vo vtest
KCL @ vo : 0 = + − − g' m vtest
RL ro ro
⇒ vo ≅ g' m (RL || ro )vtest
vtest vo
KCL @ vtest : itest = g' m vtest + −
ro ro
itest g' r
⇒ Yin = ≅ m o + sCS
vtest RL + ro
v gs = −vtest

124
CG Input Impedance (2)
Yin ≅
g' m ro ⎛ (R + r ) ⎞
⎜⎜1 + sCS L o ⎟⎟
RL + ro ⎝ g' m ro ⎠
• At low frequencies
1 1 ⎛ RL ⎞
Rin = ≅ ⎜1 + ⎟
Yin g' m ⎜⎝ ro ⎟⎠
1
– RL<<ro: Rin ≅ (well known)
g' m
RL
– RL>>ro: Rin ≅ (not so well known…)
g' m ro
CG Output Impedance
vtest v gs
itest = + + g' m vgs
ro ro
v gs = −itest RS
vtest
Rout = ≅ ro (1 + g' m RS )
itest
(Very high if g'mRS>>1 !)

125
CG Summary
• Current gain is unity up to very high frequencies
– Our "simple" device model predicts up to roughly fT
• Input impedance is very low
– At least when the output is also terminated with some
reasonable impedance
• Can achieve very high output resistance
• In summary, a common gate stage is ideal for turning a decent
current source into a much better one
– Seems like this is something we can use to improve our
common source stage
• Which is indeed nothing but a decent (voltage controlled)
current source
Cascode Stage
• Invented ~1920, in the context of vacuum tube circuits
– http://web.mit.edu/klund/www/cascode.html
i0
Gm = g m1 ⋅ ≅ g m1 Ro ≅ ro 2 (1 + g' m 2 ro1 )
ii
Gm Ro = g m1ro 2 (1 + g' m 2 ro1 ) ≅ g m1ro1 ⋅ g' m 2 ro 2 ~ ( g m ro )

2

126
High Frequency Benefits
vx g ⎛ R ⎞
= g m1Z x ≅ m1 ⎜⎜1 + L ⎟⎟
vi g' m 2 ⎝ ro 2 ⎠
• Very close to 1, for moderate values of RL

– Mitigates Miller effect
– Even if RL is large, there is often a load
capacitance that provides a low impedance
termination to help maintain this feature
• Additional benefit
– Cascode mitigates direct forward coupling
from Vi to Vo at high frequencies
High Frequency Issues
io 1
≅
ii C gs + Csb
1+ s
g' m
• Cascode causes pole around fT

– Usually non-dominant
– Can be a headache for
stability/phase margin in
circuits with feedback
• More later…

127
Design Example 2 (Lecture 6) Revisited
• What we expect to see in Spice

after adding the cascode device
– Bandwidth should increase
(reduction of Miller effect)
– Non-dominant pole around
some fraction of fT of cascode
device
Frequency Response (1)

15
without cascode
with cascode
10
|vo/vi| [dB]
0 0 1 2 3
10 10 10 10
f [MHz]
• Bandwidth increased from 184MHz to 248MHz

128
Frequency Response (2)
10 without cascode
with cascode
0
-10
|vo/vi| [dB]
-20
-30
-40
-50
-60 0 1 2 3 4 5
10 10 10 10 10 10
f [MHz]
Non-Dominant Pole Estimate
**** mosfets
element 0:mn1 0:mnc
1 g' m
model 0:nch214 0:nch214
f p2 ≅
region Saturati Saturati 2π C gsc + Csbc + Cdb1
id 502.6426u 502.6426u
vgs 806.0164m 962.3326m 1 4 mS + 0.6 mS
≅
2π 40.6 fF + (87.4 fF − 40.6 fF ) + (48.8 fF − 7.2 fF )
vds 837.6674m 659.6900m
vbs 0. -837.6674m
vth 583.4970m 753.1734m
gam eff 894.1238m 938.7402m
gm
gds
4.0020m 4.0280m
82.8309u 114.8096u
f p 2 ≅ 5.7 GHz
gmb 896.5590u 604.0200u
cdtot 48.7686f 42.9326f
cgtot 56.5608f 55.8554f
cstot 108.9121f 87.3547f For comparison:
cbtot 118.5039f 89.2450f
cgs 39.4622f 40.6097f 1 4 mS
cgd 7.2418f 7.0879f fT 2 ≅
2π 56 fF
≅ 11.4GHz

129
Supply Headroom Issue
• Even if we adjust VB such

that VDS1 is small, adding
a cascode reduces the
available signal swing
• This can be a big issue
when designing circuits
with VDD≅1V
– Typically need each
VDS>~0.2V
– A severe dynamic
range penalty
Cascode Noise
• It is typically argued that

cascodes do not add a
VDD VDD
significant amount of noise
RL RL • A closer look reveals that
cascodes can contribute
Vo Vo
significant noise at high
VB VB B frequencies
i2n2 – Noise current A no
A
longer compensates B
Vi i2n1 Vi i2n1 at high frequencies
• We'll take a more
quantitative look at this
later in this course

130
Lecture 11
Common Drain Stage
(Source Follower)
Boris Murmann
Stanford University
Overview
• Reading
– 3.3.7 (Common Drain Stage)
– 7.2.2 (Frequency Response of Voltage Buffers)
– 5.3 (Source Follower as an Output Stage, optional)
• Introduction
– Last lecture, we have seen that a common gate stage has a
fairly low input impedance, and high output impedance. The
common drain stage that we'll analyze today exhibits the
exact opposite features: High input impedance and low
output impedance. After an analysis of relevant port
characteristics, we will discuss some potential applications
and also drawbacks of this circuit.

131
Common Drain Stage
CD Voltage Transfer (1)
⎛ 1 ⎞
vo ⎜⎜ sC Ltot + sC gs + ⎟⎟ − vi sC gs − g m (vi − vo ) = 0
⎝ RLtot ⎠
vo g m + sC gs
=
vi g + sC + sC + 1
m gs Ltot
RLtot
sC gs
1+
vo gm gm
= ⋅
vi g + 1
1+
s (C gs + C Ltot )
m
1 RLtot 1
C Ltot = C L + Csb RLtot = RL || || ro gm +
g mb RLtot

132
Low Frequency Gain

gm 1
av 0 = RLtot = RL || || ro
1 g mb
gm +
RLtot
• Interesting cases
– RL→∞, ro→∞, gmb=0 av 0 = 1
• PMOS, source tied to body, ideal current source
gm
– RL→∞, ro→∞, gmb≠0 av 0 =
g m + g mb
• NMOS, ideal current source)
(typically ≅ 0.8)
gm
– ro→∞, gmb=0, RL finite av 0 =
1
• PMOS, source tied to body, load resistor gm +
RL
High Frequency Gain
s 1
1− g gm +
v
av (s ) = o = av 0 ⋅ z z=− m RLtot
vi s C gs p=−
1− C gs + C Ltot
p
• Three scenarios
|z|<|p| |z|>|p| |z|=|p|
(infinite bandwidth !?)

133
CD Input Impedance
• By inspection
Yin = s (C gd + C gb ) + sC gs (1 − av ( s ))
• Gain term av(s) is real and close to

unity up to fairly high frequencies
• Hence, up to moderate
frequencies, we see a capacitor
looking into the input
– A fairly small one, Cgd + Cgb,
plus a fraction of Cgs
PMOS Stage with Body-Source Tie
• Gate-body capacitance is in
parallel with Cgs
• gmb generator inactive
– Low frequency gain very
close to unity
• Very small input capacitance
Yin = sC gd + s (C gs + C gb )(1 − av ( s ))
Yin ≅ sC gd

134
Bootstrapped PMOS Stage
• "Extremely" small input

capacitance
Yin ≅ sC gd (1 − avP ( s )avN ( s ))
CD Output Impedance (1)
• Let's first look at an analytically

simple case
– Input driven by ideal voltage
source
• By inspection
1 1
Z out =
g m + g mb s (C gs + Csb )
• Low output impedance

– Resistive up to very high
frequencies

135

• Now include finite source resistance
vo ix = (vo − v g )(g m + sC gs ) vg Ri
Zx = =
ix ⎛ vg ⎞ 1
⎟⎟(g m + sC gs )
vo + Ri
= vo ⎜⎜1 −
⎝ vo ⎠ sC gs
1 (1 + sR i C gs )
Zx ≅
gm ⎛ sC gs ⎞
⎜⎜ 1 + ⎟
⎝ g m ⎟⎠
Ri < 1/gm Ri > 1/gm
Inductive behavior!

136
Equivalent Circuit for Ri > 1/gm
1
R1 || R 2 =
gm
R 2 = Ri
Ri2 C gs
L=
g m Ri − 1
• This circuit is prone to ringing!

– L forms an LC tank with any capacitance at the output
Inclusion of Parasitic Input Capacitance
• What happens to this result if we don’t neglect Ci=Cgd+Cgb?
1 (1 + sR i {C gs + C i })
Zx =
gm ⎛ sC gs ⎞
⎜⎜ 1 + ⎟ (1 + sR i C i )
⎝ g m ⎟⎠
1 gm 1 1 1 g
< < < < m
Ri {C gs + C i } C gs Ri C i Ri {C gs + C i } Ri C i C gs

137
Application 1: Level Shifter
• Output quiescent point is roughly Vt+Vov lower than input

quiescent point
Application 2: Buffer
• Low frequency voltage gain of the above circuit is ~gmRbig

– Would be ~gm(Rsmall||Rbig) without CD buffer stage

138
Issues
• Several sources of nonlinearity

– Vt is a function of Vo (NMOS, without S to B connection)
– ID and thus Vov changes with Vo
• Gets worse with small RL
• Reduced input and output voltage swing
– Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V
• CD buffer stage consumes 50% of supply headroom!
– In low VDD applications that require large output swing, using
a CD buffer is often not possible
– CD buffers are more frequently used when the required
swing is small
• E.g. pre-amplifiers or LNAs that turn μV into mV at the output
Application 3: Load Device
• Advantages compared to resistor load

– "Ratiometric"
• Gain depends on ratio of similar
parameters
• Reduced process and
temperature variations
– First order cancellation of
nonlinearities
• Disadvantage
– Reduced swing
g m1
av 0 =
g m 2 + g mb 2

139
Summary – Elementary Transistor Stages
• Common source
– VCCS, makes a good voltage amplifier when terminated with
a high impedance
• Common gate
– Typically low input impedance, high output impedance
– Can be used to improve the intrinsic voltage gain of a
common source stage
• "Cascode" stage
• Common drain
– Typically high input impedance, low output impedance
– Great for shifting the DC operating point of signals
– Useful as a voltage buffer when swing and nonlinearity are
not an issue
Practical Biasing Issues (1)
• Typically cannot
afford to have
sufficiently large
decoupling cap for VB
• Also, may want to
work with ground
referenced input
voltage

140
Practical Biasing Issues (2)
• The modified circuit on the left

solves allows ground referenced
inputs
– But now there is a high pass
filter in the signal path
– Need large area to achieve
low corner frequency
– Typically, this approach is
practical only in RF circuits
• Why?
Better Solution: Differential Amplifier
• Bias point of Vop and Vom set

by IB
– Independent of quiescent
value of Vip and Vim
• Differential output (Vop-Vom)
depends only on differential
input (Vip-Vim)
• More next lecture…

141
Lecture 12
Differential Pair
Boris Murmann
Stanford University
Overview
• Reading
– 3.5.0, 3.5.3, 3.5.5 (Differential Pair)
• Introduction
– The differential pair is the most widely used two-transistor
sub-circuit in analog ICs. Using a differential pair as a
replacement for a simple common source stage eliminates
the need for cumbersome gate biasing. In addition, its
differential input and output voltages are more immune to
parasitic signal coupling. Today we will analyze some
properties of differential pairs and introduce the notion of
common- and differential-mode signal components.

142
Differential Pair
• When Vip=Vim, and both

transistors are identical, we
must have Id1=Id2=ITAIL/2
Id1 Id2
• How about Vip=Vim=1V versus
Vip=Vim=2V?
– Makes no difference!
• From a signal perspective, we
Vip ITAIL Vim care only about the difference
of the applied voltages
– Makes sense to introduce
a new variable
• Vid=(Vip-Vim)
Differential and Common Mode (1)
Id1 Id2
• We now still need a second
variable that describes the
potential of nodes Vip and Vim
with respect to GND
– Could choose either Vip or Vim
ITAIL
• More elegant solution
– Cut Vid in half and define a
new independent variable
+ +
– "Common mode" voltage Vic
Vip Vid Vim
- -

143
Differential and Common Mode (2)
Id1 Id2
Vid = Vip − Vim
Vid
Vip = Vic +
2
ITAIL
V
Vim = Vic − id
2
Vip + Vim
+ + ⇒ Vic =
Vid/2 Vid/2 2
Vip Vim
- Vic -
Coupling Noise Immunity

• Using differential pairs/signals not only solves the biasing issue,
but also mitigates coupling noise issues
Single Ended Signaling Differential Signaling

144
Large Signal Transfer Function (1)
• Let's first do a simple analysis using

Id1 Id2
long channel equations
Vip − Vgs1 = Vim − Vgs 2

M1 M2 I d 1 + I d 2 = I TAIL
ITAIL
2I d1 2I d 2
Vgs1 = Vt + Vgs 2 = Vt +
W W
μCox μCox
L L
+ +
Vip Vid/2 Vid/2 Vim 1 W 4 ITAIL
- Vic - ⇒ I od = I d 1 − I d 2 = μCox Vid − Vid 2
2 L W
μCox
L
Large Signal Transfer Function (2)
• We can turn this into a more elegant expression by using

I TAIL 1 W
= μCox VOV
2
2 2 L
where VOV is the quiescent point gate overdrive with Vid=0
2
I I −I V ⎛ V ⎞
⇒ od = d 1 d 2 = id 1 − ⎜⎜ id ⎟⎟
I TAIL I TAIL VOV ⎝ 2VOV ⎠
• This equation predicts

– Iod/ITAIL = 0 when Vid=0, as expected
– Complete current steering (Iod/ITAIL=±1) takes place when
Vid= ±VOV√2

145
Large Signal Plot

• Note that the equation on previous slide is only valid in the
⎝ points)
center of this transfer function (between saturation
– Why?
1
Slope = 1
Iod/ITAIL 0
1
2 1 0 1 2
-√2 Vid/VOV √2
Observations
• Looks like something we have seen before
– A transfer function that is somewhat linear as long as
Vid<<VOV
• For small signal analysis, we can find an equivalent
transconductance by differentiation at the operating point
dI od I TAIL
Gm = =
dVid Vid =0
VOV
• Note that the transconductance of M1 and M2 is given by

I
2 TAIL
2I D 2 = I TAIL
g m1,2 = =
VOV VOV VOV

146
Does the Tail Node Move?
Id1 Id2
• Can show that
2
Vx 1⎛ V ⎞
Vx = Vic − Vt − VOV 1 − ⎜⎜ id ⎟⎟
4 ⎝ VOV ⎠
ITAIL
• From this expression, we see that

from a small signal perspective the tail
+ +
node is pinned at Vic-Vt-VOV
Vid/2 Vid/2
Vip Vim – "AC ground"
- Vic -
Small Signal Equivalent
id1 id2 • Sufficient to work with half

circuit!
gmvid/2 -gmvid/2
Vx – Can directly apply
everything we've
learned about single
transistor stage
iod = id 1 − id 2 = g m vid
• Half circuit caveats
iod/2 iod – Can not analyze
nonlinearity using half
gmvid/2 gmvid circuits
– Assumes that M1 and
M2 are identical

147
Differential Voltage Amplifier Example
Id1 Id2 • Can model short channel effects using

long channels with source degeneration
Vip − Vgs1 − I d 1 Rsx = Vim − Vgs 2 − I d 2 Rsx

Rsx Rsx I d 1 + I d 2 = I TAIL
ITAIL 2I d1 2I d 2
Vgs1 = Vt + Vgs 2 = Vt +
W W
μCox μCox
L L
1 VOV
Rsx =
gm ε c L ⇒ big mess...

148
Nonlinearity Comparison (1)

• Can look at this using Taylor expansions
• Without Rsx (long channel), we can show that
3
I od ⎛V ⎞ 1 ⎛ Vid ⎞
≅ ⎜⎜ id ⎟⎟ − ⎜⎜ ⎟⎟ − ...
I TAIL ⎝ VOV ⎠ 8 ⎝ VOV ⎠
• With Rsx (short channel) this becomes

3
I od ⎛ Vid ⎞ 1⎛ 1 ⎞⎛ Vid ⎞
≅ ⎜⎜ ⎟⎟ − ⎜⎜ ⎟⎟⎜⎜ ⎟⎟ − ...
I TAIL ⎝ (1 + g m Rsx ) ⋅VOV ⎠ 8 ⎝ 1 + g m Rsx ⎠⎝ (1 + g m Rsx ) ⋅ VOV ⎠
• Short channel differential pair is "more linear"

– But also has less gm at a given current
• For fairness, let's compare nonlinearity at same gm/ID
Nonlinearity Comparison (2)

• Recall that
gm 1 2
≅
I D 1 + g m Rsx VOV
• Plugging this into the equations on the previous slide yields

3
I od ⎛ 1 gm ⎞ 1 ⎛ 1 gm ⎞
≅ ⎜⎜ Vid ⎟⎟ − ⎜⎜ Vid ⎟⎟ − ... Long Channel
I TAIL ⎝ 2 I D ⎠ 8 ⎝ 2 ID ⎠
3
I od ⎛ 1 gm ⎞ 1⎛ 1 ⎞⎛ 1 g m ⎞
≅ ⎜⎜ Vid ⎟⎟ − ⎜⎜ ⎟⎟⎜⎜ Vid ⎟⎟ − ... Short Channel
I TAIL ⎝ 2 I D ⎠ 8 ⎝ 1 + g m Rsx ⎠⎝ 2 I D ⎠
• Minor win for short channel in terms of linearity

– In practice, this may be overshadowed by additional effects
that are not captured in the simple degeneration model

149
"Linear Region" of Transfer Function

• In the long channel case, we found that for good linearity we
need Vid<<VOV
• As we have seen from the derivation above, this requirement
can be generalized to capture both long and short channel
cases simultaneously 2
Vid <<
⎛ gm ⎞
⎜⎜ ⎟⎟
⎝ ID ⎠
• A few approximate rules of thumb

For ~1.5% nonlinearity error: For ~0.1% nonlinearity error:
2 2
Vid < 0.5 ⋅ Vid < 0.2 ⋅
⎛ gm ⎞ ⎛ gm ⎞
⎜⎜ ⎟⎟ ⎜⎜ ⎟⎟
⎝ ID ⎠ ⎝ ID ⎠
Voltage Amplifier Transfer Functions
• In a differential amplifier, we primarily

want to have large gain that links only
the two differential variables
vod
Adm =
vid
• Unfortunately, circuit nonidealities will

also cause nonzero "parasitic" gain
terms
voc voc vod

Acm = Adm −cm = Acm− dm =
vic vid vic
See text 3.5.6.9

150
Common Mode Gain
voc
Acm =
vic
• Ideally zero (RTAIL=∞)

gm
• With finite RTAIL: Acm = − ⋅ (R ro [1 + g m ⋅ 2 RTAIL ])
1 + g m ⋅ 2 RTAIL
Common Mode Rejection Ratio

• Figure of merit that quantifies ratio of desired/undesired gain
– Ideally infinite
Adm
CMRR =
Acm
• For our simple resistively loaded differential pair, this becomes

(assuming R<<ro and ignoring body effect)
gm ⋅ R
CMRR ≅ = 1 + g m ⋅ 2 RTAIL
gm
⋅R
1 + g m ⋅ 2 RTAIL
• Other important figures of merit
Adm Adm
Acm− dm Adm −cm

151
Power Supply Rejection Ratio
• In practice, "noise" on the supplies

will also propagate to the output
– In a differential system usually
due to (half-) circuit imbalance
• Define
vod vod
A+ = A− =
vdd vss
Adm Adm
PSRR+ = PSRR− =
A+ A−
Input Referred Interpretation
vdd vss VDD
PSRR+ PSRR−
vi or vid vo or vod
Amplifier
• E.g. 1mV input signal, 100mV supply noise

– Need PSRR >> 100 (40dB)
• PSRR can be a very critical issue in highly integrated, complex
integrated circuits
– Lots of potential supply noise sources
• E.g. cross-talk between analog and digital sections

152
Lecture 13
Current Mirrors
Offset Voltage
Boris Murmann
Stanford University
Overview
• Reading
– 4.1, 4.2 (Current Mirrors)
– 3.5.6.6, 3.5.6.7 (Input Offset Voltage)
• References
– M. Pelgrom et al., "Matching properties of MOS transistors," IEEE
J. Solid-State Circuits, Oct. 1989.
– P.G. Drennan et al., "Understanding MOSFET mismatch for analog
design," IEEE J. Solid-State Circuits, March 2003.
• Introduction
– In this lecture, we will take a closer look at practical
implementations of current mirrors with emphasis on high
swing biasing techniques. In addition, we will discuss
nonidealities such as threshold voltage mismatch and IR
drop.
153
Current Mirror Bias
• Objectives
– Want "accurate" mirror ratio ITAIL/IREF
– Want large RTAIL (and small CTAIL) for good CMRR
– Want small Vmin to maximize common mode input range
Basic Sizing Considerations
• Always use L1=L2

• Typically make W1/W2 or W2/W1 integer
– Use unit devices connected in parallel
– "m-factor" in Spice
• E.g. M1 d g s b W=10u L=0.35u m=5

154
Inaccuracy due to ΔVDS
ID
=1/r o
slope ΔI
VDS
ΔV
V1 − V2 ΔV
ΔI = I1 − I 2 ≅ =
ro ro
• Two options
– Use device with large ro (Large L)
– Make V1 as close as possible to V2
Output Resistance (M2)

NMOS W/L=10, VGS=800mV, L=0.35μm...0.7μm
2500
2000
1500
ro [kΩ]
1000
500
0
0 0.5 1 1.5 2 2.5 3 3.5
VDS [V]

155
Output Resistance Zoom

NMOS W/L=10, VGS=800mV, L=0.35μm...0.7μm
700
600
500
400
ro [kΩ]
300
200
100
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VDS [V]
Higher Rout
Rout ≅ g m ro2
• A cascode can help create a higher output resistance, e.g. to

improve CMRR in a differential pair
• Even though the impedance is now high at the current mirror
output, we still need V1=V2 to minimize systematic errors in the
current ratio I2/I1

156
Solution 1
• Works, but VOUTmin is very large

– Using long channel algebra,
we have
VOUT min ≅ 2(Vt + VOV ) − Vt = Vt + 2VOV
• Note that using long channel

equations tends to be OK for
current mirrors
– Usually operated in strong
inversion
– Channel length often not
minimum
Solution 2
• Use some kind of "magic battery" that sets the cascode gate
potential such that VOUTmin = 2VOV (minimum possible)
• "High swing" bias

157
Magic Battery 1
• Gate overdrive of ¼ device is twice as large as VOV of all other

devices
– Vcas=Vt+2VOV
– VOUTmin = 2VOV
• Sensitive to body effect
Magic Battery 2
• Less sensitive to body effect

• Stacked device mimics transistor with length 4L
– May not match characteristics of devices with length L all
that well

158
Magic Battery 3
1 W 2 1W ⎛ V ⎞
I1 ≅ μCox VOV = μCox ⎜ [Vx + VOV + Vt ] − Vt − x ⎟ ⋅ Vx ⇒ Vx = VOV
2 L 3 L⎝ 2⎠
• Insensitive to body effect

• (1/3) triode device will not exactly produce VOV
– Typically make device ~1/5 of W, to allow for safety margins
and improved Rout
Magic Battery 4
• No extra current branch

• Needs lots of headroom on
input side
• Sensitive to body effect

159
Magic Battery 5
I1 I1 I1 I2
Vcas
W1/L1 W2/L2 W2/L2
W2/L2
Vx
(2/3)*W1/L1 W1/L1 W1/L1
• The previous circuits assumed that Lmirror=Lcascode

– Sometimes want Lmirror≠Lcascode
• The above circuit makes Vcas =Vt2 + VOV2 + VOV1
– VOUTmin becomes VOV2 + VOV1, as desired
Design Considerations
• In all of the above-discussed circuits, care must be taken to keep

the devices in their active region with sufficient safety margin, and
not to "waste" too much ro
– Typically use ~1/6 in 1/4 size device approach (slide 10)
– Typically use ~1/5 in 1/3 triode device approach (slides 12-14)
• Work with integer ratios and unit devices as much as possible
– Using a 1/5 device really means that we work with a unit
device of size 1, and use 5 of them elsewhere
• Sometimes desirable to keep mirror ratio (I2/I1) reasonably small
– Say, no larger than 10…20
– Ensures reasonable bandwidth at bias nodes for fast recovery
from noise coupling

160
Capacitive Coupling
Vx Low cap:
fast recovery
big bounce
Vx t
t
High cap:
slow recovery
small bounce
• Can use decoupling capacitors to reduce the amplitude of noise

coupling into bias nodes
• If noise is "deterministic" and occurs at the right point in time,
you might be better off not decoupling, but making the bias node
"fast" (small mirror ratio) so it can recover quickly
Offset Voltage
• A current mirror relies on accurate matching of device

parameters (e.g. Vt)
• Unfortunately, there will always be some mismatch between two
nominally identical devices
• A common way of modeling mismatch is based on a
decomposition into two components
– A difference in threshold voltage
– A difference in μCoxW/L = β
• The differences are typically modeled as zero-mean Gaussian
random variables with a standard deviation that primarily
depends on the device area (W·L)

161
Pelgrom Coefficients
AVt Aβ
σ ΔV = σ Δβ =
t
WL β WL
• In 0.35μm technology: AVt ≅ 7mV-μm, Aβ ≅ 1%-μm

– AVt tends to scale down with technology, roughly proportional
to gate oxide thickness
– Aβ has remained roughly constant with scaling
• Example: W=10μm, L=0.35μm
7 mV 1%
σ ΔV = = 3.7 mV σ Δβ = = 0.53%
t
3.5 3.5
β
Inaccuracy Due to Mismatch
ΔI = I 1 − I 2 ≅ g m ΔVt + I 1Δβ
ΔI gm
≅ ΔVt + Δβ
I1 I1
• Example: W=10μm, L=0.35μm, gm/ID=10S/A
2
⎛ S ⎞
σ ΔI = ⎜ 10 ⋅ 3.7 mV ⎟ + (0.53% )2 = (3.7% )2 + (0.53% )2 = 3.74%
⎝ A ⎠
I1
• Threshold mismatch usually dominates

162
Well Proximity Effects
• P. G. Drennan et al., "Implications of Proximity Effects for

Analog Design," Proc. CICC, pp.169-176, Sep. 2006.
Inaccuracy Due to IR Drop
ΔI = I 1 − I 2 ≅ g mVwire
ΔI gm
≅ Vwire
I1 I1
• Want small gm/ID ("large VOV") to mitigate errors due to wire IR

drop
– Unfortunately this means large Vmin

163
A Note on Current Mirror Accuracy

• As we have seen, it is very hard to build "highly" accurate
current mirrors
– Systematic errors: ΔVDS, IR Drop, …
– Random errors: ΔVt, …
• This is often not an issue
– E.g. gm ~ sqrt(ID); 20% error in ID causes ~10% error in gm
• For mirrors using short channels, it is sometimes OK to tweak
the mirror ratio to compensate for ΔVDS-induced systematic
errors
– Keep in mind that you should not overdo this; it makes no
sense to tweak a mirror in Spice to unrealistic accuracies
– Tweaking is only going to work in practice if you know that
gds is properly modeled in your technology file
• Not always the case
Current Distribution (1)

• Typically, we'll only have one single reference current generator
on a chip
• Can generate/distribute currents across chip in two different ways
– Distribute gate voltage
• Can cause big problems due to IR drop and process gradients
• Usually limited to local distribution
– Distribute currents
• Have one global bias cell close to reference that sends currents
into local biasing sub-circuits
• Disadvantage: consumes additional current

164
Current Distribution (2)
Iref

165
Lecture 14
Process Variations
Feedback
Boris Murmann
Stanford University
Overview
• Reading
– 8.0, 8.1, 8.2, 8.3 (Feedback)
– 9.2 (Relation Between Gain and Bandwidth)
– Supplementary Handout "Feedback Systems" by Tom Lee
(see web, optional)
• Introduction
– In today's lecture we will first take a look at typical
component variations in CMOS technology. In light of these
numbers, we then consider negative feedback as a tool for
building amplifiers with precisely defined gain. As we shall
see, using a forward amplifier with "high", but arbitrary gain,
combined with a ratiometric, passive feedback network
allows us to build drift and process insensitive precision gain
stages.

166
PVT
• So far, we've assumed that our Spice model accurately predicts
the performance of every single chip we make
• We have also assumed that all our circuits run at room
temperature, and VDD is precisely fixed
• In practice, it is the circuit designer's job to ensure that the
circuit works in presence of large variations
– PROCESS: Variations among production lots
• "Slow, Nominal and Fast" corners
• Sometimes there are even significant variations across wafers
and individual chips
– VOLTAGE: VDD is usually specified only within ±10%
• E.g. VDD= 2.7…3.3V in our technology
– TEMPERATURE: Ambient temperature variations
• 0…70°C (or -40…125°C)
Graphical Interpretation
[Razavi, p. 599]

167
Typical Variations
Temperature Device Matching

Parameter Lot-to-Lot
Coefficient (Area Dependent)
Vt ±100mV -2mV/°C ~1…10mV
μCox ±20% -0.33%/°C ±0.2%
Rpoly2 (50Ω/square) ±20% 0.2%/°C ±0.1%
Rnwell (1k Ω /square) ±40% 1%/°C ±1%
Cpoly-poly2 ±15% -30ppm/°C ±0.1%
Consequences
• Performance metrics that depend on absolute component
values will show large variations
• Sometimes this is OK
– E.g. bandwidth of a circuit
• Can overdesign, and make sure to have minimum required
bandwidth in presence of worst case variations
• Sometimes this is not OK
– E.g. need a precise gain of two in an A/D converter
• gmRL or gmro will never be accurate enough
• Solution: Use negative feedback to desensitize the circuit to
gmRL or gmro variations

168
Negative Feedback
• Harold S. Black, 1927
vout = a(vin − fvout )
vout a
=
vin 1 + af
• Interesting case:
vout 1
af >> 1 ⇒ ≅
vin f
Interpretation
• As long as we have "large" gain in the forward path a, the
overall gain will depend only on f
• Since vout/vin ~1/f, we often make f ≤ 1
– E.g. for a "closed loop" gain of two, we need f=0.5
• f ≤ 1 is easy to implement, and ratiometric!
– A "wire" (f=1) or resistive or capacitive voltage divider
vout vout R1 + R2
≅1 ≅
vin vin R1

169
Example
R1 = R2 ⇒ f = 0.5
• Case 1: a=100
vout 1 1
= = = 1.96078...
vin 1 1
+f + 0.5
a 100
• Case 2: a=1000
vout 1 1
= = = 1.996007...
vin 1 1
+f + 0.5
a 1000
• 10x variation in forward gain, and only about 1.8% change in

closed loop gain!
Gain Sensitivity
a
• Define A=
1 + af
• Can show that

Δa Δa
ΔA
= a = a
A 1 + af 1 + T
• Fractional change in gain is reduced by product of a and f,

which can be made arbitrarily large (conceptually)
– Loop gain T
• We will find that loop gain is a very meaningful parameter that
will also appear in bandwidth and impedance calculations
– More later…

170
Effect of Negative Feedback on Nonlinearity
(1) vout = a1 (vin − fvout ) + a3 (vin − fvout )

3
!
(2) vout = b1vin + b3vin3
• Substitute (2) into (1), then compare coefficients to get

a1 a3
b1 = b3 =
1 + a1 f (1 + a1 f )4
• Linear term as expected, reduced by (1+T)
• Cubic term reduced by (1+T)4!
Negative Feedback and Bandwidth
a0
E .g . a( s ) =
s
1−
p1
• Closed loop transfer function:

a( s ) a0 1
A( s ) = = ⋅
1 + a( s ) f 1 + a0 f 1 − s 1
p1 1 + a0 f
• Bandwidth increases by (1+T)!

– But gain is reduced by (1+T)
• Product of gain and bandwidth remains constant

171
Bode Plot Illustration
Early Obstacles
• Today we are taking the concept of negative feedback for

granted
• At the time of his "invention," Harold Black had a hard time
convincing his colleagues that negative feedback was indeed
something useful
– It was very hard to make a "high gain" forward amplifier
using vacuum tubes
– Why have large gain and then throw it away by applying
negative feedback?
• Long before negative feedback had been deemed useful,
positive feedback was routinely applied to increase the gain of
amplifiers

172
Positive Feedback
• Edwin H. Armstrong, 1915
vout = a(vin + fvout )
vout a
=
vin 1 − af
• Example vout a
af = 0.9 ⇒ = = 10a
vin 1 − 0.9
• Tenfold increase in gain!
Feedback Using Ideal OpAmp
(
vout = g ⋅ v + − v − )
R1 a=g
f =
R1 + R2
vout a g R + R2
= = ≅ 1
vin 1 + af 1 + g R1 R1
R1 + R2

173
Inverting Configuration
(
vout = g ⋅ v + − v − )
f =? a =?
• Circuit does not map directly into generic block diagram

– Cannot directly identify a and f
– a≠g
Superposition
⇒a
⇒ − af

174
Inverting Configuration
R2
a=− ⋅g
R1 + R2
R1
− af = − ⋅g
R1 + R2
Result
R1
⋅g
R2 af R1 + R2 R
a=− ⋅g f = = =− 1
R1 + R2 a − R R2
2
⋅g
R1 + R2
vout a R
= ≅− 2
vin 1 + af R1
• It can be quite tedious to try and morph arbitrary circuits into a

generic "af" block diagram
– Especially when impedances come into play
• Elegant alternative: "Return Ratio Analysis"
– More later…

175
Lecture 15
Fully Differential Amplifiers
Switched-Capacitor Circuits
Boris Murmann
Stanford University
Overview
• Reading
– 6.0, 6.1.1, 6.1.2, 6.1.2 (Basic Feedback Concepts)
– 12.1, 12.2, 12.3, 12.4 (Fully Differential OpAmps)
– 6.1.7 (Internal Amplifiers)
• Introduction
– Having discussed the basic properties of ideal feedback loops, we
will now take steps toward a practical implementation of feedback
amplifiers in CMOS technology. The first amplifier we consider uses
a very crude gain stage, composed of a simple differential pair and
an active current mirror load. For the time being, we will use this
simple topology as a vehicle to gain basic insight into terminology,
analysis and design tradeoffs.
– As we will argue, it is generally difficult to drive resistive loads with
an amplifier, as the load tends to reduce the circuit's gain. As a
result, many "internal amplifiers" in integrated circuits are based on
purely capacitive feedback, using a "switched-capacitor" approach.

176
A Crude "High-Gain" Amplifier
• Output common mode not well defined

– Depends on mismatch in currents between top and bottom
current mirror
Common Mode Feedback (1)
MPa,b
MNT Ictrl
• Feedback loop forces Voc=Voc,desired by adjusting tail current

177
Common Mode Feedback (2)
Itail ID(VDS) of MP1a,b

= ID,MNT+Ictrl
Ictrl
0 VOC,des VDD
VOC
• Adjusting Ictrl changes VDS across PMOS loads (MP1a,b) and

hence alters VOC
• Without feedback, VOC would be "randomly" set by mismatch
between load and tail current, and strongly depend on load gds
Fully Differential vs. Single Ended (1)
• Symmetrical • Lower complexity

– Helps mitigate parasitic – No CMFB
coupling – Fewer feedback components
– Good PSRR
• Can build non-inverting unity
– Easy to analyze gain buffer without using any
• Twice as much output swing feedback components
compared to single ended

178
Fully Differential vs. Single Ended (2)

• Most precision analog integrated circuits are based on fully
differential stages
– Data converters, filters, etc.
• In contrast, printed circuit board circuits tend to be single ended
– Want minimum complexity and component count
• In EE214, we will study mostly fully differential circuits
– More to come in EE315
• In all of the upcoming assignments, we will use a very simple,
idealized common mode feedback circuit to avoid distraction
from the main design task
– Practical CMFB implementation examples will follow later in
this course
Differential Mode Small Signal Half Circuit

179
Load Considerations
• Low load resistance will "destroy" the gain of our amplifier

– RL may may be an explicit load or due to loading from
feedback network
• But, we want large (loop) gain for good precision
Solution 1: Buffer
• Can be very difficult to build

• Can cost lots of headroom (e.g. CD stage)
• Additional area, power

180
Solution 2: Multi-Stage Amplifier
vod
vid RL CL
• Resistive load "destroys" gain of second stage only

– First stage sees capacitive load
• Costs additional area, power and must sacrifice stage 2 gain
Solution 3: Don’t Use Resistors!
• Can emulate resistors with "switched capacitors"
Δq = C (V1 − V2 )
Δq Δq
V1 − V2 iavg = = = f ⋅ C (V1 − V2 )
i= Δt T
R 1
Ravg =
f ⋅C

181
Switched Capacitor Circuits (1)
SC low-pass filter (passive)
SC integrator
SC gain stage
(actual implementations are fully differential)
Switched Capacitor Circuits (2)

• One of the most significant inventions in the history of ICs
• Predominant approach for precision signal processing in CMOS
– CMOS technology provides good switches & capacitors
• SC circuits have many advantages over RC implementations
– Transfer function set by ratio of capacitors
• RC product suffers from large process variations
– Corner frequencies (of filters) can be adjusted by changing
clock frequency
– Can make large time constants without using large resistors
• RC lowpass, 100Hz: R=16MΩ, C=100pF
• SC lowpass, 100Hz: f=10kHz, C1=6.25pF, C2=100pF
• Reference
– R. Gregorian et al., "Switched-Capacitor Circuit Design,"
Proceedings of the IEEE, Vol. 71, No. 8, August 1983.
182
SC Circuit During φ2
• SC circuits can be very complicated,

but always boil down to same design
problem
– Build a (high-performance) amplifier
with capacitive feedback network
• In EE214 we'll just design the circuit
during φ2 without worrying about the
switches
– More details on SC configurations
and switches are discussed in
EE315
– Particular focus in EE214 is placed
on gain stage configuration
• Gain set by capacitor ratio
SC Gain Stage During φ2
• Assuming ideal amplifier:
i = vi ⋅ jωCs
1
vo = −i ⋅
jωC f
vo C
∴ =− s
vi Cf

183
Noise in SC Gain Stage (1)
• Output is usually sampled by another switched capacitor stage

• What is the relevant noise bandwidth?
Noise in SC Gain Stage (2)
• From Parseval's theorem, it follows that the noise

power of the output samples is equal to the power
spectral density of Vo (during φ2) integrated over all
frequencies
– Total integrated noise as discussed in lecture 9 1 2
Vo , peak ,max
• The dynamic range of the circuit is thus given by: DR = 2
∞ 2
– We'll derive expressions for different types of vn ,o
amplifiers in lecture 19
∫ Δf ⋅ df
0

184
OpAmps versus OTAs (1)
Operational Amplifier Operational Transconductance Amplifier
OpAmps versus OTAs (2)
OpAmp OTA
• "General Purpose" • Most on-chip amplifiers are

• Ideally a voltage controlled OTAs
voltage source • Ideally a voltage controlled
• Low output impedance current source
• Can drive resistive and • High output impedance

capacitive loads • Difficult to drive resistive
• Essentially OTA + buffer loads
• Buffer increases complexity • Use capacitive (switched

and power dissipation capacitor) feedback network

185
Lecture 16
Stability
Analysis of Feedback Circuits
Boris Murmann
Stanford University
Overview
• Reading
– 9.3 (Stability)
– 8.8 (Return Ratio Analysis)
– Supplementary Handout "Feedback Systems" by Tom Lee
(see web, optional)
• Introduction
– This lecture covers basics on the analysis of feedback
amplifiers. Using a simple OTA with capacitive feedback as
an example, we will study the so called "Return Ratio"
method as a tool to assess stability and calculate the
bandwidth of feedback amplifiers. Interestingly, most
relevant performance metrics follow directly from the "return
ratio" or loop gain of the circuit, which highlights the
significance of this parameter in feedback system design.

186
Stability
vo a( s ) a( s )
A( s ) = = =
vi 1 + a( s ) f ( s ) 1 + T ( s )
• Most general criterion: BIBO

– Bounded input – bounded output
– Applies to any system
• A continuous time linear system is BIBO stable if all its poles are
in the left half of the s-plane
– Can calculate roots of 1+T(s) to check stability
• Tedious and hard to do in general
Methods for Checking Stability

• Nyquist Criterion
– Based on evaluating T(s) in a polar plot
– Works for arbitrary T(s)
• Even if T(s) itself is unstable
– See books on control theory for details, or e.g.
• N. M. Nguyen and R. G. Meyer, "Start-up and Frequency Stability in
High-Frequency Oscillators," IEEE JSSC, pp. 810-820, May 1992.
• Bode Criterion
– A subset of the general Nyquist criterion that can be applied when
T(s) itself is stable
• Safe to use in most electronic circuits
• Beware of exceptions
– System is unstable when |T(jω)| > 1 at the frequency where
Phase(T(jω)) = -180°
– Can use simple bode plot to check for stability

187
Stability Measures
|T(jω)|
1
GM =
T ( jω ) ω =ω180
ω180
Typically want GM ≥ 3…5
ωc
Phase[T(jω)]
ωc
ω180 PM = 180° − Phase[T ( jω )]ω =ωc
Typically want PM ≥ 60…70°
Closed Loop Peaking
Closed-loop gain,
normalized to 1/f
ω/ωc
[Text, p.632]

188
OTA with Capacitive Feedback
• Important questions
– Is this circuit stable? What is its phase margin?
– What is the low frequency closed loop gain?
– What is the closed loop bandwidth?
Example: Simple Single Stage OTA
• Issues
– Feedback network loads amplifier
– Amplifier loads feedback network
– At high frequencies, there exists a (capacitive) feedforward
path that overrides the amplifier
• Cannot be modeled using the generic "af" feedback block
diagram

189
Solutions
• If all we needed was the closed loop transfer function, we could
simply do a KCL/KVL based analysis
– Can be quite tedious, especially for more complex circuits
– Hard to assess stability and stability margin
• Two port feedback analysis
– "Shunt-series, shunt-shunt, series-shunt, series-series"
feedback configurations
• See text, sections 8.4, 8.5, 8.6
– Attempts to identify amplifier (a) and feedback network (f)
with loading effects included
– Some feedback circuits cannot be modeled using two-ports
• E.g. bias circuits with feedback loops tend to have only one port
Return Ratio Analysis (1)

• Does not attempt to identify forward gain and feedback network
transfer functions separately
• Analysis aims to identify gain around feedback loop
– Loop gain, loop transmission, a·f
• Different terminology for the same thing
• From the loop gain of a circuit, we can determine
– Stability, closed loop gain characteristics, node impedances
• Analysis can be applied to arbitrary feedback circuits,
independent of topology, port structure, etc.
• We will first look at the complete framework of this technique
– Then identify a way to partition the analysis for our needs
and reduce its algebraic overhead

190
Return Ratio Analysis (2)

1. Set all independent sources to zero
2. Identify a a controlled source in the feedback loop that you want
to analyze and break the loop by disconnecting the source
• E.g. VCCS, VCVS, …
3. Inject a test signal st at the breakpoint
• Current or voltage, depending on type of removed source
4. Find the return signal sr generated by the controlled source that
was disconnected from the circuit in step 2.
5. The return ratio of the controlled source is given by RR = –sr/st
• The text uses the symbol R , we will use RR for simplicity
• Provided that we have chosen a controlled source that
breaks the loop under consideration (and no other loop), the
return ratio of the source is equal to the loop gain of the
circuit, i.e. RR = T
Example
v x = β ⋅ vo
Cf
β=
C f + Cs + C x
⎛ 1 ⎞⎟
v0 = −it ⋅ ⎜⎜ R0 C Ltot = C L + (1 − β )C f
⎝ sCtot ⎟⎠
⎛ ⎞
T (s ) = −
ir
= β ⋅ Gm ⋅ ⎜ R0
1 ⎟ = β ⋅ Gm R0
it ⎜ sC L tot ⎟ 1 + sRoC L
⎝ ⎠ tot

191
Loop Gain Expression
1
T (s ) = β ⋅ Gm R0 ⋅
[
1 + sRo C L + (1 − β )C f ]
Capacitive feedback divider, Feedback loading
includes amplifier input
capacitance Cx
Cf
β=
C f + Cs + C x
• In literature, β is often called "feedback factor"

– We will call it "return factor" to avoid confusion with f of the
generic feedback block diagram
Phase Margin (1)
T ( jω ) Ro→∞
T0 Important to note: Ro is irrelevant for

high-frequency analysis
ω
ωp ωc
β ⋅ Gm R0 β ⋅ Gm ωc
T (s ) = ≅ at high frequencies, as long as ≅ βGm Ro >> 1
1 + sRoC L tot sC L tot ωp
βGm βGm
= 1 ⇒ ωc ≅
jωcC L tot C L tot

192
Phase Margin (2)

T ( jω ) Ro→∞
T0
ω
ωp ωc
Phase[T ( jω )]
ωp ⎛ω ⎞
0° ω Phase[T ( jω )] ω =ωc = − tan −1 ⎜ c ⎟ ≅ −90°
⎜ω ⎟
⎝ p⎠
− 45°
− 90° PM ≅ 180° − 90° ≅ 90°
Closed Loop Transfer Function
vo T( s ) d
A(s ) = = A∞ +
vi 1+ T( s ) 1+ T( s )
⎛ 1 af ⎞
⎜⎜ Note similarit y : A = ⎟⎟
⎝ f 1 + af ⎠
• A∞ is the closed loop gain with ideal feedback (Gm→∞)

• d is the direct signal feedthrough with the controlled source
removed (Gm→0)
– Can often be ignored; we'll look at this term later…

193
Finding A∞
• With infinite Gm, vx must be zero, and there is no current through Cx
0 = vi sCs + vo sC f
Cs
A∞ = −
Cf
Closed Loop Bandwidth

β ⋅ Gm R0 β ⋅ Gm ωc
T (s ) = ≅ = (at high frequencies)
1 + sRoC L tot sC L tot s
T( s ) ωc ωc 1
A(s ) ≅ A∞ ≅ A∞ = ⇒ ω−3dB = ωc
1 + T( s ) s + ωc jω−3 dB + ωc 2
• Closed loop bandwidth is equal to unity gain (crossover)

frequency of |T(s)|
• Consistent with what we've learned before; closed loop pole
should be ~T0 times larger than open-loop pole
1
ω−3dB ≅ ω pT0 = ⋅ Gm Ro = ωc
sC Ltot Ro

194
Finding d
• Writing a general expression for d will be quite messy

• Better to distinguish the two cases of interest from the beginning
– Low frequency (Ro<<|1/jωC|)
– High Frequency (Ro>>|1/jωC|)
High Frequency Result
T( s ) d
A( s ) = A∞ +
1+ T( s ) 1+ T( s )
sC f
1−
Cs Gm
Detailed analysis shows: A(s ) = −
C f 1 + sC Ltot
βGm
• Pole as expected
• Zero at Gm/Cf, typically a very high frequency
– Far beyond ω-3dB if CL is large
• In most cases, calculating feedforward zeros is easier using
simple KCL analysis, with large resistors removed

195
Low Frequency Result
T0 d
A0 = A∞ + 0
1 + T0 1 + T0
Cs T0
d0 = 0 ⇒ A0 = −
C f 1 + T0
• No feedforward, capacitors are open circuits

• Define static gain error
A∞ − A0 A0 T 1 ⎛ 1⎞
ε= ε = 1− = 1− 0 = 1− ≅ 1 − ⎜⎜1 − ⎟⎟
A∞ A∞ 1 + T0 1 ⎝ T0 ⎠
1+
T0
1
ε≅
T0
Summary – OTA with Capacitive Feedback
• To find the static gain error

– Write an expression for the low frequency loop gain, neglect
all impedances due to capacitors
– Note that capacitive voltage dividers still work at low
frequency!
• To find the closed loop bandwidth
– Write an expression for the high frequency loop gain, neglect
finite output resistance of all devices
– The 3-dB bandwidth of the closed loop circuit is
(approximately) equal to the unity gain frequency of T(jω)
• To assess stability and phase margin
– Determine phase of (high-frequency) T(jω) at its unity gain
frequency
• Boring for single pole systems, more interesting if two or more
poles are involved…

196
Comparison
• Two-Port Analysis • Return Ratio Analysis
• a, f • T
• 1/f • A∞
1 af T d
A= A = A∞ +
f 1 + af 1+T 1+T
(feedforward effects are not modeled)

197
Lecture 17
Loop Gain Simulation
Boris Murmann
Stanford University
Overview
• Introduction
– Last lecture, we've seen that return ratio analysis is a useful
tool for characterizing feedback amplifiers in terms of
stability, bandwidth and static precision. Since we are always
interested in verifying our hand analysis results using
simulations, it is desirable to have an equivalent method
available in Spice. In this lecture, we will discuss the so-
called Middlebrook method for loop gain simulation. This
particular approach helps overcome the issue that ideal loop
breakpoints, e.g. at controlled sources, are not directly
accessible in Spice.

198
References
• H.W. Bode, Network Analysis and Feedback Amplifier Design, Van

Nostrand, New York, 1945.
• R.D. Middlebrook, "Measurement of Loop Gain in Feedback Systems,"
Int. J. Electronics, Vol. 38, No.4, .pp. 485-512, 1975.
• S. Rosenstark, "Loop Gain Measurement in Feedback Amplifiers," Int.
J. Electronics, Vol. 57, No.3., pp. 415-421, 1984.
• P.J. Hurst, "Exact Simulation of Feedback Circuit Parameters," Trans.
on Circuits and Systems, pp.1382-1389, Nov. 1991.
• P.J. Hurst, S.H. Lewis, "Simulation of Return Ratio in Fully Differential
Feedback Circuits," Proc. CICC 1994, pp.29-32.
• Ken Kundert, "A Test Bench for Differential Circuits," Online:
http://www.designers-guide.com/Analysis/diff.pdf
• M. Tian, V. Visvanathan, J. Hantgan, K. Kundert, "Striving for small-
signal stability," IEEE Circuits and Devices Magazine, pp. 31-41,
January 2001.
Circuit Example 1
• What is the loop gain in this circuit?

199
Return Ratio Analysis
ir
T (s ) = −
it
• As we've seen last lecture, such a hand calculation is pretty

straightforward
• How can we simulate T(jω) in Spice?
– Using "real" transistor models
Spice MOSFET AC Simulation Model
• Nodes of ideal controlled source are not accesible!

– Cannot break loop at gm generator

200
Popular Simulation Approach
vr
T ( jω ) ≅ −
vt
• Inaccurate
• Hard to estimate mock load
• May get different results for
different breakpoints
• Ideally, we'd like to avoid all
of the above issues
• Solution: Middlebrook
method
Problem Generalization
• Middlebrook argued that any single single loop feedback circuit

can be partitioned as shown below
• Hence, there is always some "nonideal" breakpoint between
impedances
– How can we use this breakpoint to find the loop gain?
available breakpoint
Z1 ⋅ Z 2
T ( s ) = gm
Z1 + Z 2

201
Double Injection Trick
vy Z2
− ≡ Tv = g m ⋅ Z 2 +
vx Z1
Solving yields:
1 1 1
True Loop T = g ⋅ Z1Z 2 = +
m 1 + T 1 + Tv 1 + Ti
Gain: Z1 + Z 2
TvTi − 1
iy
T =
Z1 Tv + Ti + 2
≡ Ti = g m ⋅ Z1 +
ix Z2
• No “DC“ break in the loop, all loading effects included!

• Measure Tv and Ti separately, then calculate actual T
Simulation Example
iy vy
Ti = Tv = −
ix vx
• Two options
– Run two copies of the same circuit simultaneously, or
– Run two simulations with different stimuli

202
Spice Code
.param ai=1 av=0 * utils.sp
m1 vo x 0 0 nch214 L=0.35u W=10u .subckt looptest x y ai=0 av=0
i1 0 vo 100u vx middle x dc 0
cf vo y 200f vy middle y ac 'av'
rf vo y 100gig it 0 middle ac 'ai'
cs y 0 400f
.ends looptest
xt x y looptest ai='ai' av='av'
.op
.ac dec 10 1e3 10e9
.options post brief
.include utils.sp
.alter
.param ai=0 av=1
.end
Matlab Postprocessing
% load signals from first run and calculate Ti

m = loadsig('middlebrook1.ac0');
ti = evalsig(m, 'I_xt_vy')./evalsig(m, 'I_xt_vx')
% load signals from second run and calculate Tv

m = loadsig('middlebrook1.ac1');
tv = -evalsig(m, 'y')./evalsig(m, 'x')
f = 1e-6*evalsig(m, 'HERTZ');
% calculate loop gain

t = (tv.*ti-1)./(2+tv+ti)
% calculate magnitude, phase and plot

% ...

203
Simulation Result
40
Magnitude [dB] 20
Tv
0
Ti
-20 T
-40 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10
f [MHz]
0
Phase [degrees]
Tv
-50 Ti
T
-100 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10
f [MHz]
How to do this in Awaves?

• Generally much more tedious, but some shortcuts make it
possible to do this
– Remember that 1/(1+T) = 1/(1+Tv) + 1/(1+Ti)
– Plugging in voltages & currents for Tv and Ti, this becomes
1/(1+T) = vx/(vx-vy) + ix/(ix+iy)
– With unity test voltage and current, this simplifies to
1/(1+T) = vx/1V + ix/1A
– Probe real and imaginary parts of vx and ix in HSpice using
• .probe ac vxreal = par('vr(x)')
• .probe ac vximag = par('vi(x)')
• .probe ac ixreal = par('ir(xt.vx)')
• .probe ac iximag = par('ii(xt.vx)')
• Can now create expressions for phase and magnitude of T and
plot using real and imaginary components of vx and ix
204
Circuit Example 2
Cf
Cs CL
+ +
vid vod
- -
Cs
CL
Cf
Fully Differential Testbench
v yp − v ym i yp − i ym
Tv = − Ti =
v xp − v xm ixp − ixm

205
Differential Looptest Circuit
.subckt difflooptest xp xm yp ym ai=0 av=0

vxp middlep xp dc 0
vyp middlep yp ac 'av'
vxm middlem xm ac 'av'
vym middlem ym dc 0
it middlem middlep ac 'ai'
.ends difflooptest
Simulation Result
40
Magnitude [dB]
20
Tv
0
Ti
-20 T
-40 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10
f [MHz]
0
Phase [degrees]
Tv
-50 Ti
T
-100 -2 -1 0 1 2 3 4
10 10 10 10 10 10 10
f [MHz]

206
Alternative Approach
• Use baluns to convert differential signals into CM/DM

components and use simple single ended loop test circuit
• The above setup is particularly for use with Spectre simulator
– Spectre has built-in Middlebrook analysis, called "stb"
– Simply replace looptest block with "iprobe" element
– Spectre automatically finds and plots T, no post-processing
needed
Ideal Balun
xfmr .subckt balun vdm vcm vp vm
=
e1 vp vcm transformer vdm 0 2
e2 vcm vm transformer vdm 0 2
xfmr
.ends balun
• Useful for separating CM and DM signal components

• Bi-directional, preserves port impedance
• Uses ideal, inductorless transformers that work down to DC
• Not available in all simulators (but often possible to emulate, see
[Kundert])

207
+ New Middlebrook Method
• Recently, Middlebrook came up with an alternative way of looking at

feedback circuits
– A more "design oriented analysis"
• He titled this approach "The General Feedback Theorem – A final
solution for feedback systems"
• If you are curious about this new method, please refer to
– http://rdmiddlebrook.com
– http://ardem.com/free_downloads.asp
– http://groups.yahoo.com/group/Design-Oriented_Analysis_D-OA/
Multi Loop Considerations
• Any practical feedback circuit has multiple feedback loops

– Fully differential circuits have CM/DM loops
– Local device feedback through Cgd, Rsource
– ...
• Solutions
– Decompose fully differential circuit into CM/DM loops
– If a local feedback loop can be modeled as a combination of
a stable controlled source and passive impedances, the
multi-loop circuit reduces to a single loop [Hurst 94]
– If there is a common breakpoint that breaks all feedback
loops simultaneosly, stability can be checked by finding the
return ratio at the single breakpoint [Hurst 94]

208
Last Resort: General Nyquist Criterion
[Bode 45]:
“If a circuit is stable when all its tubes have their

nominal gains, the total number of clockwise and
counterclockwise encirclements of the critical
point must be equal to each other in the series of
Nyquist diagrams for the individual tubes
obtained by beginning with all tubes dead and
restoring the tubes successively in any order to
their nominal gains“
[You may want to take a controls class if you are

interested in this...]
Another Useful Quote
[Bode 45]:
“... thus the circuit may sing when the

tubes begin to lose their gain because of
age, and it may also sing, instead of
behaving as it should, when the gain
increases from zero as power is supplied
to the circuit...“
Always run one or more transient analyses for a

"true" stability check!

209
Lecture 18
Differential Mode Voltage Range
Two-Stage OTA
Boris Murmann
Stanford University
Overview
• Reading
– 6.3 (Basic Two-Stage MOS Amplifiers)
– 12.6.1 (Fully Differential Two-Stage-Amplifier)
– 12.6.5 (Neutralization)
• Introduction
– As we will see in today's lecture, the available output swing
and open-loop gain of our simple single stage OTA are fairly
limited. Hence, we will begin to consider a two-stage OTA
architecture as an alternative. Unfortunately, with the
addition of a second stage, we also introduce a second pole,
which makes it difficult to achieve reasonable phase margin.
The compensation techniques discussed in the following
lecture will provide solutions to this problem.

210
Output Swing of Simple OTA
• Available output swing depends on input and output common

mode levels
• May be limited by headroom for differential pair device (Vminn) or
active load (Vminp)
Maximum Available Swing

• Input and output common
mode adjusted such that all
devices operate at "edge" of
forward active region
– Well defined using long
channel model, very
gradual transition in short
channels
• Unfortunately, the choice of
Vic and Voc are often dictated
by the circuits that interface
with the amplifier
Vodpp ,max = 2(VDD − Vmin p − Vmin n − Vmin t ) – E.g. Vic=Voc=1.5V

211
Example Vic=Voc=VDD/2
• Assuming that we are limited by Vminn, and Vminn~VOV, the

available differential peak-to-peak swing is ~4Vt
• Since the transition to triode is smooth, which criterion should
we use find the "exact" output range of an amplifier?
Gain vs. Output Swing DC Simulation
90
80
-30%
Vod/Vid [V/V]
70
60
Vodpp,max
50
40
-1.5 -1 -0.5 0 0.5 1 1.5
Vod [V]
• In EE214, we arbitrarily define output range as the peak-to-peak

swing that causes no more than 30% drop in Vod/Vid

212
How Much Gain Can We Get?

• Small signal gain (around Vid=Vod=0):
ron ⋅ rop 1 1
avo = g mn ⋅ = avon = avon
ron + rop r g a
1 + on 1 + mp von
rop g mn avop
1
avo = avon
(g m / I D ) p avon
1+
(g m / I D )n avop
avo = avon || avon for (g m / I D ) p = (g m / I D )n
• E.g. avon=avop=50, (gm/ID)n= (gm/ID)p ⇒ avo=25

• Static gain error ~1/To ~1/avo ~1/25=4%
– Not precise enough for many applications
Two-Stage Amplifier
• More output swing, more gain ~(gmro/2)2

• Output range no longer depends on input common mode

213
Common Mode Feedback
• Same as for single stage OTA!

• Common mode of first stage output is set via VGS of common
source device in second stage
Simplified AC Half Circuit with Feedback
g m1 R1 ⋅ g m 2 R2 1 1
T (s ) = β = β ⋅ a1 (s )a2 (s ) = β ⋅ a(s ) p1 = − p2 = −
⎛ s ⎞ ⎛ s ⎞ R1C1 R2C2
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 − ⎟⎟
⎝ p1 ⎠ ⎝ p2 ⎠

214
How About Miller Effect?

• Two ways to deal with Miller amplification of Cgd in first stage
– Use cascodes
• Often needed for high gain, anyways
– Use "neutralization caps"
• See text, section 12.6.5
Neutralization Caps
• With neutralization caps
Cin = C gs + C gd 1 (1 + av ) + Cn (1 − av )
• Letting Cn=Cgd gives
Cin = C gs + 2C gd 1
• Great! How about cancelling Cin completely?! I.e. letting
C gs + C gd 1 (1 + av )
Cn =
av − 1
• VERY IMPRACTICAL, because av is not well controlled

– Your circuit may end up being a great oscillator…

215
Bode Plot of Loop Gain
Mag ( jω ) β ⋅ a (s )
a2 (s )
a1 (s ) • If ωp1 and ωp2 are

ω close to each
ω p1 ω p 2 other, the loop will
Phase( jω ) essentially have
no phase margin!
β ⋅ a(s )
0°
− 90°
−180° ω
Introducing a Dominant Pole
Mag ( jω ) β ⋅ a(s )
• The problem is
a2 (s ) solved if we
somehow
a1 (s )
manage to make
ω p2 ω
ωp1<< ωp2
ω p1 ωc
– Or ωp2<< ωp1
Phase[T ( jω )]
• Loop behaves
0° close first order
system around
− 90°
crossover
−180° ω frequency

216
Phase Margin
• At the crossover frequency, the dominant pole has shifted the
phase by about -90°
• The non-dominant pole's phase at ωc is given by -tan-1(ωc/ωp2)
⎛ω ⎞ ⎛ ω p2 ⎞
PM ≅ 180° − 90° − tan −1 ⎜ c ⎟ PM ≅ tan −1 ⎜⎜ ⎟⎟
⎜ω ⎟ ⎝ ωc ⎠
⎝ p2 ⎠
ωp2/ωc PM
1 45°
2 63°
3 72°
4 76°
5 79°
Creating a Dominant Pole

• Numerical example:
β = 0.5 Gm1 = Gm 2 = 1mS R1 = R2 = 100kΩ C2 = 1 pF PM = 72°
1 f p2 fc
f p2 = = 1.6MHz fc = = 530kHz f p1 = = 106 Hz
2πR2C2 3 β ⋅ Gm1 R1 ⋅ Gm 2 R2
1
C1 = = 15nF
2π ⋅ f p1 ⋅ R1
• Two issues
– Very low fc, which means low closed loop bandwidth
– Huge capacitor
• Get roughly 1fF/μm2 in CMOS technology
• C1 would occupy about 4mm x 4mm !

217
Utilizing the Miller Effect
• Purposely connect an additional capacitor between gate and

drain of M2 (Cc = "Compensation capacitor")
• Two interesting things happen
– Low frequency input capacitance of second stage becomes
large – exactly what we need for low ωp1
– At high frequencies, Cc turns M2 into a diode connected
device – low impedance, i.e. large ωp2 !
Pole Splitting
• More analysis next lecture…

218
Lecture 19
Compensation
Noise in Feedback OTAs
Boris Murmann
Stanford University
Overview
• Reading
– 9.4.1, 9.4.2, 9.4.3 (Compensation)
• Introduction
– In this lecture, we will continue to look at pole splitting as a
method for achieving sufficient phase margin in a two-stage
amplifier. While using a Miller capacitance for compensation
helps move the non-dominant pole to higher frequency, it
also introduces an undesired zero in the transfer function.
Today, we'll discuss several options on how to cope with this
artifact.
– In addition, we will derive useful expressions for the total
integrated noise in OTAs.

219
Two-Stage OTA with Cc
• Detailed analysis shows:

⎛ C ⎞
g m1 R1 ⋅ g m 2 R2 ⋅ ⎜⎜ 1 − s c ⎟⎟
v ⎝ gm2 ⎠
a(s ) = o =
vi 1 + s[(C2 + Cc )R2 + (C1 + Cc )R1 + g m 2 R2 R1Cc ] + s 2 R1 R2 (C1C2 + Cc C2 + Cc C1 )
• Very messy…
Dominant Pole Approximation

• We can write the denominator as
⎛ s ⎞ ⎛ s ⎞ ⎛1 1 ⎞ s2
D (s ) = ⎜ 1 − ⎟ ⋅ ⎜ 1 − ⎟ = 1 − s ⎜ + ⎟ +
⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ p1 ⎠ ⎝ p2 ⎠ ⎝ p1 p2 ⎠ p1 p2
• Since in a practical design outcome we'll have |p1|<<|p2|, we can

approximate
⎛1⎞ s2
D(s ) ≅ 1 − s⎜⎜ ⎟⎟ +
⎝ p1 ⎠ p1 p2
• With this simplification, we can now easily identify p1 and p2 by

comparing the coefficients with the expression from the previous
slide

220
Final Result
⎛ s⎞
⎜1 − ⎟
a(s ) ≅ av 0 ⋅ ⎝ z⎠
⎛ s ⎞ ⎛ s ⎞
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 − ⎟⎟
⎝ p1 ⎠ ⎝ p2 ⎠
1 1
p1 ≅ − ≅−
R1 (C1 + Cc ) + R2 (C2 + Cc ) + g m 2 R2 R1Cc g m 2 R2 R1Cc
gm2 gm2
p2 ≅ − z=+
C1C2 Cc
+ C1 + C2
Cc
• Questions
– How can we design an amplifier with these complex
expressions?
– What will the zero in the transfer function do to us?
RHP vs. LHP Zero
ωz − ωz
Phase Phase
ωz ω
0° 0°
− 45° + 45°
− 90° + 90°
ωz ω

221
OTA Transfer Function with RHP Zero
• RHP zero will reduce

phase margin
– Unless gm2 >> βgm1
g m1 (assuming zero
ωc ≅ β is beyond
Cc
crossover)
ωz gm2
ωz =
Cc
ωz 1 gm2
=
ωc β g m1
Mitigating the Impact of RHP Zero
• Create unilateral feedback through Cc

– Source follower
– Cascode compensation
• Ahuja, IEEE J. Solid-State Ckts., 12/1983
• Ribner, IEEE J. Solid-State Ckts., 12/1984
• "Nulling resistor"
– Push zero to infinity
– Push zero into LHP and cancel nondominant pole (!)

222
Source Follower
• Mitigates feedforward path issue

• Problems: Reduced output swing, additional power dissipation
Cascode Compensation (1)
• Cc sees low impedance, output of first stage sees high

impedance looking into cascode device
– Reduced feedforward

223
Cascode Compensation (2)
• Benefits
– Tends to push ωp2 to higher frequencies, when load
capacitor is large (see text)
• Can use smaller Cc, less power in first stage
• Issues
– Additional power dissipation
– Bias current mismatches cause input referred offset
• The above two issues can be addressed by feeding back to
cascode device embedded in first stage (Ribner, JSSC 12/1984)
– New issue: Complex design problem (3rd order system)
Nulling Resistor (1)
• New transfer function becomes

⎛ 1 ⎞
1 − sCc ⎜⎜ − Rz ⎟⎟
a (s ) ≅ a v 0 ⋅ ⎝ gm2 ⎠
⎛ s ⎞ ⎛ s ⎞ ⎛ s ⎞
⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 − ⎟⎟ ⋅ ⎜⎜1 − ⎟⎟
⎝ p1 ⎠ ⎝ p2 ⎠ ⎝ p3 ⎠
• p1 and p2 unchanged, new pole p3, and a knob to tune the zero

224
• Rz=1/gm2 pushes the zero to +∞

– Can use a transistor in triode region to implement resistor
• Helps track process variations
• Rz=(1+C2/Cc)/gm places zero on top of ωp2!

– Cancels p2
– Good in theory, may be troublesome in practice
– If the pole and zero don't fall exactly on top of each other, we
get a so-called pole-zero doublet
• Can cause very slow settling tails in transient response
– B.Y.T Kamath, R.G. Meyer and P.R. Gray, "Relationship between frequency
response and settling time of operational amplifiers," IEEE JSSC, Vol. 9, No.
6, pp.347–352, Dec. 1974.
• See supplementary handout "Effect of Doublet on Amplifier
Settling Time" (optional)
• Third pole
1 g ω p 3 1 g m 2 Cc
ω p3 ≅ ≅ m2 = typically >> 1
Rz C1 C1 ωc β g m1 C1

225
Other Compensation Methods

• Nested Miller compensation
– >2 gain stages
– Higher order response presents design challenge
– Not (yet?) used much
– Ref: R. G. H. Eschauzier and J. H. Huijsing. Frequency
Compensation Techniques for Low-Power Operational
Amplifiers. Kluwer, 1995.
• Lag/lead compensation
– See handout "Feedback Systems" on website
– An attempt to improve bandwidth/phase margin by adding
additional zeros to T(s)
– May introduce doublets and worsen noise performance
Total Integrated Noise in Feedback OTAs
• General method
– Identify noise sources
– Derive noise transfer functions (NTF)
– Find total noise power from each source by integrating
PSD·NTF from 0 to ∞
– Add up noise powers
• Tedious, but doable…
• Examples
– Single-stage amplifier
– Single-stage amplifier with cascode
– Two-stage amplifier

226
Useful Integrals
Single Stage Amplifier
kT γ ⎛ g ⎞
VB M2 vo2,tot = ⎜⎜ 1 + m 2 ⎟⎟
C Ltot β ⎝ g m1 ⎠
kT ⎛⎜ C gg 1 ⎞⎛
⎟⎜ 1 + g m 2 ⎞⎟
= γ 1 + A∞ +
Cf
+ C Ltot ⎝⎜ C f ⎟⎠⎜⎝ g m1 ⎟⎠
+ M1 CL vo
vi Cs -
- C Ltot = C L + C junction + C f (1 − β )
• Make gm2 as small as possible, i.e. use small gm/ID for current
source device
– Issue: Smaller gm/ID means less available swing
• Small Cgg1, i.e. high fT helps reduce noise

227
Single-Stage Amplifier with Cascode
• Analysis shows
g m1
ωc = β
C Ltot
kT 1 ⎛⎜ g ω ⎞
vo2,tot = 1 + m2 c ⎟
C Ltot β ⎜⎝ g m1 ω p 2 ⎟⎠ ω p2 =
gm2
Cx
kT 1 ⎛ 1 g m2 ⎞
= ⎜⎜ 1 + ⎟
C Ltot β ⎝ k g m1 ⎟⎠ ω p2
k=
ωc
• Make gm2 as small as possible, i.e. use small gm/ID for

cascode device
– Reduces gm2/gm1 and Cx
– Issue: Smaller gm/ID means less available swing
Two-Stage Amplifier
γ kT ⎛ g m11 ⎞ kT ⎡ ⎛ g m 22 ⎞⎤
vo2,tot = ⋅ ⎜1 + ⎟+ ⎢1 + γ ⎜⎜ 1 + ⎟⎥
β Cc ⎜⎝ g m1 ⎟⎠ C Ltot ⎣⎢ ⎝ g m 2 ⎟⎠⎦⎥
Stage 1 Stage 2
• Need large Cc for low noise

• Stage 2 noise can be significant if CL is small and β is large

228
SNR in Differential Circuits
V̂o2
SNR ∝
kT
C
• In fully differential circuits, the effective output swing is doubled

– But there are two half circuits that contribute noise
• Signal power increases by 4x, noise power increases by 2x
– 3dB win in terms of SNR
– At the cost of twice the power consumption (no free lunch…)
Appendix
"Noise in a Two-stage OTA with Nulling Resistor"

Noise in a Two-stage OTA with Nulling Resistor Boris Murmann, 11/26/2006
(Initial derivations by Alireza Dastgheib)
229
230
N1 and N2 are the total integrated noise at the output due to M1 and M2, respectively. N3 is the total noise due to R.
Letting R=1/gm2 simplifies these expressions slightly:
1 kT g m2⋅ ∆
N1 = ⋅γ⋅ ∆ = C c ⋅ C L + C c ⋅ C 1 + C L⋅ C 1
β Cc β ⋅ g m1⋅ Cc C1 + CL + g m2 − β ⋅ g m1 ⋅ ∆
( ) ( )
2 2⎤
kT g m2⋅ ⎡CL⋅ C1 + Cc
⎣ ( ) + C1⋅ Cc
⎦
N2 = ⋅γ⋅
CL 2
β⋅g m1⋅ Cc ⋅ C1 + CL + g m2 − β ⋅ g m1 ⋅ Cc⋅ ∆
( ) ( )
kT g m2⋅ CL + C1 ⋅ Cc( )
N3 = ⋅
CL β ⋅ g m1⋅ Cc⋅ C1 + CL + g m2 − β ⋅ g m1 ⋅ ∆
( ) ( )
Now use these expressions to simplify further:
g m1 g m2⋅ Cc ω p2
ω c1 = β ⋅ ω p2 = k=
Cc ∆ ω p1
ω c1⋅ Cc
substitute , g m1 =
β
2
1 kT g m2⋅ ∆ ω p2⋅ ∆ 1 kT ∆
N1 = ⋅γ⋅ substitute , g m2 = → N1 = ⋅ ⋅ γ ⋅ k⋅
β Cc β ⋅ g m1⋅ Cc⋅ C1 + CL + g m2 − β ⋅ g m1 ⋅ ∆
( ) ( ) Cc β Cc 3 3 2 2
Cc ⋅ C1 + Cc ⋅ CL + k ⋅ ∆ − ∆ ⋅ Cc
substitute , ω p2 = k ⋅ ω c1
simplify
1 kT 1
N1 = ⋅ ⋅γ⋅
β Cc 2 2
Cc ⋅ Cc C1 + CL − ∆ ⋅ Cc
( )
1+
2
k⋅ ∆
substitute , ∆ = Cc⋅ CL + Cc⋅ C1 + CL⋅ C1

2 2 2
Cc ⋅ C c⋅ C 1 + C L − ∆ ⋅ Cc
( ) → −Cc ⋅ CL⋅ C1
simplify
1 kT 1
N1 = ⋅ ⋅γ⋅
β Cc 2
C c ⋅ C L⋅ C 1
1−
2
k ⋅ C c ⋅ C L + C c ⋅ C 1 + C L⋅ C 1
( )
The ratio of capacitors in this expression is always <1, also k usually 3...4. For C1->0, the last term above disappears. Hence, the noise
contribution from M1 is well approximated by
1 kT
N1 = ⋅ ⋅γ
β Cc
N2 looks messy unless we let C1->0...

231
232
ω c1⋅ Cc
substitute , g m1 =
β
ω p2⋅ ∆
2 2⎤ substitute , g m2 =
kT g m2⋅ ⎡CL⋅ C1 + Cc
⎣ ( ) + C1⋅ Cc
⎦ Cc kT
N2 = ⋅γ⋅ → N2 = ⋅γ
CL 2 CL
β⋅g m1⋅ Cc ⋅ C1 + CL + g m2 − β ⋅ g m1 ⋅ Cc⋅ ∆
( ) ( ) substitute , ω p2 = k ⋅ ω c1
substitute , ∆ = Cc⋅ CL + Cc⋅ C1 + CL⋅ C1
substitute , C1 = 0
simplify
kT
N2 = ⋅γ
CL
2
N3 1 g m2⋅ CL + C1 ⋅ Cc
( ) substitute , C1 = 0 N3 1
= ⋅ → =
N2 γ simplify N2 γ
g m2⋅ ⎡CL⋅ C1 + Cc
(
⎣ )2 + C1⋅ Cc2⎤⎦
Total Noise for C1->0:
1 kT kT
Ntot = N1 + N2 + N3 = ⋅ ⋅γ + ⋅ (γ + 1)
β Cc CL
233
Lecture 20
OTA Design Considerations
Boris Murmann
Stanford University
Overview
• Introduction
– Today, we will review a possible design strategy for two-
stage OTAs. Since there exist many degrees of freedom in
this topology, a thorough hand analysis is essential, and can
help minimize, if not completely eliminate, the time needed
for a large number of Spice iterations.

234
Two-stage OTA Design Strategy

• The design equations for a two-stage OTA are fairly complex,
and involve several capacitances that may not be known a priori
• Solution: Iterative hand analysis/design
– Most efficiently done using e.g. Excel, Matlab or MathCAD
• Possible design flow
1. Pick Cgg1, Cgg2 based on heuristics (see following slides)
2. Use initial guesses for junction capacitances
3. Calculate Cc based on noise spec
4. Find gm, fT, gm/ID
5. Iterate, using different choices in step 1
6. Find W for Spice verification
7. Resolve potential discrepancies
– E.g. refine Cjunction estimates if necessary
A Note on Discrepancies
• Discrepancies between design script and Spice are usually on
the order of 10-20%
– Mostly due to
• Bias point dependence (VDS); charts generated for VDS=VDD/2
• Inaccuracy in Cjunction estimate
• First order nature of design equations
• Good news
– It is always possible to track discrepancies down if needed
• Look at gm/ID , CGG, Cjunction in the bias point output
• Big difference to square law design using μCox, VOV, …
– These quantities simply don’t exist in your circuit…

235
Component Identification
C1 = C gg 2 + C junction1 Cf
β=
C2 = C L + (1 − β )C f + C junction 2 C f + Cs + C gg1
• For simplicity, we'll first neglect the junction caps in the following
discussion
– Straightforward to include in your optimization script (see
example)
Loop Crossover Frequency
1 g
ωc ≅ ⋅ β ⋅ g m1 R1 g m 2 R2 = β m1
g m 2 R2 R1Cc Cc
Cf
β=
C f + Cs + C gg1
• Small Cgg1 helps increase ωc

– But there is diminishing return if Cgg1 becomes small
compared to Cs, Cf
• Typically a good starting point: Cgg1 ≈ Cf + Cs
– Sometimes optimum, see final exam 2005

236
Nondominant Pole
gm2
ω p2 ≅ CLtot ≅ C L + (1 − β )C f
C Ltot C gg 2
+ C gg 2 + C Ltot
Cc
⎛ C Ltot C gg 2 ⎞
⎜ ⎟
1 ⎛ C gg 2 C Ltot ⎞⎜ C + C Ltot ⎟
≅ ⎜⎜ + ⎟⎟⎜ 1 + gg 2 ⎟
ωp2 ⎝ gm2 gm2 ⎠⎜ Cc
⎟
⎜ ⎟
⎝ ⎠
• Heuristic: Start optimization with Cgg2 ≅ CLtot

• For a given ωp2 target and fixed CLtot
– Choosing Cgg2 much smaller than CLtot means excess
gm2/Cgg2=ωT2 and therefore small (gm/ID)2
– Choosing Cgg2 much larger than CLtot will cost excess gm2
(power) to meet ωp2 target
Choice of Cc
• In practice, and particularly for high DR designs, Cc is often set

by noise requirements
• For designs that are not constraint by noise, it is Interesting to
assume Cgg2=CLtot (not necessarily optimum) to develop further
qualitative insight
– With this choice, we have 1 2 ⎛ C Ltot ⎞
≅ ⎜1 + ⎟
ω p 2 ωT 2 ⎜⎝ 2Cc ⎟⎠
• Cc large means that we can use lower ωT2 (higher gm/ID) and
save power in the second stage
– But larger Cc also requires larger gm1 and thus more power in
the first stage
– This implies that there will be a design-dependent optimum
for Cc

237
CMFB Loop (1)
• How to pick g?
CMFB Loop (2)

• CMFB loop is a feedback circuit that can be handled in the same way
we analyzed the differential loop
– Draw small signal model, find loop crossover, PM, etc.
• The value of g will set the CMFB bandwidth
– How fast should we make the CMFB loop?
• Bandwidth of CMFB loop should be "comparable" to differential loop
– So that any significant disturbances on Voc can recover quickly
• Typically OK to make CMFB bandwidth ~30% of differential loop
bandwidth
– In a typical switched capacitor circuit with 10 time constants of
differential settling, this means that the common mode has about 3
time constants to settle
• Enough time to remove ~95% of common mode disturbance

238
CMFB Loop (3)
• Systematic error in Voc
I D (MB ) − I D (MTa ) − I D (MTb ) ΔI D

ΔVoc ≅ =
g g
• E.g. ΔID=100μA, g=10mS ⇒ ΔVoc=10mV
• Bounds for g
– Upper bound due to stability
– Lower bound due to CMFB bandwidth requirements
Appendix
2-Stage OTA Design Example ("Simple Approach")

2-Stage OTA Design Example ("Accurate Approach")

239
Reference:C:\Documents and Settings\Murmann\My Documents\lib\Mathcad\defaults.mcd
2-Stage OTA Design Example ("Simple Approach")
Cf
Cs CL
- +
Vsd Vid Vod
+ -
Cs
CL
Cf
M4a,b
M1a,b
M3a,b M2a,b
(Miller compensation, neutralization caps and CMFB not shown)

240
Technology Data
2
VDD := 3V γ :=
3
gm/ID, gm/Cgg lookup tables:
Reference:C:\Documents and Settings\Murmann\My Documents\teaching\ee214_autumn07\otaexample\gm
Design Objectives
fc := 200MHz PM := 75deg DR := 72 (dB) G := 2 ε s := 0.5%
Given Component Values
Cs
Cs := 400fF CL := 200fF Cf :=
G
Design Decision: Channel lengths
Return factor estimate assuming Cgg1 is ~equal to sum of feedback caps
Cf
Cgg1 := Cs + Cf β est := β est = 0.167
Cf + Cs + Cgg1
1 3
avo := avo = 1.2 × 10
ε s⋅ β est
For simplicity, assume that each stage contributes same gain (not necessarily accurate/optimal)
avostage := avo avostage = 34.641
For simplicity, assume that intrinsic gain of both signal path devices is 2x stage gain (not
necessarily accurate/optimal). Intrinsic gain requirements:
gmro := 2avostage gmro = 69.282
Based on gmro design charts, we decide:
L1 := 0.55μm L2 := 0.4μm
For simplicity, choose same lengths for pmos/nmos loads (not necessarily optimal)
L3 := L2 L4 := L1
241
Design Decision: gm/ID
S S
gmID1 := 10 gmID2 := 10
A A
Design Decision: Relative gm/ID of active loads, output swing
Ratio of gm/ID in load devices vs. signal path (often want g1,2 to be <1, to minimize noise and
Cjunction; however, very small g1,2 may impose DR limitations)
gmID3 gmID4
g 31 = g 31 := 1 g 42 = g 42 := 1
gmID1 gmID2
Allocated Vdsmin for M2 and M4 and resulting output swing:
VDSmin := 500mV Vodmax := VDD − 2 ⋅ VDSmin (Differential peak amplitude)
Step 1: Calculate Cc based on DR spec
(
C2 := CL + 1 − β est ⋅ Cf ) C2 = 366.667 fF Total stage 2 load
2
0.5⋅ Vodmax
Ntot := Ntot = 355.234 μV
DR
10
10
⎡ 1 k B ⋅ Tr k B ⋅ Tr ⎤
Ntot = 2 ⋅ ⎢ ⋅ (
⋅ γ ⋅ 1 + g 31 +
CL ⎣
) ( )
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤ ⎥
⎦
⎣ β Cc ⎦
( )
1
⋅ k B⋅ Tr⋅ γ ⋅ 1 + g 31
β est
Cc := 2 ⋅ Cc = 0.659 pF
k B ⋅ Tr
Ntot −
C2 ⎣ ( )
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤
⎦
242
Step 2: Calculate transconductances
1
g m1 := ⋅ 2 ⋅ π ⋅ fc⋅ Cc g m1 = 4.966 mS
β est
k := tan⎛⎜ π ⋅ ⎞ k = 3.732
PM
⎟
⎝ 180deg ⎠
g m2 := k ⋅ 2 ⋅ π ⋅ fc⋅ C2 (approx.) g m2 = 1.72 mS
Step 3: Find ID, W
g m1 g m2
ID1 := ID2 := ID1 = 0.497 mA ID2 = 0.172 mA
gmID1 gmID2
( ) ( )
A A
IDW1 := pidw L1 , gmID1 IDW2 := nidw L2 , gmID2 IDW1 = 1.947 IDW2 = 8.893
m m
ID1 ID2
W1 := W2 := W1 = 255.015 μm W2 = 19.336 μm
IDW1 IDW2
Calculate the width ratios (w31 = W3/W1) for the chosen gm/ID
w31 :=
(
pidw L1 , gmID1 ) w31 = 0.219
(
nidw L3 , gmID1 ⋅ g 31 )
w42 :=
(
nidw L2 , gmID2 ) w42 = 4.567
(
pidw L4 , gmID2 ⋅ g 42 )
W3 := W1 ⋅ w31 W4 := W2 ⋅ w42 W3 = 55.835 μm W4 = 88.313 μm
55 88
= 18.333 = 14.667
3 6
243
OTA circuit for simulation (feedback network, CMFB, Cc, etc. not shown)
85uA 85uA 1020uA 170uA 170uA
M4c M4a,b
15/0.55 15/0.55
15/0.55
M=12 M=2
M4d
M1a,b
255/0.55
18/0.4 18/0.4
M3d M3c
M3a,b
18/0.4 M2a,b
M=6 19/0.4
Simulation results (first run, without any tweaking):
f c=130.75MHz, PM=55.78deg, T0=245

Magnitude [dB]
80
60
40
20
0
-20
-40 -2 0 2 4
10 10 10 10
f [MHz]
Phase [degrees]
0
-50
-100
-150
-2 0 2 4
10 10 10 10
f [MHz]
244
PSD [V2/Hz]
-20
10
5 10
10 10
f [Hz]
Sqrt(Integral) [μVrms]
Integral=417.87uVrms, DR=70.59dB (for Vodmax=2.00V)

500
0 5 10
10 10
f [Hz]
Loop crossover and phase margin are way off! Why? Look at .op output:
gm1 = 5.12mS
gm2 = 1.88mS
Not bad. What's wrong?
Junction caps are fairly large and comparable to other caps. E.g. Cdb1~300fF; this will
significantly impact nondominant pole.
Cgg1=688fF, means that beta is smaller than what we had budgetd above (beta,est)
....
Bottom line: Hard to get "reasonable" matching between hand calculations and Spice using
simplified expressions and ignoring junctions caps. Let's fix this...
245
subckt x1 x1 x1 x1 x1 x1
element 1:m1a 1:m1b 1:m2a 1:m2b 1:m3d 1:m3c
model 0:pch214 0:pch214 0:nch214 0:nch214 0:nch214 0:nch214
region Saturati Saturati Saturati Saturati Saturati Saturati
id -515.7219u -515.7219u 209.9559u 209.9559u 85.0000u 100.5239u
ibs 0. 0. 0. 0. 0. 0.
ibd 0. 0. 0. 0. 0. 0.
vgs -1.0731 -1.0731 795.4179m 795.4179m 726.2152m 726.2152m
vds -1.2776 -1.2776 1.4843 1.4843 726.2152m 1.9455
vbs 926.9464m 926.9464m 0. 0. 0. 0.
vth -924.8901m -924.8901m 594.7855m 594.7855m 602.4640m 590.0494m
vdsat -186.1804m -186.1804m 162.1420m 162.1420m 116.5494m 123.5860m
vod -148.1634m -148.1634m 200.6324m 200.6324m 123.7513m 136.1659m
beta 31.1696m 31.1696m 11.1159m 11.1159m 10.5036m 10.4989m
gam eff 458.3707m 458.3707m 894.1238m 894.1238m 894.1238m 894.1238m
gm 5.1229m 5.1229m 1.8862m 1.8862m 1.1167m 1.2474m
gds 67.8360u 67.8360u 20.4147u 20.4147u 14.0027u 12.6163u
gmb 903.7574u 903.7574u 495.7571u 495.7571u 298.8398u 328.6908u
cdtot 419.4667f 419.4667f 25.7526f 25.7526f 28.4889f 22.8775f
cgtot 681.3669f 681.3669f 37.5110f 37.5110f 34.9915f 35.1430f
cstot 938.5513f 938.5513f 69.9117f 69.9117f 65.4864f 65.6493f
cbtot 767.3791f 767.3791f 69.2340f 69.2340f 69.7566f 64.1621f
cgs 528.6546f 528.6546f 27.3328f 27.3328f 25.2053f 25.3129f
cgd 122.2292f 122.2292f 4.3896f 4.3896f 4.1602f 4.1588f
element 1:m3b 1:m3a 1:m4d 1:m4c 1:m4b 1:m4a
model 0:nch214 0:nch214 0:pch214 0:pch214 0:pch214 0:pch214
id 515.7219u 515.7219u -100.5239u -1.1886m -209.9559u -209.9559u
ibs 0. 0. 0. 0. 0. 0.
ibd 0. 0. 0. 0. 0. 0.
vgs 726.2152m 726.2152m -1.0545 -1.0545 -1.0545 -1.0545
vds 795.4179m 795.4179m -1.0545 -926.9464m -1.5157 -1.5157
vbs 0. 0. 0. 0. 0. 0.
vth 601.7593m 601.7593m -739.0005m -740.0639m -735.1556m -735.1556m
vdsat 116.9465m 116.9465m -311.3437m -310.5103m -314.3549m -314.3549m
vod 124.4559m 124.4559m -315.5066m -314.4432m -319.3516m -319.3516m
beta 63.0200m 63.0200m 1.8139m 21.7668m 3.6278m 3.6278m
gam eff 894.1238m 894.1238m 472.5709m 472.5709m 472.5709m 472.5709m
gm 6.7553m 6.7553m 559.8132u 6.6300m 1.1578m 1.1578m
gds 81.4843u 81.4843u 10.9880u 147.0550u 17.4548u 17.4548u
gmb 1.8061m 1.8061m 127.5074u 1.5107m 263.4207u 263.4207u
cdtot 167.9230f 167.9230f 29.4059f 361.5686f 54.5446f 54.5446f
cgtot 210.0083f 210.0083f 39.8665f 478.3955f 79.7341f 79.7341f
cstot 392.9864f 392.9864f 66.0755f 792.9036f 132.1528f 132.1528f
cbtot 415.5359f 415.5359f 62.0693f 753.5347f 119.8678f 119.8678f
cgs 151.2783f 151.2783f 30.0686f 360.8146f 60.1421f 60.1421f
cgd 24.9604f 24.9604f 7.0195f 84.2342f 14.0390f 14.0390f
246
Reference:C:\Documents and Settings\Murmann\My Documents\lib\Mathcad\defaults.mcd
2-Stage OTA Design Example ("Accurate Approach")
Cf
Cs CL
- +
Vsd Vid Vod
+ -
Cs
CL
Cf
M4a,b
M1a,b
M3a,b M2a,b
(Miller compensation, neutralization caps and CMFB not shown)

247
Technology Data
2
VDD := 3V γ := Lmin := 0.35μm
3
k dbn := 0.65 k dbp := 0.8 (approximate ratios of Cdb/Cgg for minimum length device)
gm/ID, gm/Cgg lookup tables:
Reference:C:\Documents and Settings\Murmann\My Documents\teaching\ee214_autumn07\otaexample\gm
Design Objectives
fc := 200MHz PM := 75deg DR := 72 (dB) G := 2 ε s := 0.5%
Given Component Values
Cs
Cs := 400fF CL := 200fF Cf :=
G
Design Decision: Channel lengths
Return factor estimate assuming Cgg1 is ~equal to sum of feedback caps
Cf
Cgg1 := Cs + Cf β est := β est = 0.167
Cf + Cs + Cgg1
1 3
avo := avo = 1.2 × 10
ε s⋅ β est
For simplicity, assume that each stage contributes same gain (not necessarily accurate/optimal)
avostage := avo avostage = 34.641
For simplicity, assume that intrinsic gain of both signal path devices is 2x stage gain (not
necessarily accurate/optimal). Intrinsic gain requirements:
gmro := 2avostage gmro = 69.282
Based on gmro design charts, we decide:
L1 := 0.55μm L2 := 0.4μm
248
For simplicity, choose same lengths for pmos/nmos loads (not necessarily optimal)
L3 := L2 L4 := L1
Design Decision: Relative gm/ID of active loads, output swing
Ratio of gm/ID in load devices vs. signal path (often want g1,2 to be <1, to minimize noise and
Cjunction; however, very small g1,2 may impose DR limitations)
gmID3 gmID4
g 31 = g 31 := 1 g 42 = g 42 := 1
gmID1 gmID2
Allocated Vdsmin for M2 and M4 and resulting output swing:
VDSmin := 500mV Vodmax := VDD − 2 ⋅ VDSmin (Differential peak amplitude)
Usually have to leave margins for PVT and gain drop at swing. Depending on final design outcome
(optimum gm/ID), it may be worth re-visiting this assumtion.
ITERATION
Adjust following parameters to minimize total current computed in step 4
Cgg1
c1 = (good starting point: c1=1) c1 := 1
Cs + Cf
Cgg2
c2 = (good starting point: c2=1) c2 := 1
CL
Step 1: Estimate/calculate return factor and all capacitances
Cf
β := β = 0.167
(Cf + Cs)⋅ (1 + c1)
(
Cgg1 := c1 ⋅ Cs + Cf ) Cgg1 = 600 fF
Cgg2 := c2 ⋅ CL Cgg2 = 200 fF

249
Lmin
Cdb1 := k dbp ⋅ Cgg1 ⋅ Cdb1 = 305.455 fF
L1
To find Cdb3, we estimate the width ratio w31 = W3/W1, assuming gm/ID1=10S/A (not known at
this point; also won't matter much...)
pidw⎛⎜ L1 , 10
S⎞
⎟
w31 :=
⎝ A⎠
w31 = 0.219 Cdb3 := w31⋅ Cdb1 ⋅
k dbn
Cdb3 = 54.338 fF
nidw⎛⎜ L3 , 10 ⋅ g 31⎞⎟
S k dbp
⎝ A ⎠
Lmin
Cdb2 := k dbn ⋅ Cgg2 ⋅ Cdb2 = 113.75 fF
L2
nidw⎛⎜ L2 , 10
S⎞
⎟
w42 :=
⎝ A⎠
w42 = 4.567 Cdb4 := w42⋅ Cdb2 ⋅
k dbp
Cdb4 = 639.428 fF
pidw⎛⎜ L4 , 10 ⋅ g 42⎞⎟
S k dbn
⎝ A ⎠
C1 := Cdb1 + Cdb3 + Cgg2 C1 = 559.793 fF Total stage 1 load
C2 := CL + Cdb2 + Cdb4 + ( 1 − β ) ⋅ Cf
3
C2 = 1.12 × 10 fF Total stage 2 load
2
0.5⋅ Vodmax
Ntot := Ntot = 355.234 μV
DR
10
10
⎡ 1 k B ⋅ Tr k B ⋅ Tr ⎤
Ntot = 2 ⋅ ⎢ ⋅ (
⋅ γ ⋅ 1 + g 31 + ) (
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤ ⎥
⎣ ⎦ )
⎣ β Cc CL
⎦
( )
1
⋅ k B⋅ Tr⋅ γ ⋅ 1 + g 31
β
Cc := 2 ⋅ Cc = 0.56 pF
k B ⋅ Tr
Ntot −
C2 ⎣ ( )
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤
⎦
(Note: for low DR designs, Cc is not neccesarily set by noise and becomes part of the optimization
process (e.g. add variable c3=cc/CL to the iteration loop)
250
Step 3: Calculate transconductances and transit frequencies
1
g m1 := ⋅ 2 ⋅ π ⋅ fc⋅ Cc g m1 = 4.222 mS
β
k := tan⎛⎜ π ⋅ ⎞ k = 3.732
PM
⎟
⎝ 180deg ⎠
⎛ C2⋅ C1 ⎞
g m2 := k ⋅ 2 ⋅ π ⋅ fc⋅ ⎜ + C1 + C2⎟ g m2 = 13.128 mS
⎝ Cc
⎠
1 g m1
fT1 := ⋅ fT1 = 1.12 GHz
2 ⋅ π Cgg1
1 g m2
fT2 := ⋅ fT2 = 10.447 GHz
2 ⋅ π Cgg2
Step 4: Find gm/ID, ID
( ) ( )
1 1
gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2 gmID1 = 10.404 gmID2 = 6.21
V V
g m1 g m2
ID1 := ID2 := ID1 = 0.406 mA ID2 = 2.114 mA
gmID1 gmID2
IDtotal := ID1 + ID2 IDtotal = 2.52 mA
This design (with c1=1, c2=1 -> IDtotal=2.52mA) will certainly work, but there's lots of room for
power optimization. With the above script, it is quite easy to iteratively step c1 and c2 up/down to
search for a power minimum.
For c1=1, c2=1, it is interesting to note that there is lots of self-loading (The Cdb's present a large
fraction of the caps that set fc and fp2). Hence, going to smaller c1 and/or c2 may help lower
power.
Another try with c1=0.5, c2=1 yields IDtotal=1.819mA. Making the pmos smaller reduces its
contributed capacitance faster than gm/ID drops; beta also improves for small c1. Hence, there is
a net reduction in power.
Similarly, using yet another try with c1=0.5, c2=0.5 yields IDtotal=1.497mA.
Manual iterations are very useful for developing intuition; but it is also possible to automate the
search process using an optimization function:
251
Cf
( )
f c1 , c2 := β←
(Cf + Cs)⋅ (1 + c1)
Cgg1 ← c1 ⋅ ( Cs + Cf)
Cgg2 ← c2 ⋅ CL
Lmin
Cdb1 ← k dbp ⋅ Cgg1 ⋅
L1
pidw⎛⎜ L1 , 10
S⎞
⎟
Cdb3 ←
⎝ A⎠
⋅ Cdb1 ⋅
k dbn
nidw⎛⎜ L3 , 10 ⋅ g 31⎞⎟
S k dbp
⎝ A ⎠
Lmin
Cdb2 ← k dbn ⋅ Cgg2 ⋅
L2
nidw⎛⎜ L2 , 10
S⎞
⎟
Cdb4 ←
⎝ A⎠
⋅ Cdb2 ⋅
k dbp
pidw⎛⎜ L4 , 10 ⋅ g 42⎞⎟
S k dbn
⎝ A ⎠
C1 ← Cdb1 + Cdb3 + Cgg2
C2 ← CL + Cdb2 + Cdb4 + ( 1 − β ) ⋅ Cf
( )
1
⋅ k B⋅ Tr⋅ γ ⋅ 1 + g 31
β
Cc ← 2 ⋅
k B ⋅ Tr
Ntot −
C2 ⎣ (
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤ ) ⎦
1
g m1 ← ⋅ 2 ⋅ π ⋅ fc⋅ Cc
β
k ← tan⎛⎜ π ⋅ ⎞
PM
⎟
⎝ 180 ⋅ deg ⎠
⎛ C2 ⋅ C1 ⎞
g m2 ← k ⋅ 2 ⋅ π ⋅ fc⋅ ⎜ + C1 + C2 ⎟
⎝ Cc ⎠
1 g m1
fT1 ← ⋅
2 ⋅ π Cgg1
1 g m2
fT2 ← ⋅
2 ⋅ π Cgg2
gmID1 ← if ⎛⎜ pgmid L1 , fT1 > 4 ⋅ , pgmid L1 , fT1 , 0.1⋅ ⎞⎟

( ) ( )
1 1
⎝ V V⎠
⎛ 1 1⎞
252
gmID2 ← if ⎛⎜ ngmid L2 , fT2 > 4 ⋅

1⎞
( ) ( )
1
, ngmid L2 , fT2 , 0.1⋅ ⎟
⎝ V V⎠
g m1 g m2
IDtotal ← +
gmID1 gmID2
IDtotal
Initial guess for optimization c1 := 1 c2 := 1

Given c1 > 0 c2 > 0
(
Copt := Minimize f , c1 , c2 )
⎛ 0.145 ⎞ f⎛ Copt , Copt ⎞ = 0.989 mA

Copt = ⎜ ⎟ ⎝ 0 1⎠
⎝ 0.379 ⎠
M := CreateMesh( f , 0.01 , 0.8 , 0.01 , 0.8 , 40 , 40)
M
Comments:
- Shallow power minimum for small c1 and c2
- the optimum is close to the "steep cliff" imposed by limiting gm/ID to practical values >4S/A in the
objective function (in the power minimum, gm/ID1=4.7S/A, gm/ID2=7.7S/A)
253
Re-calculate components with optimizer result:
c1 := Copt c2 := Copt
0 1
Estimate/calculate return factor and all capacitances
Cf
β := β = 0.291
(Cf + Cs)⋅ (1 + c1)
(
Cgg1 := c1 ⋅ Cs + Cf ) Cgg1 = 87.269 fF
Cgg2 := c2 ⋅ CL Cgg2 = 75.833 fF
Lmin
Cdb1 := k dbp ⋅ Cgg1 ⋅ Cdb1 = 44.428 fF
L1
pidw⎛⎜ L1 , 10
S⎞
⎟
w31 :=
⎝ A⎠
w31 = 0.219 Cdb3 := w31⋅ Cdb1 ⋅
k dbn
Cdb3 = 7.903 fF
nidw⎛⎜ L3 , 10 ⋅ g 31⎞⎟
S k dbp
⎝ A ⎠
Lmin
Cdb2 := k dbn ⋅ Cgg2 ⋅ Cdb2 = 43.13 fF
L2
nidw⎛⎜ L2 , 10
S⎞
⎟
w42 :=
⎝ A⎠
w42 = 4.567 Cdb4 := w42⋅ Cdb2 ⋅
k dbp
Cdb4 = 242.447 fF
pidw⎛⎜ L4 , 10 ⋅ g 42⎞⎟
S k dbn
⎝ A ⎠
C1 := Cdb1 + Cdb3 + Cgg2 C1 = 128.164 fF Total stage 1 load
C2 := CL + Cdb2 + Cdb4 + ( 1 − β ) ⋅ Cf C2 = 627.376 fF Total stage 2 load
( )
1
⋅ k B⋅ Tr⋅ γ ⋅ 1 + g 31
β
Cc := 2 ⋅ Cc = 0.34 pF
k B ⋅ Tr
Ntot −
C2 ⎣ ( )
⋅ ⎡γ ⋅ 1 + g 42 + 1⎤
⎦
254
Step 3: Calculate transconductances and transit frequencies
1
g m1 := ⋅ 2 ⋅ π ⋅ fc⋅ Cc g m1 = 1.469 mS
β
k := tan⎛⎜ π ⋅ ⎞
PM
⎟ k = 3.732
⎝ 180deg ⎠
⎛ C2⋅ C1 ⎞
g m2 := k ⋅ 2 ⋅ π ⋅ fc⋅ ⎜ + C1 + C2⎟ g m2 = 4.652 mS
⎝ Cc ⎠
1 g m1
fT1 := ⋅ fT1 = 2.679 GHz
2 ⋅ π Cgg1
1 g m2
fT2 := ⋅ fT2 = 9.763 GHz
2 ⋅ π Cgg2
Step 4: Find gm/ID, ID
( ) ( )
1 1
gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2 gmID1 = 4.639 gmID2 = 6.916
V V
g m1 g m2
ID1 := ID2 := ID1 = 0.317 mA ID2 = 0.673 mA
gmID1 gmID2
Step 5: Calculate device widths
( ) ( )
A A
IDW1 := pidw L1 , gmID1 IDW2 := nidw L2 , gmID2 IDW1 = 9.535 IDW2 = 17.356
m m
ID1 ID2
W1 := W2 := W1 = 33.208 μm W2 = 38.755 μm
IDW1 IDW2
W3 := W1 ⋅ w31 W4 := W2 ⋅ w42 W3 = 7.271 μm W4 = 177.009 μm

255
OTA circuit for simulation (feedback network, CMFB, Cc, etc. not shown)
50uA 100uA 700uA 700uA 700uA
M4c M4a,b
25/0.55 25/0.55
25/0.55
M=7 M=7
M4d
M1a,b
33/0.55
M=2
1/0.4 1/0.4
M3d M3c
M3a,b
1/0.4 M2a,b
M=7 39/0.4
Simulation results (first run, without any tweaking):
f c=181.34MHz, PM=75.68deg, T0=298

Magnitude [dB]
80
60
40
20
0
-20
-40 -2 0 2 4
10 10 10 10
f [MHz]
Phase [degrees]
0
-50
-100
-150
-2 0 2 4
10 10 10 10
f [MHz]
256
PSD [V2/Hz]
-20
10
5 10
10 10
f [Hz]
Sqrt(Integral) [μVrms]
Integral=351.77uVrms, DR=72.09dB (for Vodmax=2.00V)

400
200
0 5 10
10 10
f [Hz]
Very close to specs!
- fc is about 10% lower than expected. This is mostly due to the dominant pole approximation; the
second pole pulls fc to lower frequencies. Also, Cgd of M2 adds additional compensation
capacitance, which also reduces fc.
- PM and DR are essentially right on target.
The discrepancies, in general, can be resolved in two ways: (1) Spice tweaking (OK for small
changes), (2) Re-visit above calculations and improve assumtions and equations. E.g. factor in the
expected error from the dominant pole approximation.
An advantage of the presented methodology is that most, if not all discrepancies/errors can be
tracked down by comparing the Spice component values (gm, gm/ID, Cdb, ... from .op) with those
used in the optimization routine.
Close inspection of the .op values below reveals that most small signal parameters calculated
above agree with Spice to within 10-20%.
257
element 1:m1a 1:m1b 1:m2a 1:m2b 1:m3d 1:m3c
model 0:pch214 0:pch214 0:nch214 0:nch214 0:nch214 0:nch214
id -344.6871u -344.6871u 772.2910u 772.2910u 50.0000u 104.2676u
ibs 0. 0. 0. 0. 0. 0.
ibd 0. 0. 0. 0. 0. 0.
vgs -1.2816 -1.2816 871.7327m 871.7327m 1.0988 1.0988
vds -1.4099 -1.4099 1.4986 1.4986 1.0988 2.0205
vbs 718.4015m 718.4015m 0. 0. 0. 0.
vth -885.7614m -885.7614m 595.0075m 595.0075m 584.3535m 574.9695m
vdsat -384.5490m -384.5490m 205.6017m 205.6017m 304.2131m 307.9633m
vod -395.8371m -395.8371m 276.7252m 276.7252m 514.4807m 523.8647m
beta 3.9883m 3.9883m 23.0145m 23.0145m 531.3387u 1.0629m
gam eff 461.1502m 461.1502m 894.1238m 894.1238m 894.1238m 894.1238m
gm 1.5295m 1.5295m 4.9575m 4.9575m 161.8125u 331.7534u
gds 27.5794u 27.5794u 56.8387u 56.8387u 2.9301u 4.0365u
gmb 282.3301u 282.3301u 1.2918m 1.2918m 42.9472u 86.8132u
cdtot 55.0457f 55.0457f 52.2020f 52.2020f 2.0215f 3.4641f
cgtot 88.4114f 88.4114f 77.6753f 77.6753f 1.7924f 3.5848f
cstot 126.0118f 126.0118f 143.1825f 143.1825f 4.4518f 8.8976f
cbtot 104.3431f 104.3431f 140.4000f 140.4000f 5.1705f 9.7628f
cgs 68.7789f 68.7789f 56.7937f 56.7937f 1.3590f 2.7114f
cgd 15.6526f 15.6526f 9.0726f 9.0726f 207.4045a 414.8090a
element 1:m3b 1:m3a 1:m4d 1:m4c 1:m4b 1:m4a
model 0:nch214 0:nch214 0:pch214 0:pch214 0:pch214 0:pch214
id 344.6871u 344.6871u -104.2676u -703.2478u -772.2910u -772.2910u
ibs 0. 0. 0. 0. 0. 0.
ibd 0. 0. 0. 0. 0. 0.
vgs 1.0988 1.0988 -979.5312m -979.5312m -979.5312m -979.5312m
vds 871.7327m 871.7327m -979.5312m -718.4015m -1.5014 -1.5014
vbs 0. 0. 0. 0. 0. 0.
vth 586.6658m 586.6658m -739.8673m -742.0442m -735.5167m -735.5167m
vdsat 303.2846m 303.2846m -251.4877m -249.7596m -254.9415m -254.9415m
vod 512.1684m 512.1684m -239.6639m -237.4870m -244.0145m -244.0145m
beta 3.7191m 3.7191m 3.0506m 21.3547m 21.3541m 21.3541m
gam eff 894.1238m 894.1238m 472.5709m 472.5709m 472.5709m 472.5709m
gm 1.1179m 1.1179m 741.4965u 5.0238m 5.4115m 5.4115m
gds 27.2459u 27.2459u 13.0870u 115.7219u 74.4836u 74.4836u
gmb 297.8439u 297.8439u 170.1165u 1.1533m 1.2402m 1.2402m
cdtot 14.9146f 14.9146f 49.3740f 364.8318f 316.8690f 316.8690f
cgtot 12.5467f 12.5467f 67.0284f 469.1707f 469.2508f 469.2508f
cstot 31.1678f 31.1678f 109.9526f 769.6267f 769.7437f 769.7437f
cbtot 36.9572f 36.9572f 103.2448f 741.9384f 693.9432f 693.9432f
cgs 9.5188f 9.5188f 50.4655f 353.2113f 353.3468f 353.3468f
cgd 1.4518f 1.4518f 11.8133f 82.6932f 82.6926f 82.6926f
258
Lecture 21
Step Response
Boris Murmann
Stanford University
Overview
• Reading
– 7.5 (Relation Between Frequency and Time Response)
• Reference
– H.C. Yang and D.J. Allstot, "Considerations for fast settling
operational amplifiers," IEEE Trans. Ckts. and Syst., March
1990, pp. 326 – 334.
• Introduction
– OTAs with capacitive feedback are primarily used in
switched capacitor circuits, where fast settling to voltage
steps at the input is critical. In today's lecture we will look at
first and second order behavior in the step response of
feedback OTAs.

259
Motivation
• In switched capacitor circuits, the amplifiers have to respond to

voltage steps
• How fast of a switched capacitor circuit can we build?
Analysis
• Assuming a single pole system, we have
Cf
T0 = β ⋅ Gm Ro β=
V (s) C T0 1 C f + Cs + Cin
A(s ) ≅ out =− s ⋅
Vin ( s ) C f 1 + T0 1 + s Gm
ωc ωc ≅ β ⋅ C Ltot = C L + (1 − β ) ⋅ C f
C Ltot

260
Step Response
Vout ( s ) = A( s ) ⋅ Vin ( s )
Vout ( t ) = L−1 {A( s ) ⋅ Vin ( s )}
⎧ Vstep ⎫
Vout ( t ) = L−1 ⎨ A( s ) ⋅ ⎬=−
Cs T
⋅ Vstep ⋅ 0 ⋅ 1 − e −t / τ ( ) τ=
1
⎩ s ⎭ Cf 1 + T0 ωc
Ideal Static Dynamic

Response Error Error
⇒ ε0 ⇒ εd
Graphical Illustration
Dynamic Static
Error (t) Error
0.8
Vout/Vout,ideal
0.6
0.4
0.2
0
0 2 4 6 8 10
t/τ

261
Design Considerations (1)

• Need large DC loop gain for small static error
– |ε0| ~ 1/T0
– E.g. need T0>1000 for better than 0.1% precision
• Need small τ (large bandwidth) for fast settling
• Can define settling time ts based on tolerable dynamic error
− ε d ,tol = −e −t s / τ
t s = −τ ⋅ ln(ε d ,tol )
1
ts = − ⋅ ln(ε d ,tol )
ωc
εd,tol ts/τ
1% 4.6
0.1% 6.9
0.01% 9.2
10-6 13.8
• Going from 1% dynamic precision to 10-6 necessitates only ~3x

increase in settling time

262

• A switched capacitor circuit operates in two clock phases
• Fitting the required number of time constants within ½ period
lets us relate fCLK to a minimum bandwidth requirement
1 1 1 fc 1
ts = − ⋅ ln(ε d ,max ) < >− ln(ε d ,max )
2π ⋅ f c 2 f CLK f CLK π
ε fc/fCLK
1% 1.5
0.1% 2.2
0.01% 2.9
10-6 4.4
How Fast Can We Go?
• fc cannot be larger than about 1/3 of the nondominant amplifier

pole frequency (stability)
– In a cascoded amplifier, the nondominant pole occurs at a
frequency around fT/3
• Assuming that two junction caps equal to Cgg are present
– At a reasonable bias, the NMOS transit frequency in our
technology is roughly 8GHz (nominal process and
temperature)
• Putting all of this together, and assuming that we'll need to settle
to within 0.01% (~9 time constants), we have
1 fT f
f CLK ,max = ⋅ ≅ T = 266 MHz
2.9 9 30

263
Practical Aspects
• In practice, it is hard to achieve fCLK> fT/50

– Amplifier topology restriction
• E.g. sometimes forced to use PMOS in signal path
– Restrictions on power dissipation
• Near the technology limits, power tends to grow out of bounds
– Timing overhead to produce non-overlapping clocks
• Have somewhat less than half clock cycle to settle
– Other transient effects
• We'll look at some of those next…
Impact of Non-Dominant Pole
[Yang, IEEE TCAS 3/1990]

(see also appendix)

264
Simulation Example
• Using simple single stage (single pole) OTA

• Parameters
– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85, Vidstep=-10mV
Result
1 C L + (1 − β )C f β ⋅ Gm R0
τ= = 21ns Vod , final = −Vidstep = 9.76 mV
β Gm 1 + β ⋅ Gm R0
1000
-V
800 id
Vod (simulation)
Voltage [mV]
600 V (theory?)
od
400
200
0 50 100 150 200

Time [ns]
265
Another Run
• Changed CL from 10pF to 300fF
10
-V
id
5 V (simulation)
Voltage [mV]
od
Vod (theory?)
-5
0 5 10 15 20 25
Time [ns]
• What's this ?
Capacitive Feedforward
• In the first instant after the input step has been applied, the
output is completely determined by capacitive voltage division
• Half circuit during initial transient:
Vodstep Cs Cf
= ⋅
Vidstep C f CL C f + CL
Cs + Cin +
C f + CL

266
Analysis
• Can analyze this effect in two (equivalent) ways
– Using capacitive divider to find new starting point of
exponential
– Using inverse Laplace transform of A(s) with feedforward
zero included
• Recall from lecture 14, that A(s) is more precisely given by
s Gm
1− z=
Cs z ⋅ T0
A(s ) = − Cf
C f 1 − s 1 + T0
p βGm
p=−
C L + (1 − β )C f
New Result
⎧ Vstep ⎫ Cs T ⎛ ⎡ p⎤ ⎞
Vod ( t ) = L−1 ⎨ A( s ) ⋅ ⎬=− ⋅Vidstep ⋅ 0 ⋅ ⎜⎜ 1 − ⎢1 − ⎥ e −t / τ ⎟⎟
⎩ s ⎭ Cf 1 + T0 ⎝ ⎣ z⎦ ⎠
New
p CL + (1 − β )C f + βC f CL + C f 1
1− = = =
z C L + (1 − β )C f C L + (1 − β )C f Cf
1− β
C f + CL
• For our example:

1
= 1.4 ⇒ Vod ( t = 0 ) ≅ 10 mV (1 − 1.4 ) = −4 mV
500 fF
1 − 0.48
500 fF + 300 fF
• Good agreement with simulation

267
New Settling Time
1 ⎛ ⎡ C f ⎤ ⎞⎟
ts = − ⋅ ln⎜ ε d ,tol ⎢1 − β ⋅ ⎥
ωc ⎜⎝ ⎣⎢ C f + CL ⎦⎥ ⎟⎠
<1
• Settling time for given precision increases due to feedforward,

since the settling range is artificially enlarged
• E.g. in our simulation example, the time to settle within 0.1%
dynamic error increases from 6.9τ to 7.3τ
– Not extremely significant, especially when β is low and CL is
at least comparable to Cf
Appendix
"Bandwidth and Settling of a Two-Pole Feedback Amplifier"

268
Bandwidth and Settling of a Two-Pole Feedback Amplifier
Boris Murmann
Single Pole Amplifier (for reference) 11/11/2006
β ⋅ T0 β ⋅ Gm⋅ R 1
T( s) = T( s) = =
s 1 + sRC 1 C
1− + s⋅
p1 β ⋅ Gm⋅ R β ⋅ Gm
1
T( s) =
For large DC loop gain: C
s⋅
β ⋅ Gm
Unity gain frequency of T(s)
1 Gm
=1
C ω c1 = β ⋅
j ⋅ ω c1⋅ C
β ⋅ Gm
Phase margin
PM1 = 180deg + arg⎛⎜ ⎞

1
⎟ PM1 := 90deg
ω c1
⎜j ⎟
⎜ ω c1 ⎟
⎝ ⎠
Closed loop 3-dB frequency (neglecting feedforward effects)
(
T jω3dB ) =
1
1
=
1 1
=
1
ω 3dB = ω c1
( ) ω 3dB 2 2 2
1 + T jω3dB 2 1+j ⎛ ω 3dB ⎞⎟
ω c1 1+⎜
⎜⎝ ω c1 ⎟⎠
Linear settling time

t
−
τ 1
Step response: u( t) = 1 − e τ =
ω c1
ts
−
Dynamic error at t=ts εd = e
τ
( )
ts = −τ ⋅ ln ε d
269
Two- Pole Amplifier
1
T( s) =
⋅ ⎛⎜ 1 − ⎞
s s
ω c1 p2 ⎟
⎝ ⎠
Unity gain frequency of T(s)
1
=1 ω c2 ω p2
ω c2 ⎛ ω c2 ⎞ m= n=
j ⋅⎜1 + j ⎟ ω c1 ω c1
ω c1 ⎜ ω p2 ⎟
⎝ ⎠
2
m⋅ 1 + ⎛ m⎞ = 1 m( n ) :=
1 2
⋅ 2 ⋅ n ⋅ n + 4 − 2n
2
⎜n⎟
⎝ ⎠ 2
0.9
m( n)
0.8
0.7
1 2 3 4 5
n
Non-dominant pole moves crossover point to slightly lower frequencies (as one would predict
from first order model). E.g. for a nondominant pole with a frequency of ~three times the
crossover frequency (n=3), the crossover shifts to ~0.95*wc1.
Phase margin
ω p2
PM2 = 180deg + arg⎡⎢ ⎤ = 180 ⋅ deg − 90deg + arg⎛ ⎞
1 1
⎥ ⎜ ⎟ k=
ω c2 ⎛ ω c2 ⎞ ω c2 ω c2
⎢j ⋅⎜1 + j ⎟ ⎥ ⎜1 + j⋅
⎟
⎢ ω c1 ⎜ ω p2 ⎟ ⎥ ⎜ ω p2 ⎟
⎣ ⎝ ⎠⎦ ⎝ ⎠
270
PM2( k ) := 90deg − atan⎛⎜

1⎞
⎟
⎝k⎠
90
80
70
180
PM2( k) ⋅
π
60
50
40
1 2 3 4 5 6 7 8
k
1
k ( PM2) :=
tan⎜
⎛ π − PM2⎞
⎟
⎝2 ⎠
4
⎛
k⎜PM⋅
π ⎞
⎟
⎝ 180 ⎠
3
1
45 50 55 60 65 70 75 80
PM
271
Closed loop 3-dB frequency (neglecting feedforward effects)
ω ω p2
A( ω ) =
1
w= n=
ω ω c1 ω c1
1+j
⎛
⋅⎜1 + j
ω ⎞
ω c1 ω p2
⎟
⎝ ⎠
1 1
A( w , n ) := c( w) :=
1 + j w⋅ ⎛⎜ 1 + j
w⎞ 2
⎟
⎝ n⎠
1.5
A ( w , 1)
A ( w , 2)
1
A( w , 100)
c( w ) 0.5
0
0.1 1 10
w
1
=
1 ω 3dB ω p2
1 + j r⋅ ⎛⎜ 1 + j
r⎞ 2 r= n=
⎟ ω c1 ω c1
⎝ n⎠
2
⎛ 2⎞
⎜ 1 − r ⎟ + r2 = 2 r( n ) :=
1 2 2
⋅ 4⋅ n − 2⋅ n + 2⋅ n⋅ n − 4⋅ n + 8
⎝ n⎠ 2
1.4
r( n) 1.3
1.2
1.1
2 4 6 8 10
n
For wp2=3*wc1, closed loop bandwidth is about 35% higher than first order prediction
272
Linear settling time

2
1 1 1 U( s) = k ⋅ ω c1 ω p2
U( s) = ⋅ = ⋅ k=
⋅ ⎛⎜ 1 + ⎞
s s s s 2 2 ω c1
1+ k ⋅ ω c1 + s⋅ k ⋅ ω c1 + s
ω c1 ω p2 ⎟
⎝ ⎠
s1 2 s2 2
2
k ⋅ ω c1 + s⋅ k ⋅ ω c1 + s = 0
2
=−
k
+ ⎛k⎞ − k =−
k
− ⎛k⎞ − k
⎜2⎟ ⎜2⎟
ω c1 2 ⎝ ⎠ ω c1 2 ⎝ ⎠
k ⎛ 4⎞ k ⎛ 4⎞
s1n( k ) := − ⋅ ⎜ 1 + 1− ⎟ s2n( k ) := − ⋅ ⎜ 1 − 1− ⎟
2 ⎝ k⎠ 2 ⎝ k⎠
2
1 k ⋅ ω c1
U( s) = ⋅ a = s1n⋅ ω c1 b = s2n⋅ ω c1
s (s − s1n⋅ ω c1)⋅ (s − s2n⋅ ω c1)
2 ⎛ 1 e
a⋅ t
e
b⋅ t ⎞
tn = t⋅ ω c1
u ( t) = k ⋅ ω c1 ⋅ ⎜ + + ⎟
⎝ a⋅ b a( a − b ) b ( b − a) ⎠
s 1n( k) ⋅ tn s2n( k) ⋅ tn
k⋅ e k⋅ e
( )
k
u tn , k := + +
s1n( k ) ⋅ s2n( k ) s1n( k ) s1n( k ) − s2n( k ) (
s2n( k ) s2n( k ) − s1n( k ) ) ( )
( )
u tn , 1 1.1
u( tn , 2)
u( tn , 3)
1
0.9
0 2 4 6 8 10
tn
273
( ) (
ε d t n , k := u tn , k − 1 )
(
t sn ε dspec , k :=) (
t s ← −ln ε dspec + 10 )
( )
while ε d t s , k < ε dspec
t s ← ts − 0.01
ts
( )
return
−ln ε dspec k := 1 , 1.1 .. 8
Relative settling time versus k=wp2/wc1 for various dynamic error specs
1.4
1.2
1
tsn( 0.01% , k)
tsn( 0.1% , k)
0.8
tsn( 1% , k)
1 0.6
0.4
0.2
0
1 2 3 4 5 6 7 8
k
274
1
k ( PM2) :=
⎛ π − PM2⎞ PM := 50 , 51 .. 90
tan⎜ ⎟
⎝2 ⎠
1.4
1.2
⎛ ⎛
tsn⎜0.01% , k⎜PM⋅
π ⎞⎞
⎟⎟ 1
⎝ ⎝180 ⎠⎠
⎛ ⎛
tsn⎜0.1% , k⎜PM⋅
π ⎞⎞
⎟⎟ 0.8
⎝ ⎝ 180 ⎠⎠
⎛ ⎛
tsn⎜1% , k⎜PM⋅
π ⎞⎞
⎟⎟
⎝ ⎝ 180 ⎠⎠ 0.6
1
0.4
0.2
0
50 60 70 80 90
PM
Conclusion: Try to target phase margin between 70...75 degrees; amplifier then
settles ~30% faster than single pole system (ignoring second order effects).
275
Lecture 22
Slewing
Boris Murmann
Stanford University
Overview
• Reading
– 9.6.1, 9.6.2, 9.6.5 (Slew Rate)
• Introduction
– Today we'll complete our discussion of transient behavior in
OTA circuits with capacitive feedback. Aside from the
feedforward artifact we've discovered last time, there exists
another effect called "slewing". Whenever the differential
input pair is driven outside its "linear range", the differential
output current is limited by the available tail bias. In typical
switched capacitor circuits, slewing can cause a significant
speed reduction, and is therefore an important effect to
consider.

276
Simulation Example from Last Lecture
• Using simple single stage OTA (See lecture 15, slide 3)

• Parameters
– Cs=Cf=500fF, CL=10pF, β=0.48, Gm=1mS, GmRo=85
Another Simulation
• Set Vidstep=-1V (CL=10pF ⇒ insignificant feedforward to output)
1000
800
-Vid
Voltage [mV]
600 Vod (simulation)

Vod (theory?)
400
200
0 50 100 150 200

Time [ns]
• What causes this discrepancy ?

277
Capacitive Divider at OTA Input

• Half circuit during initial transient:
Cs 500 fF
Vxdstep = Vidstep ≅ −1V = −480 mV
C f CL 500 fF + 40 fF + 500 fF
Cs + Cin +
C f + CL
• Initially -480mV across differential pair input!
Differential Pair Characteristics

• Differential output current begins to saturate ~|Vid| > 1.4·2/(gm/ID)
• Beyond this point, current will be much less than⎝ that predicted
by linear model (slope at origin)
1
Slope = 1
Iod/ITAIL 0
1
2 1 0 1 2
-√2 Vid/(2/[gm/ID]) √2

278
Differential Pair Input Voltage vs. Output Current
0
-100
-200 "Slewing" "Linear Settling"
Vxd [mV]
-300
-400 -1.4·2/gm/ID)
-500
0 50 100 150
Time [ns]
0
Diff. pair I od [μA]
-100
-200
-300
0 50 100 150
Time [ns]
Slewing
• During "slewing", the amplifier drives its output with a constant

current (equal to tail bias)
• The slewing behavior ends when |Vid| has become smaller than
about 1.4·(2/gm/ID)
– This is the point when the differential pair re-enters its "linear
region"
– Hence, the remaining portion of the settling is often called
"linear settling"
• Even though the output voltage really settles with a (1-et/τ)
relationship
• The total settling time of the amplifier in presence of slewing can
be calculated as shown in the following derivation

279
Slew Rate
• In order to find the time it takes to complete slewing, we can first

calculate the "ramp speed" at which the output changes
– This quantity is called "Slew Rate" (SR)
dVod I TAIL I TAIL

SR = = =
dt CLtot CL + (1 − β )C f
Slewing Time
• The input of the differential pair changes at a rate equal to β·SR,
where β is given by the usual capacitive feedback divider
• Hence, the time it takes to complete slewing is given by
Vxstep − 2.8 / (g m / I D )
t slew =
β ⋅ SR
• In our example, we have

I TAIL 200 μA V
SR = ≅ = 20
C Ltot 10 pF μs
480 mV − 280 mV
t slew = = 21ns
V
0.48 ⋅ 20
μs

280
Subsequent Linear Settling

• Once slewing is completed, the differential output voltage is
Vod ,slew = t slew ⋅ SR = 420 mV
• The final settling value in our example is roughly 1V

– Almost half way there after slewing
• This means that the dynamic error budget for the remaining
settling portion has increased
– E.g. if we wanted to settle within 0.1% of the final value
(~1V), we only need to complete the remaining transient to
within 0.1%·1V/0.58V=0.17%
– Not a very big win, usually a negligible change in the number
of required time constants
• 0.1%→6.9τ, 0.17% → 6.4τ
Complete Expression for Settling Time
Vxstep − 2.8 / ( g m / I D )
t s = t slew + tlin ≅ − τ ln(ε d ,tol )
β ⋅ SR
I TAIL I TAIL Cf
SR = = β=
C Ltot C L + (1 − β )C f C f + Cs + Cin
Cs Cs
Vxdstep = Vidstep ≅ Vidstep
C f CL Cs + Cin + C f
Cs + Cin +
C f + CL
<1
• Note that circuits with large closed loop gain tend to slew less
– Since Vidstep cannot be larger than Voutputswing/Gain
– E.g. Voutputswing=2V, Gain =8 ⇒ Vxdstep < Vidstep < 250mV
• Won’t slew at all if gm/ID < 2.8/250mV= 11.2V-1

281
Slewing in a Two-Stage OTA (1)
• Nodes V1p and V1m stay roughly constant

– These nodes move at a rate equal to the slew rate Vop, Vom
divided by ~ intrinsic gain of second stage
– Second stage acts as "integrator"
• Must design circuit such that slew rate is limited by ITAIL

– IB2 limitation would cause asymmetric slewing
• One branch slew limited by IB2, other slew limited by ITAIL
– Asymmetric slewing causes CM shift
• Causes slow transients due to slow CMFB
282
• The maximum slew rate at which output Vom can move down
d (Vom − V1 p ) ⎧I / 2 I B2 / 2 ⎫
SR− ,MAX = = min⎨ TAIL , ⎬
dt ⎩ Cc Cc + C Ltot ⎭
• The maximum slew rate at which output Vop can move up
d ( Vop − V1m ) I /2
SR+ ,MAX = = TAIL
dt Cc
• To make slew rates equal, we need
ITAIL I B2
≤
Cc Cc + C Ltot
Slewing in "Continuous Time" Circuits

• Slewing is not only an issue in switched capacitor circuits, it can
also limit the large signal performance of continuous time circuits
• Example:
vo (t ) = Vˆo sin (ωt )
iout dvo
iout (t ) = CL
Vout dt
Vin
= ω ⋅ C L ⋅ Vˆo cos(ωt )
CL
îout = ω ⋅ C L ⋅V̂o
• At large frequency and/or amplitude, the peak output current needed

can exceed the maximum current available from the amplifier

283
Resulting Waveform
• When slewing is an issue, it can be mitigated by biasing the

relevant transistors at lower gm/ID
– Increase ID, keep gm constant
– Slewing performance improves, because of larger ID and
also because the differential pair input range increases
(2.8/[gm/ID])
– Small signal performance remains virtually unchanged or
improves if fT is a limiting factor (since fT increases)
– Issue: Lower gm/ID means higher power consumption

284
How to Incorporate Slewing in Design Flow
• Set up a spreadsheet for small signal design as usual

– Settling time requirement translates into minimum "linear"
bandwidth spec (based on linear analysis, without slewing)
• Introduce a bandwidth spec scale factor K≥1 in your design
script
– If the circuit slews, we will need more bandwidth than
predicted from linear analysis
• Perform design optimization as usual, begin with K=1
• Calculate slewing time, add to linear settling time
– Done if tslew=0
• Increase K until design meets settling time spec
– In the process, you may consider to optimize gm/ID values to
minimize power in presence of slewing

285
Lecture 23
Feedback and Port Impedances
OTA Variants, CMFB Implementation
Boris Murmann
Stanford University
Overview
• Reading
– 8.8.2 (Closed-Loop Impedance Formula using Return Ratio)
– 6.7 (MOS Active-Cascode Amplifiers)
– 12.5 (CMFB Circuits)
– 12.6 (Fully Differential Amplifiers)
– 9.4.4 (Compensation of Single Stage CMOS OTAs)
• Reference
– K. Bult, G.J.G.M. Geelen, "A fast-settling CMOS op-amp for SC circuits with
90-dB DC gain," IEEE J. Solid-State Circuits, Dec. 1990, pp. 1379 – 1384.
• Introduction
– In order to complete our framework for feedback circuit analysis, we will
study the effect of feedback on port impedances in today's lecture. A useful
analytical tool for quick calculations is Blackman's Impedance Formula,
which allows us to find port impedances based on a superposition of simple
sub-analyses.
– Next, we survey common OTA architectures and associated implementation
aspects. Most OTAs used in practice are derivatives of the basic single- or
two-stage topology, with add-ons such as simple cascodes or gain boosted
cascodes. The survey concludes with a brief analysis of the most commonly
used common mode feedback implementations.

286
Using Feedback to Modify Port Impedances
• Our initial motivation for using feedback was to build precise

gain elements that are insensitive to gmR variations
• In addition, feedback can be used to increase/decrease port
impedances
– In fact, we have already seen one example of such behavior
• Closed loop bandwidth of OTA feedback amplifier was (1+T)
higher than open loop bandwidth
• This means the impedance seen by the load capacitor must
have dropped in presence of feedback
• We can calculate the port impedances of arbitrary feedback
circuits using "Blackman's Impedance Formula"
– Based on loop gain calculations
– Extremely useful and easy to use
Blackman's Impedance Formula
1 + T ( port shorted )
Z port = Z port (k = 0 ) ⋅
1 + T ( port open )
1. First, find port impedance with feedback loop broken

– E.g. set gm=0
2. Calculate loop gain in circuit with port under consideration shorted
3. Calculate loop gain in circuit with port under consideration open
• In many cases, either the "shorted" or "open" loop gain is zero

287
Example 1
1
Rout (k = 0 ) = Rout (av = 0 ) =
gm
T ( port shorted ) = 0
T ( port open ) = av
1 1
Rout =
g m 1 + av
Example 2: Shunt-Shunt Stage
Rin ( g m = 0 ) = RF + ro Rout (g m = 0 ) = ro
T (input shorted ) = 0 T (output shorted ) = 0
T (input open ) = g m ro T (output open ) = g m ro
1 1 ⎛ RF ⎞ 1 1
Rin = (RF + ro ) ≅ ⎜1 + ⎟ Rout = ro ≅
1 + g m ro g m ⎜⎝ ro ⎟⎠ 1 + g m ro g m

288
Example 3: Active Cascode
• Also referred to as "Regulated Cascode" or "Gain Boosting"

technique
Rout (av = 0 ) ≅ r01 ⋅ g m 2 ro 2
T ( port open ) = 0
gm2
T ( port shorted ) ≅ av ≅ av
g m 2 + g mb 2
Rout ≅ r01 ⋅ g m 2 ro 2 ⋅ (av + 1)

≅ r01 ⋅ g m 2 ro 2 ⋅ av
Basic Implementation
• Can use simple CS stage as

auxiliary amplifier
– Issue: Costs headroom
• See literature for more advanced
implementations
– E.g. using fully differential
folded cascode amplifier as an
auxiliary amplifier
Rout ≅ r01 ⋅ g m 2 ro 2 ⋅ g m 3 ro 3

289
Properties
• Must compensate local feedback loop such that its crossover

frequency ωc occurs before non-dominant pole at source of M2.
• Consideration of the total impedance at the output node
(including CL) shows that gain boosting introduces a pole zero
doublet around ωc
– Can result in slow step response, if not designed carefully
– See Bult, JSSC 12/1990 for design considerations
• In typical designs, "gain boosting" adds about 20-30% to the
total power dissipation of an OTA
OTA Variants: Telescopic OTA
• Approximately same gain

as two stage amplifier,
with only two current legs
– Maximum power
efficiency
• Issue: Low swing
– Especially if input and
output common mode
cannot be chosen
freely

290
Biasing
• Typically use at least 20% of tail

current in auxiliary biasing branch
– Must avoid slow recovery of
this node during transients
• Can use several device in series
to implement MB1
– "1/3rd or 1/5th" device
– Helps avoid extremely small
width for MB1
Folded Cascode OTA
• Large input
common mode rage
• Slightly improved
output range
• Folding adds power
dissipation

291
Compensation
AC Half Circuit for Telescopic OTA AC Half Circuit for Folded Cascode OTA
• Nondominant pole ωp2=gm1a/Cp

– Cp=Cgs1a+Cj1a+Cj1
• Easy to compensate
– Make k·β·gm1/CL < ωp2
– k=3 for 72° phase margin
Current Mirror OTA
k 1 1 k
• Gm=k·gm1,2, ωp2 ~ ωT/(1+k)

• Large swing
• Good for low speed, low power applications
– See e.g. Yao, JSSC 11/2004

292
All NMOS Signal Path (1)
[Feldman et al., JSSC 10/1998]
• Capacitive level shift allows NMOS in second stage
All NMOS Signal Path (2)
[Yang et al., JSSC 12/2001]
• Differential pair and separate common mode feedback in

second stage
293
Gain Boosted Gain Boosters
[Chiu et al., ISSC 2004]
• Gain ~ gmro6, design achieved av0=130dB in 0.18μm technology
Common Mode Feedback
• Implementation aspects
– How to sense
– How to compare to desired value
– How to provide a "knob" for adjusting Voc

294
Knob
• Typically generate ~80% of tail current with fixed bias, leave

remaining 20% as tuning range for CMFB loop
Comparison Circuit
• Low frequency loop gain T0 ≅ 0.25·gmx·rop1 · gmp2/gmx

– Loop will control Voc more accurately if Mp1 is cascoded

295
Sensing
• Using a resistive divider may destroy differential gain

• Solutions
– Use source followers to drive divider (headroom issue)
– Purely capacitive sensing
CMFB Implementation Example
• Circuit uses switched

capacitors (CM) to set the
voltage across sensing
capacitors (CCM)
[Feldman et al., JSSC 10/1998]

296
"Passive" CMFB (1)
• During φ1: Initialize voltage across Ccmfb to Voc,desired - VB

• During φ2: Activate feedback loop
– If Voc>Voc,desired, Vcntrl becomes >VB and lowers Voc
"Passive" CMFB (2)
• OTA cannot be used during φ1, because the common mode

feedback mechanism is inactive
– Often not a problem in switched capacitor circuits, where the
OTA is active only during one half-cycle
• Can use switched capacitor scheme shown on slide 22 to
enable uninterrupted common mode feedback
• Unfortunately, this simple circuit cannot be used if an additional
inversion is needed in the common mode feedback loop
– E.g. won't work for a two-stage OTA that uses a single
common mode feedback loop (see e.g. slide 9, lecture 18)
– Will work for the two-stage OTA with separate CMFB loops
as shown on slide 16

297
Common Mode Half Circuit
• Low frequency loop gain:
g Ccmfb
T0 ≅ mx rop ⋅
2 C
Ccmfb + x
2
• Loop crossover frequency

1 Ccmfb g mx
ωc ≅
2 Cx Ccmfb ⋅ 0.5C x
Ccmfb + C +
2 L Ccmfb + 0.5C x
• Nondominant pole
g mn
ω p2 ≅
Cy
• The required bandwidth of the common mode loop strongly
depends on the amount of expected imbalance, common mode
transients or ac components
– In an ideal world, the common mode is not affected by the
signal and hence stays constant
• In this case, the bandwidth of the CMFB loop is unimportant
• For robustness in practical implementations, the bandwidth of
the common mode loop is often chosen to be about 30% of the
differential signal path bandwidth
– In a typical switched capacitor circuit with 10 time constants
differential settling, this means that the common mode has
about 3 time constants to settle
• Enough time to remove 95% of common mode disturbance

298
Lecture 24
OTAs with Single Ended Outputs
Output Stage Examples
Boris Murmann
Stanford University
Overview
• Reading
– 4.3.5 (Differential Pair with Current Mirror Load)
– 6.3.3 (Systematic Offset in Two-Stage Amplifier)
– Chapter 5 (Output Stages)
• Introduction
– This lecture concludes our discussion of amplifier implementations
by looking at a number of missing bits and pieces. First, we will
discuss subtleties of OTA implementations that use a single ended
output. While rarely used in the signal path of high performance
integrated circuits, OTAs with single ended outputs can be useful
as auxiliary amplifiers in biasing circuits. Finally, we will take a brief
look at output stages that are suitable for driving resistive loads.
While most on-chip loads tend to be capacitive in nature, low
impedance drivers are often needed when interfacing to off-chip
components and wire lines.

299
Single Ended OTA
• Current mirror performs "differential to single-ended conversion"
Mirror Doublet
• Half of the output current comes directly from the differential
pair, the other half goes through a current mirror with finite
bandwidth
– Result: Pole-zero doublet
⎛ ⎞
⎜ ⎟
⎜ 1 1 1 ⎟
io = g m vid +
⎜2 2 s⎟
⎜ 1− ⎟
⎝ p⎠
s
1−
2p
= g m vid
s
1−
p
• In the circuit on the previous slide p ≅ -ωTp/2 (neglecting

junctions)
300
Unity Gain Buffer
• Closed loop gain ≅ 1

• Output impedance ≅ 1/gm
• Output range equal to common mode input range
– Advantageous to use a folded cascode OTA architecture
Inverting Amplifier
• Cx = ?, T(s) = ?
– Big mess…

301
Two-Stage OTA with Single Ended Output
Systematic Offset
• No offset if VGS6=VGS3
balances the current in
the output branch
• Input referred
systematic offset is
(VGS6,balance-VGS3)/av1,
where av1 is the gain of
the first stage

302
Output Stages
• Needed to drive resistive loads (low R)
– Integrated continuous time RC-filters
– Off-chip resistive loads
– Line drivers
• E.g. twisted pair (Ethernet, ISDN, ADSL)
• Solutions
– Use OTA + source follower output stage
• Swing issue
– Use OTA + "low gain" common source stage
• E.g. make gm·RL~1
• E.g. 20mS·50Ω =1, IBIAS=20mS·10V-1 = 2mA
– "Sophisticated" output stages
• Examples on following slides
Output Stage Nomenclature (1)

• Class-A
– Output devices conduct for entire cycle of output sine wave
– E.g. source follower with constant current source bias
• Class-B
– Output devices conduct for ≅50% of sine wave cycle
– E.g. back-to back PMOS/NMOS source followers
• NMOS and PMOS each conduct for about one half cycle
• No quiescent current during zero crossing of sine wave
• Class-AB
– Output devices conduct for >50%, but <100% of cycle
– E.g. a simple inverter
• Problem: How to set quiescent current around zero crossing
• Needs local or global feedback to mitigate nonlinearity

303
Output Stage Nomenclature (2)
Class-A Class-B
Class-AB Class-C
Selected References on Output Stages
• D. M. Monticelli, "A quad CMOS single-supply op amp with rail-

to-rail output swing," IEEE J. Solid-State Ckts., pp. 1026-1034,
Dec. 1986.
• R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H.
Huijsing, "A compact power efficient 3 V CMOS rail-to-rail
input/output operational amplifier for VLSI cell libraries," IEEE J.
Solid-State Ckts., pp. 1505 - 1513, Dec. 1994.
• G. Palmisano, G. Palumbo, and R. Salerno, "CMOS Output
Stages for Low-Voltage Power Supplies," IEEE Trans. Ckts. and
Syst. II, pp. 96-104, Feb. 2000.

304
Class-AB Output Stage
[Hogervorst]
Output Current (Vo=0)
• Output transistors
never turn off
• Quiescent current
Iout
Current [A]
ID(M26) set by transistor

ratios
ID(M25)
• Large drive
capability
Iin1=Iin2 [A]

305
Complete OpAmp
[Hogervorst]
Low Voltage Variant
<Vtn+|Vtp|
[Palmisano]

306
Complete OpAmp
<Vtn+|Vtp|
[Palmisano]
A Note on General Purpose OpAmps

• Issue: Compensation
– The designer of a general purpose OpAmp does not know
anything about the feedback network of the particular
application
– General purpose OpAmps are typically compensated for the
"worst case", i.e. unity feedback configuration
• Tends to be wasteful, since much less compensation is needed
for smaller return factors
– Some general purpose OpAmps provide an external pin to
let the user decide on the required compensation capacitor

307
Lecture 25
Supply Insensitive Biasing
Boris Murmann
Stanford University
Overview
• Reading
– 4.4.2 (Supply Insensitive Biasing)
• Introduction
– Throughout this course, we have ignored the question on
how to generate the reference bias currents used in most of
our circuits. Today, we will examine a variety of current
reference implementations, with primary focus on supply
independence.

308
Poor Man's Bias
VDD − Vt − VOV
I OUT ≅ I IN =
R
• Issue: Current is essentially proportional to VDD

– E.g. if VDD varies by X%, bias current will roughly vary by the
same amount
"Vt" Referenced Bias
2 I IN
Vt +
W
μCox
VGS 1 Vt + VOV L
I OUT = ≅ ≅
R2 R2 R2
• By using a sufficiently large device,

we can make VOV << Vt, and achieve
Vt
I OUT ≅
R2
• Question: By how much will IOUT

change given some variation in VDD?

309
Sensitivity
• The sensitivity of a parameter y to a change in parameter x can
be approximately found using
Δy / y ∂y / y x ∂y ! y
≅ = = Sx
Δx / x ∂x / x y ∂x
• In our case, we are looking for
SVIDD
OUT
= SVIDD
IN
⋅ S IIINOUT
I IN ∂I OUT
≅ 1⋅ ⋅
I OUT ∂I IN
1 VOV 1 1 0.1V
≅ e.g . = 7.1%
2 Vt + VOV 1 2 0.6V + 0.1V
• Not bad, but also not all that great…
BJT Version
VBE 1 1 kT ⎛ I IN ⎞
I OUT = = ln⎜ ⎟
R2 R2 q ⎜⎝ I S ⎟⎠
kT
q 26 mV
SVIDD
OUT
= e.g . = 3.7%
VBE 700 mV

310
Stability
g m 2 R2 1 1
T (s ) ≅ g m1 R1 ⋅ ⋅ ⋅
1 + g m 2 R2 1 + s s
1+
ω p1 ω p2
• Loop gain greater 1 at low

frequencies, two poles
– Means that we must make one of
the poles dominant to guarantee
sufficient phase margin
• E.g. use large capacitance to
ground at drain of T1
Self Biasing
• In the above discussed bias generator circuits, the supply
sensitivity is still fairly high, because IIN is essentially directly
proportional to VDD
• Idea: Mirror output current back to input instead of using supply
dependent input current!

311
Start-Up Circuit
(WEAK)
• Unfortunately, self-biasing comes with a built in "chicken and

egg problem"
– There exists a stable operating point with all currents =0
– Can use a simple start-up circuit to solve this problem
VBE Reference
VBE 1
I OUT =
R
• Utilizes "parasitic" substrate PNP transistor available in any

CMOS technology

312
Temperature Dependence (1)

• Similar to the sensitivity to supply variations, we can establish
an expression for temperature variations
– Fractional temperature coefficient
∂I OUT
TC F = ∂T
I OUT
• For the circuit on the previous slide we have
∂I OUT 1 ∂VBE 1 VBE 1 ∂R

= − 2
VBE 1 ∂T R ∂T R ∂T
I OUT =
R ⎛ 1 ∂VBE 1 1 ∂R ⎞
= I OUT ⎜⎜ − ⎟
⎝ VBE 1 ∂T R ∂T ⎟⎠
Temperature Dependence (2)

• Final result
1 ∂VBE 1 1 ∂R
TC F = −
VBE 1 ∂T R ∂T
• Temperature dependence is usually quite high
1 ∂VBE 1 − 2mV / K
≅ = −0.33% / K
VBE 1 ∂T 600 mV TC F = −0.53% / K
1 ∂R
≅ +0.2% / K (poly resistor)
R ∂T
• E.g. ΔT=100K ⇒ ΔI=-53% (!)

313
ΔVBE Reference
I OUT ⋅ R = VBE 1 − VBE 2

kT ⎛ I IN ⎞ kT ⎛ I OUT ⎞
= ln⎜ ⎟− ln⎜ ⎟⎟
q ⎜⎝ I S 1 ⎟⎠ q ⎜⎝ I S 2 ⎠
kT ⎛ I IN I S 2 ⎞
= ln⎜ ⎟
q ⎜⎝ I S 1 I IN ⎟⎠
kT
= ln(n )
q
1 kT
I OUT = ln(n )
R q
TC of ΔVBE Reference
∂VT ∂R
R − VT kT
∂I OUT ∂T ∂T VT =
= ln(n ) q
∂T R 2
VT ⎛ 1 ∂VT 1 ∂R ⎞
= ln(n ) ⎜ − ⎟
R2 ⎜⎝ VT ∂T R ∂T ⎟⎠
1 ∂VT 1 ∂R 1 1 ∂R
TC F = − = −
VT ∂T R ∂T T R ∂T
• Example 1
TC F = − 0.2% / K = 0.13% / K
300 K
• TC of resistor and kT/q partially cancel!

314
ΔVGS Reference (1)
I REF ⋅ R2 = VGS 1 − VGS 2

= VOV 1 − VOV 2
⎛ 1 ⎞
≅ VOV 1 ⎜ 1 − ⎟
1 m ⎝ m⎠
⎛ 1 ⎞
VOV 1 ⎜ 1 − ⎟
I REF ≅ ⎝ m⎠
R2
[Lee, 2nd ed. p.326]
• Strange result, why is this useful?
ΔVGS Reference (2)

• The transconductance of M1 is approximately
⎛ 1 ⎞
2 ⋅ ⎜1 − ⎟
2 I D1 2 I REF 1
= ⎝
m⎠
g m1 = =
VOV 1 VOV 1 R2
• Transconductance of M1 and other devices biased using this

circuit depend only on m and R2!
– This is why this bias circuit is more appropriately called
"constant gm reference"
• Design aspects
– Can use off-chip resistor to set gm precisely
– Large VOV helps reduce mismatch errors
– Small I⋅R2 makes circuit less sensitive to body effect

315
Constant Settling Time Bias (1)

• Reference
– I. E. Opris, L. D. Lewicki, "Bias optimization for switched
capacitor amplifiers,"IEEE TCAS II, pp. 985-989, Dec. 1997.
Settling time with constant bias current

• Settling time of amplifier is given by
Vo ,slew ⋅ C C
t s = t slew + tlin ≅ +N
I β ⋅ gm
• Constant gm bias helps, but is not optimum for minimizing

process variations
• Really want a bias circuit that keeps ts constant

316
ΔV
I = I0 +
R
Vo ,slew ⋅ C C
ts ≅ +N
I β ⋅ gm
C⎛ I ⎞
⇒I ≅ ⎜⎜Vo ,slew + N ⎟
ts ⎝ β ⋅ g m ⎟⎠
• Can make setting time

"constant" by choosing
⎛ 1 ⎞
2 ⋅ β ⋅ ts ⋅ ⎜ 1 − ⎟
Vo ,slew ⋅ C ⎝ k⎠
I0 ≅ R≅
ts N ⋅C

317
Lecture 26
Bandgap Reference
Boris Murmann
Stanford University
Overview
• Reading
– 4.4.3 (Temperature Insensitive Biasing)
• Introduction
– In this lecture we will introduce the basic idea behind the
frequently used "bandgap" voltage reference. Conceptually,
a bandgap reference simply combines two quantities with
opposite temperature behavior to generate a voltage with
(approximately) zero TC.

318
Key Idea
• kT/q has a positive temperature coefficient

– "PTAT" proportional to absolute temperature
• VBE of a BJT decreases with temperature
– "CTAT" complementary to absolute temperature
• Can combine PTAT + CTAT to yield an approximately zero TC
voltage reference
– Useful in circuits that require a stable reference voltage
• E.g. A/D converters
Conceptual Block Diagram

319
A Closer Look at VBE
kT ⎛ I C ⎞
VBE = ln⎜ ⎟
q ⎜⎝ I S ⎟⎠
• Even though kT/q increases with temperature, VBE decreases
because IS itself strongly depends on temperature
kT ⎛ I C VG 0 /( kT / q ) ⎞
VBE ≅ ln⎜ e ⎟⎟
q ⎜⎝ I 0 ⎠
kT ⎛ I 0 ⎞
≅ VG 0 − ln⎜ ⎟
q ⎜⎝ I C ⎟⎠
• I0 is a device parameter, which is (unfortunately) not completely

independent of temperature
– We'll ignore this for now
• VG0 is the bandgap voltage of silicon "extrapolated to 0°K"
Extrapolated Bandgap
[Pierret, Advanced
Semiconductor
1.205eV Fundamentals, p.85]
1.205eV
VG 0 = = 1.205V
q

320
Temperature Coefficient of VBE

kT ⎛ I 0 ⎞
VBE ≅ VG 0 − ln⎜ ⎟⎟
q ⎜⎝ I C ⎠
• Assuming that both I0 and IC are constant over temperature
dVBE k ⎛I ⎞ VBE − VG 0
≅ − ln⎜⎜ 0 ⎟⎟ =
dt q ⎝ IC ⎠ T
• Example
dVBE 0.6V − 1.205V mV
≅ = −2.02
dt 300 K K
CTAT + PTAT
• Returning our initial idea, we can now find the condition that
gives us a temperature independent voltage
kT kT ⎛ I 0 ⎞ kT
VBE + M ≅ VG 0 − ln⎜⎜ ⎟⎟ + M
q q ⎝ IC ⎠ q
⎛ ⎛ ⎞⎞
≅ VG 0 +
kT ⎜ M − ln⎜ I 0 ⎟ ⎟
q ⎜ ⎜ I ⎟⎟
⎝ ⎝ C ⎠⎠
• Combining VBE and an appropriately scaled version of kT/q

produces a temperature independent voltage, equal to VG0

321
Simple CMOS Realization
ΔVBE 1 kT
I1 = I 2 = = ln(n )
R1 R1 q
R2 kT
Vout = VBE 1 + ln(n )
R1 q
Choice of n
• Usually make n=integer2-1, e.g. n=8

• Layout:

322
Design Example
• From measurement data, we know that |VBE| of a unit device is

700mV at room temperature and I=50μA
• Decided to use n=8
1 kT 1
R1 = ln(n ) = 26 mV ln(8 ) = 1.08 kΩ
I2 q 50 μA
VGO − VBE 1 1.205V − 0.7V
R2 = R1 = 1.08 kΩ = 9.34 kΩ
kT
ln(n ) 26 mV ln (8 )
q
Nonidealities
• "Curvature"
– Temperature dependence of I0
• Offset voltages and TC of offset voltages
• Resistor mismatch and TC
• Finite β and β mismatch
• More next lecture…

323
Lecture 27
Bandgap Reference
(Continued)
Boris Murmann
Stanford University
Overview
• Reading
– 4.4.3 (Temperature Insensitive Biasing)
• Introduction
– Today's lecture will cover several important details that
we've left out in our previous analysis of bandgap
references. We will discuss nonidealities such as "curvature"
and the impact of offset voltages. Finally, we will take a brief
look at state-of-the art implementations and performance.

324
Selected References (1)

• R. J. Widlar, "New developments in IC voltage regulators," IEEE
J. Solid-State Circuits, pp. 2-7, Feb. 1971.
– First report, LM309 5V regulator
• A. P. Brokaw, "A simple three-terminal IC bandgap reference,"
IEEE J. Solid-State Circuits, pp. 388-393, Dec. 1974.
– A classic implementation
• C. Palmer and R. Dobkin, "A curvature corrected micropower
voltage reference," IEEE Int. Solid-State Conference, pp. 58-59,
Feb. 1981.
• G. Nicollini et al., "A CMOS bandgap reference for differential
signal processing," IEEE J. Solid-State Circuits, pp. 41-50, Jan.
1991.
– Offset compensated amplifier
Selected References (2)

• T.L. Brooks et al., "A low-power differential CMOS bandgap
reference," IEEE Int. Solid-State Conf., pp. 248-249, Feb. 1994.
– Differential output, stacked diodes
• H. Banda et al. "A CMOS bandgap reference circuit with sub-1-
V operation," IEEE J. Solid-State Circuits, pp. 670 - 674, May
1999 .
• P. Malcovati et al., "Curvature-compensated BiCMOS bandgap
with 1-V supply voltage," IEEE J. Solid-State Circuits, pp. 1076-
1081, July 2001.

325
VBE Revisited
• Last lecture, we assumed that

kT ⎛ I 0 ⎞
VBE ≅ VG 0 − ln⎜ ⎟
q ⎜⎝ I C ⎟⎠
• A more accurate, but empirical model is given by
kT ⎛ K 1 ⋅ T r ⎞
VBE ≅ VG 0 − ln⎜ ⎟⎟
q ⎜⎝ I C ⎠
• The temperature dependence inside the logarithm slightly
curves the VBE vs. temperature characteristic
– TC of VBE is not quite independent of temperature
• Parameter r depends on technology, typically 3…6
Curvature
[Lee, 2nd ed., p.322]

326
Collector Current
• Another superficial assumption was to assume that the current

IC is independent of temperature
– Actually PTAT in the example circuit from last lecture
– Also affected by TC of resistors
• To capture the temperature behavior of IC, we can introduce yet
another empirical fudge factor and write
kT ⎛ T r ⎞
VBE ≅ VG 0 − ln⎜ K ⎟
q ⎜⎝ T n ⎟⎠
• The factor n is 1 for ideal PTAT current behavior
Modified TC of VBE
• With this refinement, we have
dVBE d ⎡ kT ⎛ T r ⎞⎤
≅ ⎢− ln⎜ K ⎟⎥
dT dT ⎣ q ⎜⎝ T n ⎟⎠⎦
k ⎛ T r ⎞ kT K (r − n )T r − n −1
≅ − ln⎜⎜ K n ⎟⎟ −
q ⎝ T ⎠ q Tr
K n
T
k ⎡ ⎛ Tr ⎞ ⎤
≅ − ⎢ln⎜⎜ K n ⎟⎟ − (r − n )⎥
q⎣ ⎝ T ⎠ ⎦
kT
VG 0 − VBE + (r − n )
q
=−
T

327
Modified Condition for Zero-TC
kT
VG0 − VBE + (r − n )
kT dVBE k q
0=M + =M −
q dT q T
⎡ kT ⎤
⎢VG0 − VBE + (r − n ) q ⎥
⇒M = ⎣ ⎦
kT
q
• Or, more interestingly

kT
Vout = VG 0 + (r − n )
q
• Must design for Vout that is a few kT/q higher than VGO
Modified Output Voltage
[Lee, 2nd ed., p.323]
• Getting good temperature stability typically requires some

tweaking or calibration
– Some semiconductor foundries provide tried and true
bandgap cells that are optimized for a particular technology

328
Curvature Compensation
[Palmer]
• Control current such that the impact of "(r-n) term" is minimized

• In practice, curvature compensation may not be all that effective
if other nonidealities dominate…
Offset Voltage
ΔVBE 1 ⎛ kT ⎞
I1 = I 2 = = ⎜⎜ ln(n ) − VOS ⎟⎟
R1 R1 ⎝ q ⎠
R2 ⎛ kT ⎞
Vout = VBE 1 + VOS + ⎜⎜ ln(n ) − VOS ⎟⎟
R1 ⎝ q ⎠
R2 ⎛ kT ⎞ ⎛R ⎞
= VBE 1 + ⎜⎜ ln(n )⎟⎟ − VOS ⎜⎜ 2 − 1 ⎟⎟
R1 ⎝ q ⎠ ⎝ R1 ⎠

329
Issues
• VOS appears amplified at the bandgap output and can cause a
large absolute error in Vout
– Since R2/R1-1 ≅ 8, this means that for VOS=5mV, the error in
Vout will be about 40mV or roughly 3.3%
• If the bandgap is trimmed after manufacturing, e.g. to yield an
output of VGO+2kT/q, then this is no longer the point of zero TC
in presence of VOS
• In CMOS, VOS drift is typically 1…10μV/K
– This means Vout will drift at least 8μV/K, which corresponds
to about 6.6 ppm/K
• Good CMOS bandgaps achieve about 10…50ppm/K
• Possible solutions
– Mitigate impact of offset by stacking two VBE
– Cancel offset or use low offset BJT differential pair
SC Bandgap with Offset Cancellation
[Nicollini]

330
Bandgap with stacked VBE
[Brooks]
Sub-1-V Bandgap
≅1.2V
⎛ kT ⎞
⎜ ln( N ) ⎟
V q
Vref = R4 ⎜ BE + ⎟
[Banba] ⎜ R2 R3 ⎟
⎜ ⎟
⎝ ⎠
• Idea: Add currents proportional to VBE and kT/q, instead of

stacking voltages

331
Variant with Curvature Compensation
Low offset amplifier
[Malcovati]
Performance

332
Lecture 28
Technology Scaling
Boris Murmann
Stanford University
Overview
• Introduction
– The trend of continuously shrinking feature sizes in
integrated circuits has resulted in enormous performance
gains in both digital and analog circuits. However, since
device scaling necessitates the use of smaller supply
voltages, it is often argued that noise limited circuits can no
longer benefit from scaling. In this lecture, we will take a
closer look at this argument and also review basic analog
device performance trends in light of feature size reduction.

333
The Age of "Moore's Law"

• In 1965, Gordon Moore predicted that there will be an
exponential growth in the number of transistors per integrated
circuit
… And He was Right
[Moore, ISSCC 2003]

334
Smaller
Minimum Feature Size
Faster

335
Cheaper
Average Transistor Price
Misnomer
• The term "Moore's Law" was coined by the press
– Of course, the exponential progress rate is not set by
fundamental law
– Merely a rate of progress that makes sense for the industry
and keeps things predictable for all involved players
• Device technologists
• Makers of manufacturing equipment
• Circuit designers
• Sales and marketing
• The dirty truth is that Moore's law is mostly just a gigantic
economic feedback loop
– With lot's of great innovation fueled by $$$

336
Moore's Law in Action
$$$
Worldwide Semiconductor Sales
[European
Nanotechnology
Roadmap]

337
State-of-the-Art Semiconductor Fab

• Cost ~ $3,000,000,000
State-of-the-Art Silicon Technology

• 90nm feature sizes, electrical channel length of 50nm
• Gate oxide thickness 1.2nm, roughly 5 atomic layers
• 8 Layers of metal routing

338
State-of-the-Art Chips
Single-Chip 802.11
Transceiver
[Zargari, ISSCC 2004]
Pentium 4 Processor,
125 Million Transistors
[Schutz, ISSCC 2004]
Impact of Technology Scaling
• Scaling is great from a digital perspective!

• Can show that scaling down features and voltages achieves
three things simultaneously
– Higher speed
– More transistors/area
– Lower energy per operation
• How about analog circuits?

339
Quotes
• [Vertregt, ESSCIRC 2004]

– "Significant power efficiency improvements are predicted as a
result of scaling to deep sub-micron technology nodes."
• [Annema, IEEE J. Solid-State Circuits, 12/2005 ]
– "In summary: unlike digital designs, analog circuits can benefit from
technology scaling if the supply voltages are not scaled down."
• [Nauta, ESSCIRC 2005]
– "The evolution of CMOS technology will continue for many years to
come, which is beneficial for digital circuits but which is not so for
analog."
List of Concerns
• Reduced supply voltage

• Low intrinsic gain
• Variability
• Distortion
• Gate leakage
• Isolation
• …
• Cost (mask & wafer)
• Model accuracy
• …

340
gm/ID and fT trends

(a)
40 160
30 180nm 120 • gm/ID essentially

130nm
unaffected by
gm /ID [S/A]
fT [GHz]
90nm
20 80
scaling
10 40
• Very high fT in
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
0
0.6
recent technologies
VGS-Vt [V]
– Enables RF
(b)
1200 CMOS
180nm
1000 130nm
(gm /ID)*fT [GHz*S/A]
90nm
800
600
400
200
0
-0.4 -0.2 0 0.2 0.4 0.6
VGS-Vt [V]
Available Signal Swing

5
3
VDD [V]
0
0.50um 0.35um 0.25um 0.18um 0.12um 90nm 65nm 45nm 32nm
Technology Node
VDD
> 4kT/q
kT
Available Swing < VDD − 8
q
> 4kT/q

341
Noise Limited Circuit Performance
g Swing 2
P ∝ VDD ⋅ I D BW ∝ m DR ∝
C kT / C
2
BW ⋅ DR ⎛ Swing ⎞ g m
∝ VDD ⋅ ⎜⎜ ⎟⎟ ⋅
P ⎝ VDD ⎠ I D
• Low VDD is generally bad news, but

– Analog designers have worked hard to maintain or even
improve Swing/VDD
• Typical ADC in 0.5μm: Swing/VDD=2/5
• Typical ADC in 90nm: Swing/VDD=0.5/1
– How about gm/ID?
Leveraging fT
40 160
30 180nm 120
130nm
gm /ID [S/A]
fT [GHz]
90nm
20 80
10 40
0 0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
VGS-Vt [V]
• Example
– fT = 50GHz, 130nm: gm/ID = 8S/A, 90nm: gm/ID = 16S/A
• For "fixed-speed" applications, high fT can be leveraged to mitigate low
VDD penalty

342
Further Considerations
• Analog building blocks are never completely limited by thermal noise

– Not uncommon to have ~50% dynamic power
• Decreases with scaling
• Designers are continuing to develop/refine low-voltage design
techniques
– Recent publications show very good analog building block
performance at 1V
• Bottom line
– Analog design is challenging at 1V, but it's neither impossible
nor detrimental
Intrinsic Gain
(a)
250
180nm
200 130nm • A real issue
90nm
150
– How to design a high-
ID [μA]
100
gain op-amp with devices
(VGS-Vt=100mV) that have intrinsic gain of
50
~10?
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VDS [V] • How much worse does this
(b) get at 45nm/65nm?
50
40
30
gm /gds
20
180nm
10 130nm
90nm
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VDS [V]

343
Intrinsic Gain in the Near Future
15
10
gm /gds
45nm (TCAD)
5 65nm (TCAD)
(VGS-Vt=100mV)
90nm (BSIM4)
0
0 0.2 0.4 0.6 0.8 1
VDS [V]
• Pretty bad…
• Solutions
– Use non-minimum length device (NML-device)
– Use asymmetric device without drain-side pocket implant (A-
device)
– Or, don't try to build op-amps in these technologies…
• E.g. "Digitally Assisted ADC" research in my group
A-Device vs. Standard Device

HoleImpactIonization HoleImpactIonization
Signed Log Signed Log
-0.16
-0.16
26.58 26.52
23.2 23.2
20.3 20.3
-0.12
-0.12
17.4 17.4
14.5 14.5
11.6 11.6
-0.08
-0.08
8.7 8.7
5.8 5.8
2.9 2.9
-0.04
-0.04
0 0
0
0
0.04
0.04
0.08
0.08
0.12
0.12
0.16
0.16
0.2
0.2
0.24
0.24
0.28
0.28
0.32
0.32
0.36
0.36
0.4
0.4
0.44
0.44
-0.16 -0.12 -0.08 -0.04 0 0.04 0.08 0.12 0.16 -0.16 -0.12 -0.08 -0.04 0 0.04 0.08 0.12 0.16
• Removing halo widens depletion region

– Reduces impact ionization and improves output resistance

344
Intrinsic Gain of Alternate Devices (45nm)
( )
150
Min. length
NML-device
100 A-device
gm /gds
50 (VGS-Vt=100mV)
(VGS-Vt=100mV)
0
0 0.2 0.4 0.6 0.8 1
VDS [V]
• For both NML and A-device Lphysical=80nm (Lphysical=24nm for

minimum length device)
• Great, lots of gain!
– But how about fT?
gm/ID and fT for Alternate Devices (45nm)

(a)
40 800
30 600 • fT much lower than

Minimum length
for minimum length
gm /ID [S/A]
fT [GHz]
NML-device
20 A-device 400
45-nm device
10 200
– But still better
0 0 than minimum
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VGS-Vt [V] length device in
5000
(b) 90nm…
Minimum length
4000 NML-device
• Who needs fT >
(gm /ID)*fT [GHz*S/A]
A-device
3000 200GHz in an op-

2000
amp…?
1000
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VGS-Vt [V]

345
Variability (1)
[Courtesy A. Bowling,
Texas Instruments]
Variability (2)
• Must keep in mind that even if we draw nice colorful rectangles

in our CAD tools, things won't come out like that…
• Device shape strongly depends on surroundings
• Good old layout recipes become more important and must be
applied even when only "moderate" matching in required
– Use unit devices
– Match surroundings of unit devices

346
Variability (3)
[Marcel Pelgrom, NXP]
• Device mismatch larger than process corner variations!

– For small "digital" transistors…
Variability (4)
Digital Analog
• A "new" problem • A well known problem
– Significant impact on – Designers are used to
achievable performance, "caring" about mismatch
yield, design
• Lots of options and potential
methodology, EDA, …
solutions
• Big difference compared to – Layout techniques,
analog analog or digital
– Care about millions if not calibration, dynamic
billions of devices! element matching, larger
device area, …
• Usually care about matching
for a few up to a few hundred
transistors
347
An Interesting Hike Lies Ahead…
Bag of
Tricks
A
Cost – The "Real" End of The Roadmap?
[Marcel Pelgrom, NXP]
• Reference point: 30 mm2 die in 0.12μm CMOS

348
Lecture 29
Class Summary
Project Discussion
Boris Murmann
Stanford University
Transistor Models
• Any model is an approximation of the real world
– Must leave many details out
– Must retain the important details (to be useful)
– Appropriate level depends on questions you want to answer
• BSIM model/Spice
• gm/ID approach
• Long channel equations
• When designing and analyzing circuits, we are usually forced to
use much simpler models than the ones available in Spice
– gm/ID methodology partially closes this gap
• A "good" IC designer is always on the lookout for modeling
limitations!

349
Transistor Figures of Merit
• Transit Frequency
gm
ωT =
C gg
• Current Efficiency
gm
ID
• Intrinsic Gain
gm
g ds
Circuit Analysis
• Once we have appropriate models, we can in principle analyze
any circuit using KCL/KVL
– Usually too difficult and also won’t allow us to reason about
design choices and tradeoffs
• Crutches for circuit analysis
– Small signal approximation
– Zero value time constant method
– Miller approximation
– Return ratio analysis
– Blackman's impedance formula
– …
• Again, a good designer will always be on the lookout for
potential limitations of the respective analysis method

350
The "Atoms" of Analog Circuit Design
• Common source
– Basic voltage amplifier
• Common gate
– Good for "shielding"
– Can help boost output impedance, mitigate Miller effect
• Common drain
– Buffer, level shifter
• Differential pair
Feedback (1)
• Desensitizes circuit to (forward-) gain variations
• Modifies port impedances
• Central quantity of interest: Loop gain T
– Quantifies static error
– Used to assess stability, phase and/or gain margin
– Helpful in calculating closed loop port impedances
• Finding T is simple
– E.g. break loop at transconductor, inject test current,
calculate ratio of return and test current
• Typically need a dominant pole
– Hard to use more than 2-3 amplifier stages and maintain
sufficient phase margin

351
Feedback (2)
• Impact of phase margin on step response
– Excessive "ringing" for phase margin <60°
– Fast settling for phase margin ~70°
• Impact of phase margin on closed loop AC response
– Gain peaking and slightly larger 3-dB bandwidth for small
phase margin
• Compensation techniques
– Can use simple load compensation for single stage OTAs
– Miller compensation is most popular for two-stage designs
• Can push parasitic zero to infinity using nulling resistor
• Beware of tricks such as pushing the zero into the LHP to avoid
pole-zero doublets
– Cascode compensation
• For designers with experience…
OTAs with Capacitive Feedback

• Primary application: Switched capacitor circuits
• Important performance metric: Settling time
– Small signal model fails when input exceeds "linear range"
– Slew rate ~ I/C
– ts = tlin + tslew
• High performance OTAs are usually implemented as fully
differential circuits
– Need CMFB
– Better XXX-rejection than single ended circuits
– Easy to analyze, since circuit is "perfectly" balanced
• Exceptions occur during transients, in presence of mismatch,
etc.

352
Electronic Noise
• Tends to set achievable power dissipation in circuits with high

DR requirements
• Fundamental noise
– Thermal noise
• Technology related noise
– 1/f noise
• Increasing (noise limited) precision by "one bit" quadruples
power dissipation!
References
• Self-biasing concept
– Beware of stability issues!
• Current references
– VDD, VGS, ΔVGS, VBE, ΔVBE - based approaches
– To first order, ΔVGS bias yields constant gm over temperature
and process
• Voltage reference
– Bandgap
– Useful as a reference whenever there's a need to convert
"bits to Volts" or "Volts to bits"
– Conceptually simple, but lots of second order issues

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1

B. Murmann EE 214 Introduction 1

A Few Words About Your Instructor

• Assistant Professor in EE since 2004

B. Murmann EE 214 Introduction 2

EE214 Basics (1)

B. Murmann EE 214 Introduction 3

EE214 Basics (2)

B. Murmann EE 214 Introduction 4

B. Murmann EE 214 Introduction 5

• Please remember you are bound by the honor code

B. Murmann EE 214 Introduction 6

Be Reasonable When Asking TAs

B. Murmann EE 214 Introduction 7

• We will HSpice for circuit simulation

B. Murmann EE 214 Introduction 8

The Spice Monkey Problem (1)

• What most people know

B. Murmann EE 214 Introduction 9

The Spice Monkey Problem (2)

B. Murmann EE 214 Introduction 10

Analysis versus Design

B. Murmann EE 214 Introduction 11

• Develop deeper understanding of MOS device behavior relevant

B. Murmann EE 214 Introduction 12

Preview - Design Example of Lecture 20

B. Murmann EE 214 Introduction 13

• CMOS technology and device models

B. Murmann EE 214 Introduction 14

B. Murmann EE 214 Lecture 1 1

B. Murmann EE 214 Lecture 1 2

The Big Picture

• Most modern electronic information processing systems rely on

B. Murmann EE 214 Lecture 1 3

Vacuum Tube Transistor Modern Discrete

B. Murmann EE 214 Lecture 1 4

45nm CMOS (Intel)

B. Murmann EE 214 Lecture 1 5

B. Murmann EE 214 Lecture 1 6

B. Murmann EE 214 Lecture 1 7

Discrete vs. Integrated Circuits

Discrete Audio Amplifier Integrated CMOS Audio Amplifier

• Minimize transistor count • "Unlimited" number of transistors

B. Murmann EE 214 Lecture 1 8

Modern Integrated Circuit Technologies

Parameter CMOS Si BJT SiGe BJT

• Why use CMOS for analog integrated circuits?

B. Murmann EE 214 Lecture 1 9

Basic MOS Operation (1)

• With zero voltage at the gate, device is "off"

B. Murmann EE 214 Lecture 1 10

Basic MOS Operation (2)

• With a positive gate bias applied, electrons are pulled toward

Basic Operation (3)

• If we now apply a positive drain voltage, current will flow

B. Murmann EE 214 Lecture 1 12

B. Murmann EE 214 Lecture 2 1

B. Murmann EE 214 Lecture 2 2

Basic MOS Operation

• How can we calculate ID as a function of VGS, VDS?

B. Murmann EE 214 Lecture 2 3

1) Current is controlled by the mobile charge in the channel. This is a very

B. Murmann EE 214 Lecture 2 4