Advantages of 3D Packaging Technology Over Conventional Technologies

The shift from conventional single chip packages to 3D technology, leads to substantial size and weight reductions. The main limiting factors for 3D technology are (i) the interconnection capacity (see subsection ), (ii) the thermal characteristics, and (iii) the required robustness. It has been reported that a 40-50 times reduction in size and weight is achievable using 3D technology compared to conventional packaging. As an example, volume and weight comparisons between Texas Instrument's 3D bare dice packaging, discrete and planar packaging (MCM) are presented in Tables and . It is evident from Table that a 5-6 times reduction in volume, over MCM technology, and a 10-20 times volume reduction, over discrete packaging technology, is possible. Moreover, a 2-13 times reduction in weight, compared to MCM technology, and a 3-19 times weight reduction, compared to discrete components, is also achievable. All of these reductions result from eliminating the overhead weight and size associated with conventional technologies.

Type SRAM DRAM

Capacity 1 Mbit 4 Mbit 1 Mbit 4 Mbit 16 Mbit

Discrete 1678 872 1357 608 185

Planar 783 249 441 179 69

3D 133 41 88 31 69

Discrete/3D 12.6 21.3 15.4 19.6 16.8

Planar/3D 5.9 6.1 5.0 5.0 6.2

Table: 3D Mass memory volume comparison between other technologies and Texas 3D technology in cm /Gbit (Adapted from [11]).

Type SRAM DRAM

Capacity 1 Mbit 4 Mbit 1 Mbit 4 Mbit 16 Mbit

Discrete 3538 1588 2313 862 363

Planar 2540 862 1542 590 227

3D 195 145 132 113 113

Discrete/3D 18.1 10.9 17.5 7.6 3.2

Planar/3D 13.0 5.9 11.6 5.2 2.0

Table: 3D Mass memory weight comparison between other technologies and Texas 3D technology in grams /Gbit (Adapted from [11])
In response to the increasing challenges in maintaining technology advancements through traditional scaling at a pace consistent with Moore's law, alternative methods to achieve enhanced system level performance are becoming increasingly important. 3D Technology has the potential to provide significant performance enhancements for several generations. Realization of this technology will require collaborative research and development across system architecture, design, and technology. Significant changes to the basic circuit design, layout procedures and tools flow, as well as the routing of global signals and supplies (power/ground distribution, clock distribution, and I/O), will be required to accommodate the 3D technology features in stacked active chip designs. These changes can only be understood through a detailed evaluation of the impact of each of the unique 3D technology elements on the design. The Research Division is involved in leading the exploration of these new aspects of 3D VLSI chip design for future systems.