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VIDEO TECHNICAL GUIDE

DIGITAL VIDEO MOVIE

GR-DVL9500 NTSC/PAL

COPYRIGHT 1999 VICTOR COMPANY OF JAPAN, LTD.

December 1999

INDEX
SECTION 1 EXPLANATION OF NEW TECHNOLOGIES ADOPTED FOR GR-DVL9500 SERIES
1.1 CONCEPTION TO DEVELOP GR-DVL9500 SERIES .......................................................1-1 1.2 OUTLINE OF DOUBLE-SPEED VIDEO RECORDING (SHOOTING)................................1-2 1.2.1 Double-speed recording in brief .....................................................................................1-2 1.2.2 Outline of double-speed video recording and playback of double-speed recorded video......................................................................1-2 1.3 PS CCD.............................................................................................................................1-4 1.3.1 Principle of CCD operation in double-speed shooting ....................................................1-4 1.3.2 Readout area and recording picture in double-speed shooting ......................................1-6 1.4 VIDEO SIGNAL OF DOUBLE-SPEED SHOOTING (RECORDING) ..................................1-6 1.4.1 Video signal of double-speed shooting (1) .....................................................................1-6 1.4.2 Video signal of double-speed shooting (2) .....................................................................1-6 1.4.3 Video signal in slow playback.........................................................................................1-7

SECTION 2 CIRCUIT DESCRIPTION


2.1 DESCRIPTION OF PS CCD OPERATIONS ......................................................................2-1 2.1.1 CCD pin assignment and block diagram ........................................................................2-1 2.1.2 CCD pin functions..........................................................................................................2-2 2.1.3 3-Phase Drive Vertical CCD...........................................................................................2-3 2.1.4 Transmission to Horizontal CCD from Vertical CCD.......................................................2-3 2.1.5 Transmission between Horizontal CCDs ........................................................................2-4 2.1.6 2-channel Output Horizontal CCD..................................................................................2-5 2.1.7 Pilot Signal Generator....................................................................................................2-5 2.1.8 Drive Timing (NTSC)......................................................................................................2-6 2.2 CDS AGC (IC5101/IC5102) ...............................................................................................2-7 2.2.1 CDS AGC (IC5101/IC5102) pin assignment and block diagram.....................................2-7 2.2.2 CDS AGC (IC5101/IC5102) pin functions ......................................................................2-8 2.3 T. G (IC5002) .....................................................................................................................2-9 2.3.1 TG (IC5002) pin assignment ..........................................................................................2-9 2.3.2 T. G (IC5002) pin functions ............................................................................................2-10 2.4 V. DRIVER (IC4101) ..........................................................................................................2-12 2.4.1 V. DRIVER (IC4101) pin assignment..............................................................................2-12 2.4.2 V. DRIVER (IC4101) block diagram ...............................................................................2-13 2.4.3 V. DRIVER (IC4101) pin functions .................................................................................2-14 2.5 ADC (IC4201/IC4202)........................................................................................................2-15 2.5.1 ADC (IC4201/IC4202) pin assignment ...........................................................................2-15 2.5.2 ADC (IC4201/IC4202) block diagram .............................................................................2-15 2.5.3 ADC (IC4201/IC4202) pin functions ...............................................................................2-16 2.6 DSP (IC4301) ....................................................................................................................2-17 2.6.1 DSP (IC4301) pin assignment and block diagram..........................................................2-18 2.6.2 DSP (IC4301) pin functions............................................................................................2-19

INDEX-1

2.7 FM (IC4302) ......................................................................................................................2-24 2.7.1 FM (IC4302) pin assignment..........................................................................................2-24 2.7.2 FM (IC4302) block diagram............................................................................................2-25 2.7.3 FM (IC4302) pin functions..............................................................................................2-26 2.8 DVIO (IC3202) ...................................................................................................................2-28 2.8.1 DVIO (IC3202) pin assignment and block diagram ........................................................2-28 2.8.2 DVIO (IC3202) pin functions ..........................................................................................2-29 2.9 PLL (IC3201) .....................................................................................................................2-33 2.9.1 PLL circuit description....................................................................................................2-33 2.9.2 PLL (IC3201) pin assignment.........................................................................................2-34 2.9.3 PLL (IC3201) block diagram ..........................................................................................2-34 2.9.4 PLL (IC3201) pin functions.............................................................................................2-35 2.10 SHUFFLE MEMORY (IC3002).........................................................................................2-36 2.10.1 Shuffle memory (IC3002) pin assignment ....................................................................2-36 2.10.2 Shuffle memory (IC3002) pin functions ........................................................................2-37 2.11 COMPRESS/AUDIO/SHUFFLE (CAS) (IC3001)..............................................................2-39 2.11.1 CAS (IC3001) pin assignment and block diagram ........................................................2-39 2.11.2 CAS (IC3001) pin functions..........................................................................................2-40 2.12 ECC/DCI/ATF (EDA) (IC3003) .........................................................................................2-43 2.12.1 EDA (IC3003) pin assignment and block diagram ........................................................2-43 2.12.2 EDA (IC3003) pin functions..........................................................................................2-44 2.13 DYNAMIC DRAM (DRAM) (IC3004) ................................................................................2-48 2.13.1 DRAM (IC3004) pin assignment...................................................................................2-48 2.13.2 DRAM (IC3004) block diagram ....................................................................................2-48 2.13.3 DRAM (IC3004) pin functions ......................................................................................2-49 2.14 VITERBI A/D (IC3005) .....................................................................................................2-51 2.14.1 VITERBI A/D (IC3005) pin assignment and block diagram...........................................2-51 2.14.2 VITERBI A/D (IC3005) pin functions ............................................................................2-51 2.15 PRE/REC (IC3502)..........................................................................................................2-52 2.15.1 PRE/REC (IC3502) pin assignment and block diagram ...............................................2-52 2.15.2 PRE/REC (IC3502) pin functions .................................................................................2-53 2.16 PB EQUALIZER (IC3501)................................................................................................2-55 2.16.1 PB_EQ (IC3501) pin assignment and block diagram ...................................................2-55 2.16.2 PB_EQ (IC3501) pin functions .....................................................................................2-56 2.16.3 PB EQ circuit ...............................................................................................................2-58 2.17 EVR DA CONV. (IC3503).................................................................................................2-59 2.17.1 DAC (IC3503) pin assignment .....................................................................................2-59 2.17.2 DAC (IC3503) block diagram .......................................................................................2-59 2.17.3 DAC (IC3503) pin functions .........................................................................................2-60

INDEX-2

2.18 ENV D/A CONV. (IC1201)................................................................................................2-61 2.18.1 ENV D/A CONV. (IC1201) pin assignment ...................................................................2-61 2.18.2 ENV D/A CONV. (IC1201) block diagram.....................................................................2-61 2.18.3 ENV D/A CONV. (IC1201) pin functions .......................................................................2-62 2.19 DIGITAL INTERFACE (IC8001) .......................................................................................2-63 2.19.1 Digital IF (IC8001) pin assignment and block diagram .................................................2-63 2.19.2 Digital IF (IC8001) pin functions ...................................................................................2-64 2.20 MSD CPU (IC1401) .........................................................................................................2-68 2.20.1 MSD CPU (IC1401) pin assignment.............................................................................2-68 2.20.2 MSD CPU (IC1401) pin functions.................................................................................2-69 2.21 SYSCON CPU (1001)......................................................................................................2-73 2.21.1 SYSCON CPU (1001) pin assignment .........................................................................2-73 2.21.2 SYSCON CPU (IC1001) pin functions..........................................................................2-74 2.22 MDA (IC1601)..................................................................................................................2-78 2.22.1 MDA (IC1601) pin assignment .....................................................................................2-78 2.22.2 MDA (IC1601) block diagram .......................................................................................2-79 2.22.3 MDA (IC1601) pin functions .........................................................................................2-80 2.23 ON SCREEN (OSD) (IC1002)..........................................................................................2-82 2.23.1 OSD (IC1002) pin assignment .....................................................................................2-82 2.23.2 OSD (IC1002) block diagram .......................................................................................2-82 2.23.3 OSD (IC1002) pin functions .........................................................................................2-83 2.24 FOCUS & ZOOM DRIVER (IC4851) ................................................................................2-84 2.24.1 Focus & Zoom driver (IC4851) pin assignment and block diagram ..............................2-84 2.24.2 Focus & Zoom driver (IC4851) pin functions ................................................................2-85 2.25 VIDEO OOUTPUT DRIVER (IC3701) ..............................................................................2-86 2.25.1 VIDEO OOUTPUT DRIVER (IC3701) pin assignment and block diagram....................2-86 2.25.2 VIDEO OOUTPUT DRIVER (IC3701) pin functions .....................................................2-87 2.26 VF LCD DRIVER (IC7401)...............................................................................................2-88 2.26.1 VF LCD DRIVER (IC7401) pin assignment and block diagram ....................................2-88 2.26.2 VF LCD DRIVER (IC7401) pin functions .....................................................................2-89 2.27 LCD MONITOR DRIVER (IC7301)...................................................................................2-91 2.27.1 LCD MONITOR DRIVER (IC7301) pin assignment ......................................................2-91 2.27.2 LCD MONITOR DRIVER (IC7301) block diagram........................................................2-92 2.27.3 LCD MONITOR DRIVER (IC7301) pin functions .........................................................2-93 2.28 AUDIO AMP (IC2201)......................................................................................................2-95 2.28.1 AUDIO AMP (IC2201) pin assignment .........................................................................2-95 2.28.2 AUDIO AMP (IC2201) block diagram ...........................................................................2-96 2.28.3 AUDIO AMP (IC2201) pin functions .............................................................................2-97 2.29 16BIT A/D, D/A CONV. (IC2101)......................................................................................2-98 2.29.1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram ...........................2-99 2.29.2 16BIT A/D, D/A CONV. (IC2101) pin functions .............................................................2-99
INDEX-3

2.30 REGULATOR CTL (IC6101) ............................................................................................2-100 2.30.1 REGULATOR CTL (IC6101) pin assignment................................................................2-100 2.30.2 REGULATOR CTL (IC6101) pin functions ...................................................................2-101

INDEX-4

SECTION 1 EXPLANATION OF NEW TECHNOLOGIES ADOPTED FOR GR-DVL9500 SERIES


1.1 CONCEPTION TO DEVELOP GR-DVL9500 SERIES
In the video camera market this year, it is expected that the digital video camera will have an 80 percent market share, and its market size is estimated about 250 billion yen including peripheral equipment market. Such being the case, small-sized and high performance video products are and will be put on the market in rapid succession by many manufacturers, and almost all of new products are designed to be systematized with personal computers and printers for wide and dynamic utilization. With the background of the changing market environment as mentioned above, the GR-DVL9500 series are developed placing great importance on the following points as well as aiming at full use of the characteristics of the digital video camera. (1) In spite of the compact body, the GR-DVL9500 series secures the highest resolution (picture quality) among home video cameras. (2) Excellent handling performance and enriched system for easy operation on every occasion in daily life, particularly, the newly developed progressive 500 camera system that realizes the highest leveled digital video by adoption of the progressive scan CCD (hereinafter abbreviated as PS CCD) that is excellent in color reproducibility, the original super high band camera circuit and highsensitive complementary color filter, all of which furthermore develop the high resolution of the progressive 500 camera system. (3) Thanks to the excellent performance of the PS CCD, high-speed recording by 120 frames per second and high density slow playback that are the first adoption for the home video camera. (4) Besides the above-mentioned features, the automatic flush function that automatically compensates flush illumination for still picture recording in a dark place, DV output terminal, and many other functions convenient for various purposes.

1-1

1.2

OUTLINE OF DOUBLE-SPEED VIDEO RECORDING (SHOOTING)

1.2.1 Double-speed recording in brief High-speed shooting (video recording) exceeding 60 frames per second has been utilized for industrial and scientific purposes such as observation and analysis of high speed phenomena, on-the-spot broadcasting of sports, etc. Video cameras used for the aforementioned purposes are capable of ultra high speed shooting such as from 180 frames per second to one hundred million frames per second. Since such the equipment is very expensive because special pickup device and special recording device are used in it, it hasn't been popularized as video apparatus for general use. The GR-DVL9500 series are a new camcorder with an attractive function added, which enables the user easily to check his swing form at golf, to analyze natural phenomenon such as milk crown when a drop of milk splashes, to observe action of animal, bird, etc. such as flutter of wings, all of them cannot be observed by the naked eye. Regarding the CCD that is the major pickup device of the video camera, that of the GR-DVL9500 series sequentially scans signals of two-dimensionally arranged photodiodes and outputs them as video signal as shown in Fig. 1-2-1. Although a high-speed video camera can be realized by raising the scan frequency, there are many problems to develop a high-speed video camera by such the means, that is to say, signal frequency must be raised with rise of scan frequency, signal processing circuit of the camera needs large-scale improvement to deal with high frequency band as well as high band recording system to record such high frequency signals.
Undesired charge area (111 lines)

Vertical transfer CCD

Photodiode

V1 V2 V3

222lines

Pickup device (CCD)


Undesired charge area (111 lines)

Horizontal transfer CCD1

CH1

Horizontal transfer CCD1

Horizontal transfer CCD2

Fig. 1-2-1 Structure of general CCD

Fig. 1-2-2 Structure of PS CCD

1.2.2 Outline of double-speed video recording and playback of double-speed recorded video Fig. 1-2-3 illustrates the overall configuration of the double-speed video recording and double-speed recorded video playback system. This system is mainly composed of the camera section, special effector section and recording/playback processing section (1) The PS-CCD in which the undesired charge drain is incorporated is adopted as the pickup device of the camera section. In the double-speed recording mode, approximately half of the CCD area is scanned in half a period (1/120 second) of the standard time to output video signal while unnecessary charges are discharged through the undesired charge drain. (2) After that, image data of two fields (sub fields) that are respectively obtained by scanning half the CCD area are combined by the special effector section to be the upper half and lower half of a picture of one field. The field rate of the picture processed by the special effector section is 60 Hz that is the same as the standard recording mode, therefore, the image data is recorded on video tape by the recording/playback section in the same manner as the standard recording.
1-2

(3) In playback, double-speed recorded video can be played back in the slow playback mode or slow zoom playback mode. There is a point to be attended to, that is signals recorded on the DV format. When such the signal is played back in the slow motion mode, the tape runs for 10 tracks and then the tape travel is once suspended from playback by the servo operation, and playback is resumed for the next 10 tracks, because video signals recorded on the DV format are constructed in the form of ten tracks per one frame. Namely, playback of DV formatted video tape is constructed by repetition of 10-tracks playback under the servo control. The GR-DVL9500 sreies realizes the slowmotion playback by means of such the servo control. (For preventing video tape from deterioration, the GR-DVL9500 series limits continuous slow-motion playback time to 120 seconds at maximum.) (4) If double-speed recorded video is played back in the slow-motion mode (1/10 speed of the standard) by this function, motion of image is 1/10 as slow as the real motion. However, the user can enjoy very smooth slow motion in the slow playback mode because each field is renewed every 1/60 second.
1/10-speed slow playback

Camera section
111 Lines
VIDEO 1 VIDEO 2

Special effector section


DSP IC

REC/PB section
PLAY

PS CCD
222 Lines 111 Lines

CDS/AGC ADC

Y/C AUTO

FMC (EIS)

REC

VTR

HD/VD/FRVD

VD/VD2

HD/VD/FRVD
VF_BLK

TG

13.5M/27M

SSG

VF

CCD output signal

Slow playback picture 1

Slow playback picture 2

VF masking processing

Masking VF/Blanking
1/120 sec

Fig. 1-2-3 High-speed recording/playback system

1-3

1.3

PS CCD

The principle of the PS CCD for the GR-DVL9500 are illustrated in Fig. 1-3-1. This PS CCD is characterized by two points of the following. (1) Two horizontal transfer CCD's are incorporated inside. (2) An undesired charge drain is installed under the second horizontal transfer CCD.
V1 V2 V3 V1: Vertical register transfer clock V2: Vertical register transfer clock V3: Vertical register transfer clock H1: Horizontal register transfer clock H2: Horizontal register transfer clock HOB: Drain gate drive clock
CH1 CH2

Vertical transfer CCD

Photodiode

Pickup device (CCD)

Horizontal transfer CCD1 Horizontal transfer CCD2 Undesired charge drain


H1 H2 HOB

Fig. 1-3-1 Illustration of principle of PS CCD (1) In the standard shooting (video recording) mode, high potential is applied to V3 through the vertical blanking period in order to read charges in the vertical transfer CCD out of photodiodes of the pickup device. After that, charges are vertically transferred to the horizontal CCD by two lines every H, namely, charges are read out by a sequential charge readout system. Differently from the conventional four-phase driven vertical two-pixels mixed readout CCD, this CCD does not read pixel charges mixedly between the photodiode and vertical transfer CCD but reads signals of all photodiodes individually at shutter speed of 1/60 second in the standard shooting mode. As well as the GR-DVL9000 video camera, the whole complementary color pixels independent readout system is adopted for processing signals of the CCD in order to realize high resolution color video. 1.3.1 Principle of CCD operation in double-speed shooting In the double-speed shooting mode, two vertically separate signals are input in a period of 1 field. Generally, transfer rate of the horizontal transfer CCD is pointed out as a problem in high-speed shooting. In the GR-DVL9500 series, data read out of the CCD is partially discharged into the undesired charge drain installed under the second horizontal transfer CCD, therefore, high-speed shooting is realized without change of the transfer rate of the horizontal transfer CCD. Pixels to be actually recorded are those of 111 lines of odd fields and 111 lines of even fields, namely pixels of 222 lines are recorded in total. Fig. 1-3-2 illustrates a CCD drive sequence in double-speed shooting, however, the illustration refers to 16 lines only for a convenience of explanation. (1) Charges of photodiodes are transferred to the horizontal transfer CCD by (b) vertical transfer 1 and (c) vertical transfer 2. (2) In the process of (d) vertical transfer 3, 4, horizontal transfer pulse is input and data signal is output in the standard shooting mode, however, in the high-speed shooting mode charges of the lines 1 to 4 are regarded as undesired signals. Therefore, signals of the lines 1 and 2 are discharged out of the undesired charge drain under the horizontal transfer CCD in the process of (d) vertical transfer 3, 4.
1-4

(3) In the standard shooting mode, horizontal transfer pulse is input and data signal is output in the process of (d) vertical transfer 3, 4, however, in the high-speed shooting mode charges of the lines 1 to 4 are regarded as undesired signals. Therefore, signals of the lines 1 and 2 are discharged out of the undesired charge drain under the horizontal transfer CCD in the process of (d) vertical transfer 3, 4. (4) In the same manner, charges of the line 5 and line 6 are transferred in the process of (e) vertical transfer 5, 6. (5) In the process of (f) horizontal transfer 1, charges for 1 H are horizontally transferred and signals for 1H are output from the CCD. (6) As a result of repetition of the above-mentioned operation, charges of readout area are output and undesired charges are disposed through the undesired charge drain.
line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1

Readout area

line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3 line 2 line 1

(a) Charges in CCD

(b) Vertical transfer 1

(c) Vertical transfer 2

line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5 line 4 line 3

line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 6 line 5

line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7

line 6 line 5

line 1 line 2

line 3 line 4

(d) Vertical transfer 3, 4

(e) Vertical transfer 5, 6

(f) Horizontal transfer 1

Fig. 1-3-2 Illustration of principle of PS CCD (2)


1-5

1.3.2 Readout area and recording picture in double-speed shooting In practical operation, charges just a half of the readout area cannot be read out because it takes a certain time to drain undesired charge as mentioned in the preceding paragraphs (1) to (3). For the GR-DVL9500 sereies charges of total 222 lines are specified to be valid, namely, 111 lines are valid for the first half of the readout area and another 111 lines are valid for the second half of the readout area. Time needed to drain undesired charge is for 15 lines (H) respectively.

1.4

VIDEO SIGNAL OF DOUBLE-SPEED SHOOTING (RECORDING)

1.4.1 Video signal of double-speed shooting (1) In the double-speed shooting mode, a picture that is actually recorded comprises of a couple of vertically halved pictures as shown in Fig. 1-3-3. Therefore, if video recorded by the GR-DVL9500 series are played back by another DVC or it is output in the EE mode, every picture (frame) is sandwiched by two frames that are 1/60 seconds ahead of and behind the playback picture respectively. In the slow-motion playback (at 1/10 speed of the standard), the upper-half picture and lower-half picture are alternately played back for five fields respectively in the center part of the VF screen.

Picture output on the VF screen is blanked by the lower half. (A) Recorded picture (B) Picture appearing on the VF screen In the slow-motion (1/10 speed) playback, the upper-half picture and lower-half picture are alternately played back for 5 fields respectively in the center of the VF screen. (C) Picture played back by DVC other than GR-DVL9500 series (D) Picture played back by GR-DVL9500 series

Fig. 1-4-1 Video signal of double-speed shooting (1) 1.4.2 Video signal of double-speed shooting (2) Fig. 1-4-2 shows video signals in one vertical synchronizing period in both the standard playback and double-speed playback modes. In the double-speed shooting (recording), undesired charges are discharged to the undesired charge drain through the vertical transfer CCD at a high speed.

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VD (1) Standard shooting (recording) Standard shooting Doublespeed shooting

(a)

(b)

(c) (a)

(b)

(c)

(2) Doublespeed shooting (recording)

1/20

Fig. 1-4-2 Video signal of double-speed shooting (2) 1.4.3 Video signal in slow playback When video recorded in the double-speed shooting mode is played back in the slow-motion playback mode, pictures (fields) are sorted, edited and controlled for the vertical positioning by the DSP and FMC IC, because each playback picture is composed of two different pictures of the upper-half and lower-half. As shown in Fig. 1-4-3, video signals recorded in the upper half (A) of the first field period are output on the monitor screen for 1/60 second by 5 times (5/60 second), and then signals of the lower-half (B) are output on the screen for 10/60 second. In other words, video (a frame) recorded for 1/60 second is played back for 1/6 second in the slow playback mode.
Field No. 1 5 6 10

(A) VTR (1/10 S low) (B)

Fields are sorted by the FMC circuit of the camera section.

Picture on monitor screen

A 1/60

A 1/60

B 1/60

B 1/60

Fig. 1-4-3 Video signal in 1/10 speed slow playback


1-7

SECTION 2 CIRCUIT DESCRIPTION


2.1 DESCRIPTION OF PS CCD OPERATIONS
Every pixel independent readout system of the PS CCD realizes recording of high vertical resolution still picture without use of mechanical shutter.
1pin

Transfer system Optical size Effective pixels Total Horizontal register clock Chip size Unit cell size Optical black Dummy bits Color filter

Interline transfer CCD 1/3 inch size format NTSC 724(H) 494(V) approx.360k pixels *PAL 724(H) 582(V) approx.420k pixels NTSC 758(H) 504(V) approx.380k pixels *PAL 758(H) 592(V) approx.450k pixels 13.5MHz (DVC reference clock) 6.40mm (H) 5.05mm (V) NTSC 6.75m m (H) 7.40m m (V) *PAL 6.85m m (H) 6.25m m (V) Horizontal Front 6 / Back 28 Vertical Front 8 / Back 2 Horizontal 16 Vertical 5 W,G,Cy,Ye complementary filter

8 6 12pin H 28

Fig. 2-1-1 Optical black assignment 2.1.1 CCD pin assignment and block diagram

Cgg2

Cgg1

VHOLD

VOUT2

VOUT1

GND

11

10

Cy Wh Vertical-CCD Ye Gr Cy Wh

Ye Gr Cy Wh Ye Gr

Ye Gr Cy Wh Ye Gr

1st Horizontal-CCD 2nd Horizontal-CCD

Pilot Signal Generator

HIG1
1

HIS

V1

V2

V3

12

13

14

15

16

17

18

19

20

21

22

* Photo Sensor

SUB

H1

Vdd

RG

H2

VL

HHG1

HHG2

Fig. 2-1-2 CCD pin assignment and block diagram


2-1

POG

VOG

HOB

2.1.2 CCD pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name HIG1 HIS V3 V2 V1 VHOLD GND CGG1 VOUT1 CGG2 VOUT2 VDD RG VL SUB H1 H2 HHG1 HHG2 HOB POG VOG In/Out In In In In In In Out Out In In In In In In In In In In Pilot signal infusion clock Pilot signal source bias Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register final step hold clock GND Output amplifier 1 gate decouple capacitor Signal output 1 Output amplifier 2 gate decouple capacitor Signal output 2 Power supply Reset gate clock Protect transistor bias Substrate (over flow drain) Horizontal register transfer clock Horizontal register transfer clock H. register to H. register transfer clock H. register to H. register transfer clock not used Pilot signal output transfer clock Vertical register final step transfer clock REF.

Table 2-1-1 pin functions

2-2

2.1.3 3-Phase Drive Vertical CCD The vertical CCD performs reading and transmission independently without mixing all pixels in 1 field. First, the accumulated charge is read to the vertical CCD V3 and V2 by the read pulse SG (SG is superimposed with V2). Then, vertical transmission is performed twice in the 1 horizontal blanking period using the 3phase drive pulses V1, V2, and V3.
V-CCD V1 V3 V2 V1 V3 V2 V1 V3 SENSOR V1 V3 V2 V1 V3 V2 V1 V3 V2

SIGNAL CHARGE

Fig. 2-1-3 3-Phase drive vertical CCD 2.1.4 Transmission to Horizontal CCD from Vertical CCD It is necessary to prevent the signal charge of the next 1 line from being transmitted to the horizontal CCD until the transmission of the signal charge of the first line between the horizontal CCDs is completed. VHOLD is used as the buffer and VOG is used for reading from the buffer.
1st HCCD-1

V3 V1 V3 V2 VHOLD VOG H1/H2 HHG1 SENSOR

V2

VHOLD VOG

H1 H2

HHG1

SIGNAL CHARGE

Fig. 2-1-4 Transmission to horizontal CCD from vertical CCD


2-3

2.1.5 Transmission between Horizontal CCDs The first line signal charge is transmitted to the second horizontal CCD by transmission between horizontal CCDs. A gate (HHG2) for transmission between horizontal CCDs is provided for this purpose. To ensure both transmission efficiency between the horizontal CCDs and charge handled by the first horizontal CCD, the first horizontal CCD is divided into two. Transmission gates (HHG1) are also assigned between these two CCDs. The divided signal is mixed again in the final stage of the first horizontal CCD. The signal charge of the first line is transmitted to the channel below the HHG1 from the vertical CCD and moved to the channel below the next HHG2. When HHG2 becomes low bias, the signal charge is transmitted to the second horizontal CCD. After the signal charge of one line has been transmitted, the transmission of the signal charge of the second line starts. The signal charge of the second line is first transmitted to the channel below HHG1, split into two there, and transmitted to the first horizontal CCD-1 and first horizontal CCD-2.

V-CCD

1st HCCD-1 VOUT1 Compound Channel 1st HCCD-2 VOUT2 2nd HCCD

Fig. 2-1-5 Transmission between horizontal CCDs


1st HCCD-1 1st HCCD-2 2nd HCCD VOG H1 H2 H1 H2 H1 H2 H2 H1 H1 1st HCCD-1

HHG1

HHG2

HHG1

H1

H2

H2

1st HCCD-2

HHG2

H2

H1

H1

2nd HCCD

H1 H2

Fig. 2-1-6 Transmission of the first line signal charge


2-4

1st HCCD-1 1st HCCD-2

2nd HCCD
H2 H1

VOG 1st HCCD-1

H1 H2

HHG1

H1 H2

HHG2

H1 H2

HHG1

H1

H2

H2

1st HCCD-2

HHG2

H2

H1

2nd HCCD

H1 H2 Channel Stop

Fig. 2-1-7 Transmission of the second line signal charge 2.1.6 2-channel Output Horizontal CCD Outputs signals of two vertical lines simultaneously with the 2-stage horizontal register. As a result, signals are output from two output terminals (Vout 1, Vout 2) for the odd and even fields simultaneously in the 1/60 (*1/50) second period. Interlacing is performed by the frame memory control (FMC) performed later. 2.1.7 Pilot Signal Generator A reference signal called the pilot signal is output to channel A or channel B of the output of this CCD in the 1H period before the horizontal front OB. Then 2-channel pilot signal levels are compared at the stage before the Y/C circuit to correct the inconsistency caused by the difference of the paths between the channels. The pilot signal and output timing are generated by the pilot signal source bias HIS, pilot signal injection clock HIG1, and pilot signal output stage transmission clock POG.

2-5

2.1.8 Drive Timing (NTSC) 1) Drive Timing Chart (Vertical Sync)


FLD

VD

BLK

520

525 1 2 3 4 5

260

265

270

275

280

SG

V1 V2

V3 CCD OUT1 * CCD OUT2 494 2 4 6 8 2 4 494 2 4 6 8 2 4

493

1 3 5 7 1 3

493

1 3 5 7 1 3

*2CH 1/60sec Non-Intelace Transfer

Fig. 2-1-8 Drive timing chart (Vertical Sync) 2) Drive Timing Chart (Horizontal Sync)
HD/SYNC
1 86

BLK
858 1 112 128

CLK
1 21 1 1 7 1 1 21 21 1 14 1 1 18 1 1 8 1 1 1 1 28 1 5 1 1 16 41 22 1 21 1 7 1 7 36 30 21 1 1 21 21 1 13 1 1 21 8 14 1 1 21 21 1 1 21 21 1 7 14 1 1 1 21 14

V1 V2 V3 VHOLD VOG H1 H2
1 1

1 1 25

32

HHG1

HHG2

14

28

Fig. 2-1-9 Drive timing chart (Horizontal Sync)


2-6

134

28

145

285

10

15

20

2.2

CDS AGC (IC5101/IC5102)

This IC is CCD head amplifier for digital camera. It features CDS (correlation double sampling), AGC, Sampling/Hold for A/D input, Blanking, Reference voltage for A/D and Output driver for A/D converter. 2.2.1 CDS AGC (IC5101/IC5102) pin assignment and block diagram CCDLEVEL AGCCONT
14
VRT BLK SW POWER SAVE CONT VRB DRV VRB

ICONT

GND1

24

23

22

21

20

19

18

17

16
BUF

VCC1

SHD

SHP

DIN

15

13

SH1

SH2 AGC SH3

DC SHIFT

OB SW AGC CLP

CDS CLP2 DMSW2

VREF DMSW1 CDS CLP1

CAM SH OFFSET

VRT DRV

DRV

10

11

12

VCC3

PBLK

PS

DRVOUT

Fig. 2-2-1 CDS AGC (IC5101/IC5102) pin assignment and block diagram

2-7

OFFSET

CLPOB

GND2

GND3

VRB

XRS

VRT

NC

AGCCLP

CLPDM

VCC2

PIN

2.2.2 CDS AGC (IC5101/IC5102) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name GND2 PS GND3 DRVOUT VCC3 NC VRB VRT OFFSET PBLK XRS CLPOB AGCCLP AGCCONT CCDLEVEL VCC1 SHP SHD GND1 CLPDM PIN DIN VCC2 ICONT In/Out In Out Out Out In In In In Out In In In In In In GND Power save mode (H: normal operation /L: power save) GND Driver output for A/D converter Power supply not used Bottom side reference voltage output for A/D (1.35V) Top side reference voltage output for A/D (2.35V) Offset adjustment input Pre-branking pulse input Sample hold pulse for A/D input timing Optical black clamp pulse input AGC clamp AGC gain control input not used Power supply CDS pre-charge level sample hold pulse CDS signal level sample hold pulse GND CCD dummy pixel portion clamp pulse CCD signal input CCD signal input Power supply A/D Driver current control REF.

Table 2-2-1 CDS AGC (IC5101/IC5102) pin functions

2-8

2.3

T. G (IC5002)

This IC generates pulses to drive the PS CCD and timing pulses necessary for video signal process circuits. The main clock (27MHz) made by crystal X5001 and the 1/2 divided clock (13.5MHz) are sent to the SSG in DSP IC4301. The SSG makes HD, VD and FLD then send back to the TG. The pulses for the CCD are generated based on HD, VD, FLD and 13.5MHz. The shutter speed control information is supplied from the CAMERA CPU IC 4401 through the serial bus. Also the sampling and clamp pulses for CDS/AGC IC5101/IC5102, and the A/D converter clock (13.5MHz) for ACD IC4201/IC4202 are generated at here. 2.3.1 TG (IC5002) pin assignment
MODE2 TEST4 50 MODE STBY CLD2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

Vdd1 OSCI OSCO PS ED0 ED1 ED2 SMD1 SMD2 XSG XV2 XSUB Vss H1 H2 NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

WEN

Vdd1

CKO

CLD

FLD

HDI

Vss

Vss

CKI

VDI

CL

ID PBLK XCPOB XCPDM RM Vdd1 Vss PSH2 PSH1 TEST3 XRST TEST1 NP XRS XSHD XSHP

Vdd1

Vss

VDD2

XV1

XVHOLD

XV3

Vss

RG

XHHG2A

XHHG2B

XHHG1B

Fig. 2-3-1 TG (IC5002) pin assignment

2-9

XHHG1A

XPOG

XHIG1

XVOG

XHOB

2.3.2 T. G (IC5002) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name Vdd1 OSCI OSCO PS ED0 ED1 ED2 SMD1 SMD2 XSG XV2 XSUB Vss H1 H2 NC Vdd2 RG Vss XHIG1 XPOG XVHOLD XV1 XV3 XVOG Vdd1 Vss XHOB XHHG2A XHHG2B XHHG1B XHHG1A In/Out In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out H. register to H. register transfer pulse Not used Not used Serial/Parallel mode select (L:serial /H:parallel) L:fix Electrical shutter select (PS=L: chip enable, PS=H: parallel) Electrical shutter select (PS=L: serial transfer clock, PS=H: parrallel) Electrical shutter select (PS=L: setting data, PS=H: parrallel) Electrical shutter select (PS=L: no effect, PS=H: parrallel) Electrical shutter select (PS=L: no effect, PS=H: parrallel) CCD signal charge read out pulse CCD vertical register transfer pulse CCD signal charge sweep out pulse GND(VDD1,VDD2 common) CCD horizontal register transfer pulse CCD horizontal register transfer pulse Not used Power supply for H1,H2,RG (4.5V~5.5V) Reset gate pulse GND(VDD1,VDD2 common) Pilot signal infusion pulse Pilot signal transfer (to horizontal register) pulse Transfer to H.register timing adjust pulse CCD vertical register transfer pulse CCD vertical register transfer pulse Transfer pulse from V.register to H.register Power supply for internal logic (2.7V~3.6V) GND (VDD1,VDD2 common) Drain gate drive pulse REF. Power supply for internal logic (2.7V~3.6V)

Table 2-3-1 T. G (IC5002) pin functions-1/2

2-10

T. G (IC5002) pin functions-2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name XSHP XSHD XRS NP TEST1 XRST TEST3 PSH1 PSH2 Vss Vdd1 RM XCPDM XCPOB PBLK ID WEN TEST4 Vss CL CLD FLD Vss Vdd1 MODE2 HDI VDI STBY CLD2 MODE CKO CKI In/Out Out Out Out In In In Out Out Out Out Out In In In In In Out In Out In CDS Pre-charge sample hold pulse CDS Data sample hold pulse CDS reset gate pulse NTSC/PAL select (L:NTSC,H:PAL) Not used Master reset (power on reset) Not used Not used Not used GND (VDD1,VDD2 common) Power supply for internal logic (2.7V~3.6V) Mode select (L:Interlace /H:Non-interlace) Dummy bit clamp pulse Optical black clamp pulse Pre-branking cleaning pulse Not used Not used Not used GND (VDD1,VDD2 common) A/D converter clock 13.5MHz A/D converter clock 13.5MHz Field pulse GND (VDD1,VDD2 common) Power supply for internal logic (2.7V~3.6V) XPOG timing select HD input VD input Stand by enable FCK13.5MHz CCD output mode select (L:2ch-output/H:1ch-output) 2FCK27MHz output 2FCK27MHz input REF.

Table 2-3-1 T. G (IC5002) pin functions-2/2

2-11

2.4

V. DRIVER (IC4101)

The V.DRIVER is supplied with Vertical register transmission pulses (V1,V2,V3,VHOLD,VOG), Signal charge gate pulse (SG), Horizontal register transmission pulses (HHG1,HHG2) and Pilot signal control pulses (HIG,POG) from the TG IC5002. These pulses are converted to 2-state or 3-state levels in such a way as to drive the CCD. The signal charge gate pulse (SG) is overlapped onto the vertical register transmission pulses (V2). Also this IC has the amplifier for substrate voltage. 2.4.1 V. DRIVER (IC4101) pin assignment
SUBDC VSUB XSG XV2 TI1 HIG1 POG TI2 XSUB XVHOLD VM VHH VM VL VO2 HIGO POGO SUB VHH VM VL VHOLDO 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

VDD XV1 XV3 XVOG STBY XHOB XHHG2-1 XHHG2-2 XHHG1-2 XHHG1-1 VL

Fig. 2-4-1 V. DRIVER (IC4101) pin assignment

VO1 VO3 VOGO VL VM VH HOBO HHGO2 HHGO1 VH VM


2-12

12 13 14 15 16 17 18 19 20 21 22

2.4.2 V. DRIVER (IC4101) block diagram

VSUB XSG XV2 HIG1 TI1 POG TI2 XSUB

43

X3.2

44

SUBDC

42 41 39 40 38 37 36

V02

HIGO

POGO

SUB

XVHOLD

35

11

VHOLD0

XV1

32

12

V01

XV3

31

13

V03

XVOG

30

14

VOG0

XHOB STBY XHHG2-2 XHHG2-1 XHHG1-2 XHHG1-1

28 29 26 27 25 24
1/2VDD

18

HOB0

19

HHG02

20 23 15 10 3 17 21 1 8 2 9 16 22 34

HHG01 VL VL VL VL

VDD

33

VM

VM

VM

VM

VHH

Fig. 2-4-2 V. DRIVER (IC4101) block diagram


2-13

VHH

VM

VH

VH

2.4.3 V. DRIVER (IC4101) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VHH VM VL VO2 HIGO POGO SUB VHH VM VL VHOLDO VO1 VO3 VOGO VL VM VH HOBO HHGO1 HHGO2 VH VM VL XHHG1-1 XHHG1-2 XHHG2-2 XHHG2-1 XHOB STBY XVOG XV3 XV1 VDD VM XVHOLD XSUB TI2 POG HIG1 TI1 XV2 XSG VSUB SUBDC Pin Name In/Out Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In In In In In In In In Out Power supply (+15V) Power supply (0V) Power supply (-6.5V) High voltage output (3 state) High voltage output (3 state) High voltage output (3 state) High voltage output (2 state) Power supply (+15V) Power supply (0V) Power supply (-6.5V) High voltage output (2 state) High voltage output (2 state) High voltage output (2 state) High voltage output (2 state) Power supply (-6.5V) Power supply (0V) Power supply (+5V) High voltage output (3 state) High voltage output (3 state) High voltage output (3 state) Power supply (+5V) Power supply (0V) Power supply (-6.5V) Output control (HHGf 1) Output control (HHGf 1) Output control (HHGf 2) Output control (HHGf 2) Output control (HOBf ) Output control (HOBf ) Output control (VOGf ) Output control (Vf 3) Output control (Vf 1) Power supply (+5V) Power supply (0V) Output control (VHOLDf ) Output control (SUB) Output control (POGf ) Output control (POGf ) Output control (HIGf ) Output control (HIGf ) Output control (Vf 2) Output control (Vf 2) Substrate voltage amplifier input Substrate voltage amplifier output REF.

Table 2-4-1 V. DRIVER (IC4101) pin functions


2-14

2.5

ADC (IC4201/IC4202)

This IC is a 10-bit, 20-MSPS A-D (analog-to-digital) converter. 2.5.1 ADC (IC4201/IC4202) pin assignment
NC NC NC DRVDD AVSS NC AVDD NC NC AIN VREF NC D0 D1 D2 D3 D4 NC NC D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37

36 35 34 33 32 31 30 29 28 27 26 25

NC REFBS REFBF NC MODE NC REFTF REFTS CLAMP_IN CLAMP REFSENSE NC

NC NC OTR DRVSS
45 DRVDD

Fig. 2-5-1 ADC (IC4201/IC4202) pin assignment 2.5.2 ADC (IC4201/IC4202) block diagram
28 CLAMPIN 27 CLAMP 42 AVDD

22 CLK

NC NC NC NC CLK 3_STATE STBY

NC

13 14 15 16 17 18 19 20 21 22 23 24

24 STBY 32 MODE SHA AIN 39 REFTS 29 REFBS 35 REFTF 30 REFBF 34 VREF 38 REFSENS 26 AVSS 44
A/D D/A A/D D/A A/D D/A A/D D/A

SHA

GAIN

SHA

GAIN

SHA

GAIN

SHA

GAIN
A/D

23 3-STATE

CORRECTION LOGIC

OUTPUT BUFFER

1V
DRVSS 45

16 12 8 5 1

OTR D9 D5 D4 D0

Fig. 2-5-2 ADC (IC4201/IC4202) block diagram


2-15

2.5.3 ADC (IC4201/IC4202) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name D0 D1 D2 D3 D4 NC NC D5 D6 D7 D8 D9 NC NC NC OTR DRVSS NC NC NC NC CLK 3-STATE STBY NC REFSENSE CLAMP CLAMP_IN REFTS REFTF NC MODE NC REFBF REFBS NC NC VREF AIN NC NC AVDD NC AVSS DRVDD NC NC NC In/Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In In REF. LSB Digital output

Not used Not used

Digital output MSB Not used Not used DRVss digital GND

Not used

Clock input 13.5MHz L: normal operation Stand by H:power down mode/L:normal operation Not used REFSENSE reference select H:fix CLAMP L:no clamp fix CLAMPIN clamp reference input :not used Top reference voltage 2.35V Top reference decoupling 2.35V Not used MODE not used Not used Bottom reference decoupling 1.35V Bottom reference voltage 1.35V Not used Not used Analog input Not used Avdd analog supply Not used Analog GND DRVdd digital driver supply Not used

Table 2-5-1 ADC (IC4201/IC4202) pin functions


2-16

2.6

DSP (IC4301)

This just one package IC performs digital signal processing for PS-CCD system. Its mainly performances of each blocks are followings. 1) PRE-BLOCK Pre-block locates the front of DSP system, and the 2-channel 10 bits AD-converted input data are processed 2ch-tracking and OB clamping as necessary for the Y/C-block. The 2ch-tracking compare the 2-channel tracking pulses (pilot signals) added on the CCD output signal, and output the difference information of between channels to the (-com (Camera CPU). The (-com calculates a revised value for the B-channel signal level, and sends back here. After corrected the difference of between channels, the OB level of the horizontal rear part is calculated. This OB data is used for clamp the next field signal. Also this data is sent to the (-com for reference of high luminance adjustment. 2) Y/C COLOR PROCESS The color processes are color separation, color false suppression, white balance, chroma matrix, CNR and reverse of negative/positive, and finally converts to the DVC format then outputs to the next FMC. The output form of A and B channels are dot-sequential data as B?Y upper 4-bits, B?Y lower 4-bits, R?Y upper 4-bits, R?Y lower 4-bits. 3) Y/C LUMINANCE PROCESS The luminance processes are luminance generation, moire collection, (?/ knee collection, gain/setup and reverse of negative/positive, and finally outputs to the next FMC as an 8-bits data each A and B channels. 4) FMC The camera video signal 12-bits (luminance 8-bits / color 4-bits) ( 2-channels from Y/C or the playback video signal 12-bits (luminance 8-bits / color 4-bits) from the DVC-VTR are supplied, and performed digital effect with control reading and writing to/from the frame memory. In case recording mode, the camera signal that is 2-channels frame data is converted to 1-channel field data at the line number conversion then output to the DVC deck section. 5) SSG This part performs sync signal generation for the video camera. The horizontal sync (HD), vertical sync (VD), complex sync and horizontal/vertical reference signal for the DVC deck section (INH/INV) are generated by dividing the reference clock (27MHz, 13.5MHz), which are supplied from the TG IC5002. When VTR is playback mode, the SSG synchronizes with horizontal sync (PBHS) and vertical sync (PBVS) those are supplied from DVC deck section, then outputs the reference signals to the deck and FMC part. 6) AUTO This part calculates for the auto focus and iris control, then send this data to the camera CPU through the BUS I/F part. Also the iris drive pulse is generated here and output from 151 pin of the DSP IC as the IRIS PWM. 7) BUS I/F The BUS I/F is interface between the each block in the DSP and the camera CPU. The transmission and receive to/from the camera CPU through the MPX 16-bits bus. In case of DV still image transfer to the PC using the JLIP terminal, the DV image data that captured with the frame memory is read out by the FMC. Then it is sent to the camera CPU through the BUS I/F. At the camera CPU the data is converted for the RS-232C (TX) then output to the JLIP terminal. 8) SHUTTER SOUND The shutter sound for the snapshot mode is generated here. This sound outputs from the 129-pin as analog signal.

2-17

2.6.1 DSP (IC4301) pin assignment and block diagram


DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 I/F3V GND DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 I/F3V GND DOUT16 DOUT17 DOUT18 DOUT19 DOUT20 DOUT21 DOUT22 DOUT23 GND I/F3V DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 GND 2V GND I/F3V DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 GND DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 NC NC I/F3V GND AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 I/F3V GND 2V GND BIN9 BIN8 BIN7 BIN6 BIN5 BIN4 BIN3 BIN2 BIN1 BIN0 GND HD VD FLD FRVD CLK27IN CLK135IN NC I/F3V I/F3V GND GND ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 NC NC ALE NWE NRE 26 3 2 47 32 80 18 48 49 64 33 81 19 121 105 89 73 65 20 50 34 66 35 82 21 51 67 57 22 36 52 53 23 37 40 169 185 137 153 24 39 38 54 55 68 69 70 71 98 83 84 87 86 85 99 56 72 103 102 101 17 63 31 46 30 62 16 45 4 5 29 15 44 28 14 27 1 13 6 7 43 42 78 61 59 79 58 60 11 12 74 77 75 93 91 92 90 94 9 8 104 88 106 109 107 126 108 124 122 125 10 142 123 140 138 139 141 156 154 235

FMC PRE BLOCK


2CH TRACKING OB CLAMP

Y/C

ZOOM VECTOR/EIS LINE CHANGE PINUP/ACTION WIPE/CINE

SSG

BUS I/F

SHUTTER SOUND

AUTO
IRIS/FOCUS

120 136 157 143 170 171 172 158 173 186 187 201 202 217 203 188 218 204 174 219 189 205 159 190 206 220 160 175 191 207 221 176 208 162 222 233 234 163 192 178 193 209 223 179 177 194 161 210 224 195 147 211 225 152 168 239 238 182 230 232

I/F3V GND FMIE FMWR FMWAE FMRAE FMWAD FMRAD FMLWE FMUWE FMRE WCLK RCLK CLK18 SSPP VD2 TOUT NC NC NC BD3 BD2 BD1 BD0 FRP INH INV TEST PBHS PBVS CSYNC CLK270 CLK1350 VTR45 VTR135 GND I/F2V FCVO_0 FCVO_1 FCVO_2 FCVO_3 FCVO_4 FCVO_5 FCVO_6 FCVO_7 FCVO_8 FCVO_9 FCVO_10 FCVO_11 FCVO_12 FCVO_13 FCVO_14 FCVO_15 2V GND QCTEST MINTEST CLKSEL NC VF_BLK

RESET DFLT TVMD TNW STBY FSET OMT KASRST AFBEND BEND PWM I/F3V GND 2V GND IOCNT NC NC SCANTEST TDO TRST TCK TMS TDI I/F3V GND NC NC DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND Analog_out COMP IREF VREF DAC_3V

Fig. 2-6-1 DSP (IC4301) pin assignment and block diagram

2-18

PBIN11 PBIN10 PBIN9 PBIN8 PBIN7 PBIN6 PBIN5 PBIN4 PBIN3 PBIN2 PBIN1 PBIN0

100 115 119 118 117 116 134 132 135 133 151 41 25 237 236 150 76 95 149 148 167 166 165 164 184 200 110 131 96 97 111 114 127 130 144 145 129 128 112 113 215 146 155 231 183 199 216 229 228 214 240 213 227 197 198 181 226 212 196 180

2.6.2 DSP (IC4301) pin functions-1/5


Pin No. 26 3 2 47 32 80 18 48 49 64 33 81 19 121 105 89 73 65 20 50 34 66 35 82 21 51 67 57 22 36 52 53 23 37 40 169 185 137 153 24 39 38 54 55 68 69 70 71 Pin Name NC I/F3V GND AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 I/F3V GND 2V GND BIN9 BIN8 BIN7 BIN6 BIN5 BIN4 BIN3 BIN2 BIN1 BIN0 GND HD VD FLD FRVD CLK27IN CLK135IN NC I/F3V I/F3V GND GND ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 ADR7 In/Out In In In In In In In In In In In In In In In In In In In In Out Out Out In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out REF. Not used 3V supply GND (MSB)

Ach signal input from A/D IC4202

(LSB) 3V supply GND 2V supply GND (MSB)

Bch signal input from A/D IC4201

(LSB) GND HD output VD output Field distinction output Test terminal Clock input 27MHz Clock input 13.5MHz Not used 3V supply 3V supply GND GND (MSB)

CPU data/address MPX BUS 16bit from SYSCON CPU IC1001

Table 2-6-1 DSP (IC4301) pin functions-1/5


2-19

DSP (IC4301) pin functions-2/5


Pin No. 98 83 84 87 86 85 99 56 72 103 102 101 100 115 119 118 117 116 134 132 135 133 151 41 25 237 236 150 76 95 149 148 167 166 165 164 184 200 110 131 96 97 111 114 127 130 144 145 Pin Name ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 NC NC ALE NWE NRE RESET DFLT TVMD TNW STBY FSET OMT KASRST AFBEND BEND PWM I/F3V GND 2V GND IOCNT NC NC SCANTEST TDO TRST TCK TMS TDI I/F3V GND NC NC DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND DAC_GND In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In In In In In In In Out In REF.

CPU data/address MPX BUS 16bit from SYSCON IC1001

(LSB) Not used Not used Address latch enable input Write enable input Read enable input Reset input DSP_RST_2 Not used Not used Test terminal SSG stand by Reset input DSP_RST_3 EIS data read out timing Not used (H: fix) AF data read out timing WB data read out timing IRIS control PWM output 3V supply GND 2V supply GND Not used (H: fix) Not used Not used for Boundaly scan test for Boundaly scan test Reset input DSP_RST_1 for Boundaly scan test for Boundaly scan test for Boundaly scan test 3V supply GND Not used

GND

Table 2-6-1 DSP (IC4301) pin functions-2/5


2-20

DSP (IC4301) pin functions-3/5


Pin No. 129 128 112 113 215 146 155 231 183 192 216 229 228 214 240 213 227 197 198 181 226 212 196 180 232 230 182 238 239 168 152 225 211 147 195 224 210 161 194 177 179 223 209 193 178 192 163 234 Pin Name Analog_out COMP IREF VREF DAC_3V NC NC NC NC NC NC NC PBIN11 PBIN10 PBIN9 PBIN8 PBIN7 PBIN6 PBIN5 PBIN4 PBIN3 PBIN2 PBIN1 PBIN0 VF_BLK NC CLKSEL MINTEST QCTEST GND 2V FCVO_15 FCVO_14 FCVO_13 FCVO_12 FCVO_11 FCVO_10 FCVO_9 FCVO_8 FCVO_7 FCVO_6 FCVO_5 FCVO_4 FCVO_3 FCVO_2 FCVO_1 FCVO_0 I/F2V In/Out Out In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out REF. Shutter sound output Reference current Reference voltage DAC 3V supply

Not used

PBY7 PBY6 PBY5 PBY4 PBY3 PB luminance signal input from deck section from DVIO IC3202 PBY2 PBY1 PBY0 PBC3 PBC2 PBC1 PB chroma signal input from deck section from DVIO IC3202 PBC0 VTR section memory reference signal output Not used Not used (L: fix) Not used (L: fix) Not used (L: fix) GND 2V supply YSI7 YSI6 YSI5 YSI4 YSI3 luminance signal output to deck section to DVIO IC3202 YSI2 YSI1 YSI0 CSI7 CSI6 CSI5 CSI4 CSI3 chroma signal output to deck section to DVIO IC3202 CSI2 CSI1 CSI0 2V supply

Table 2-6-1 DSP (IC4301) pin functions-3/5


2-21

DSP (IC4301) pin functions-4/5


Pin No. 233 222 162 208 176 221 207 191 175 160 220 206 190 159 205 189 219 174 204 218 188 203 217 202 201 187 186 173 158 172 171 170 143 157 136 120 235 154 156 141 139 138 140 123 142 10 125 122 Pin Name GND VTR135 VTR45 CLK1350 CLK270 CSYNC PBVS PBHS TEST INV INH FRP BD0 BD1 BD2 BD3 NC NC NC TOUT VD2 SSPP CLK18 RCLK WCLK FMRE FMUWE FMLWE FMRAD FMWAD FMRAE FMWAE FMWR FMIE GND I/F3V NC DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 GND DIN15 DIN14 In/Out Out Out Out In In Out Out In Out In In Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In REF. GND Not used Reference clock 4.5MHz (CLK4M5) for FOCUS & ZOOM driver IC4851 Reference clock output 13.5MHz Reference clock 27MHz (VTR27M) for DVIO IC3202 Not used VTR PB vertical reference signal input VTR PB horizontal reference signal input Test terminal VTR section vertical reference signal output VTR section horizontal reference signal output Frame reference pulse input

Data signal in/out of DVC bus (for Static image data) from/to CAS IC3001

Not used Test terminal Not used Sector start signal input of DVC bus from CAS IC3001 Reference clock output 18MHz from DVIO IC3202 Read clock Write clock Read enable Upper write enable Lower write enable Read address Write address Read address enable Write address enable Write address reset mode enable Input enable GND 3V supply Not used FMY7A FMY6A FMY5A FMY4A FMY3A Ach luminance signal input from frame mamory from IC4302 FMY2A FMY1A FMY0A GND FMY7B Bch luminance signal input from frame mamory from IC4302 FMY6B

Table 2-6-1 DSP (IC4301) pin functions-4/5


2-22

DSP (IC4301) pin functions-5/5


Pin No. 124 108 126 107 109 106 88 104 8 9 94 90 92 91 93 75 77 74 12 11 60 58 79 59 61 78 42 43 7 6 13 1 27 14 28 44 15 29 5 4 45 16 62 30 46 31 63 17 Pin Name DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 I/F3V GND 2V GND DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 I/F3V GND DOUT23 DOUT22 DOUT21 DOUT20 DOUT19 DOUT18 DOUT17 DOUT16 GND I/F3V DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 GND I/F3V DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 In/Out In In In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out REF. FMY5B FMY4B FMY3B Bch luminance signal input from frame mamory from IC4302 FMY2B FMY1B FMY0B 3V supply GND 2V supply GND FMC3A FMC2A FMC1A Ach chroma signal input from frame mamory from IC4302 FMC0A FMC3B FMC2B FMC1B Bch chroma signal input from frame mamory from IC4302 FMC0B 3V supply GND TMY7A TMY6A TMY5A TMY4A TMY3A Ach luminance signal output to FM IC4302 TMY2A TMY1A TMY0A GND 3V supply TMC3A TMC2A TMC1A Ach chroma signal output to FM IC4302 TMC0A TMY7B TMY6B Bch luminance signal output to FM IC4302 TMY5B TMY4B GND 3V supply TMY3B TMY2B Bch luminance signal output to FM IC4302 TMY1B TMY0B TMC3B TMC2B TMC1B Bch chroma signal output to FM IC4302 TMC0B

Table 2-6-1 DSP (IC4301) pin functions-5/5


2-23

2.7

FM (IC4302)

This IC is a field memory having a storage capacity of 222,720 words 24 bits. 2.7.1 FM (IC4302) pin assignment

RADE/RX RCLK NRE DO0 DO1 DO2 DO3 DO4 DO5 Vss DO6 DO7 DO8 DO9 DO10 DO11 Vcc Vcc DO12 DO13 DO14 DO15 DO16 DO17 Vss DO18 DO19 DO20 DO21 DO22 DO23 WXINC WR/TR WADE/RX WXAD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36

RXAD RR RXINC Vss D/F DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 WAIT Vss DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 WCLK NLWE NUWE IE

Fig. 2-7-1 FM (IC4302) pin assignment


2-24

2.7.2 FM (IC4302) block diagram

D/F 66 READ REGISTER 3 NRE 19 - 24 DO12 - 17 26 - 31 DO18 - 23 12 D OUT BUFFER U-BANK (760 X 290 X 12) X-DECODER MEMORY CELL ARRAY FIFO MODE CONTROL 37 NUWE 36 IE 12 WRITE BUFFER 40 - 51 DIN23 - 12 READ REGISTER 4 - 9 DQ0 - 5 (DO0 - 5) 11 - 16 DQ6 - 11 (DO6 - 11) 12 12 READ REGISTER

MODE CONTROL

WCLK 39 WR/TR 33 WADE/RX 34 WXAD 35 WXINC 32 RCLK 2 RR 69 RADE/RX 1 RXAD 70 RXINC 68

BLOCK MODE CONTROL

4-9 DQ0 - 5 (DO0 - 5) 11 - 16 DQ6 - 11 (DO6 - 11)

Fig. 2-7-2 FM (IC4302) block diagram

2-25
X-DECODER WRITE BUFFER MEMORY CELL ARRAY REFRESH CONTROL U-BANK (760 X 290 X 12) X-DECODER 12 D OUT BUFFER 53 WAIT READ REGISTER

RAS (DIN0) 65

CAS (DIN1) 64

NLWE 38

NUWE 37

A0 - A9 54 - 63

54 - 65 DIN11 - 0 12 36 IE 37 NUWE

RAS (DIN0) 65

CAS (DIN1) 64

VBB Generator

4 - 9 DO0 - 5 11 - 16 DO6 - 11

3 NRE

2.7.3 FM (IC4302) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name REDE/RX RCLK NRE DO0 DO1 DO2 DO3 DO4 DO5 Vss DO6 DO7 DO8 DO9 DO10 DO11 Vcc Vcc DO12 DO13 DO14 DO15 DO16 DO17 Vss DO18 DO19 DO20 DO21 DO22 DO23 WXINC WR/TR WADE/RX WXAD In/Out In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In Serial read clock Data output enable FMC0B FMC1B FMC2B FMC3B FMC0A FMC1A GND FMC2A FMC3A FMY0B FMY1B FMY2B FMY3B Power supply Power supply FMY4B FMY5B FMY6B FMY7B FMY0A FMY1A GND FMY2A FMY3A FMY4A FMY5A FMY6A FMY7A Line address +1 increment L:fixed Write address reset mode enable/Write data transfer Write address input enable/Write address reset Write address data (serial) A ch luminance signal output to DSP IC4301 A ch luminance signal output to DSP IC4301 B ch luminance signal output to DSP IC4301 B ch luminance signal output to DSP IC4301 A ch chroma signal output to DSP IC4301 A ch chroma signal output to DSP IC4301 B ch chroma signal output to DSP IC4301 REF. Read address input enable/Read address reset

Table 2-7-1 FM (IC4302) pin functions-1/2

2-26

FM (IC4302) pin functions-2/2


Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 IE NUWE NLWE WCLK DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14 DIN13 DIN12 Vss WAIT DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 D/F Vss RXINC RR RXAD Pin Name In/Out In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In Input enable Upper bank write enable Lower bank write enable Write serial clock TMY7A TMY6A TMY5A TMY4A TMY3A TMY2A TMY1A TMY0A TMC3A TMC2A TMC1A TMC0A GND Not used TMY7B TMY6B TMY5B TMY4B TMY3B TMY2B TMY1B TMY0B TMC3B TMC2B TMC1B TMC0B Mode select L: fixed GND Line address +1 incremant L: fixed Read address reste mode enable L: fixed Read address data (serial) B ch chroma signal input from DSP IC4301 B ch luminance signal intput from DSP IC4301 A ch chroma signal input from DSP IC4301 A ch luminance signal intput from DSP IC4301 REF.

Table 2-7-1 FM (IC4302) pin functions-2/2

2-27

2.8

DVIO (IC3202)

During recording, 4:2:2 video data (Y: 8 bits /Cr, Cb: 8bits 13.5 MHz) from the camera is converted to the 4:1:1 (*4:2:0) (Y/C: 8 bits 18 MHz) and output to the shuffle memory. During playback, the 4:1:1 (*4:2:0) DVC data is converted to the 4:2:2 internal data and sent to the analog video output. In the playback digital mode, the 4:1:1 data is sent to the camera (YMCA). At this time, the color difference signal is sent by the method which divides the data into upper 4 bits and lower 4 bits. The analog output has four DACs-Y, C, Cr, and Cb while a synchronization block has been added for the Y signal. A color encoder and burst function are also incorporated for the C signal. 2.8.1 DVIO (IC3202) pin assignment and block diagram
TEST1 TEST0 VDD2V VDD3V VSS DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1 DUMMY0 INV INH YSI7 YSI6 YSI5 YSI4 YSI3 YSI2 YSI1 YSI0 VDD2V VDD32 VSS CSI7 CSI6 CSI5 CSI4 CSI3 CSI2 CSI1 CSI0 CAMCLK REFCLK PBY7 PBY6 PBY5 PBY4 PBY3 PBY2 PBY1 PBY0 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89

TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 SCAN VSS VDD3V VDD2V INF TRST TMS TCK TDI TDO VSS SHORTCUT VMASK PWROFF YADJ CPSYNC YIN YADVREFH YADVBSI AVSS YADVREFM YADVREFL AVDD AVSS CIN CADVREFH CADVBSI AVSS CADVREFM CADVREFL AVDD AVSS ADVSS ADVDD ADVSS ADVDD

Signal Selector

4:2:2 4:1:1

Color Bar Generator

Clock Conv.

4:2:2 4:1:1

PLL

FRPGEN

1/20

Y DAC

C DAC

Cr DAC

Cb DAC

PC 1/2

88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

VDD2V VDD32 VSS PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBVS PBHS DSF7 DSF6 DSF5 DSF4 DSF3 DSF2 DSF1 DSF0 VDD2V VDD23 VSS CLK18M1 CLK450K CLK18M2 CLK188M CASVD CASHD FRP SDIO SCLK STP LCDCK VSS VDD2V RST APCRST MCVS VSS XOUT XIN VDD3V

Fig. 2-8-1 DVIO (IC3202) pin assignment and block diagram


2-28

YDAVREF YDABIAS YOUT AVDD AVSS CDAVREF CDABIAS COUT ADVDD ADVSS CRDAVREF CRDABIAS CROUT AVDD AVSS CBDAVREF CBDABIAS CBOUT ADVDD ADVSS PWDNADDA POFF27 POFF18 POFFCG FILSW27 FILSW18 EVFHD VBLK CGFD VSS CLK27IN CLK27OUT CLK18IN CLK18OUT VDD3V VDD2V CLKCGIN CLKCGOUT VSS PC27C PC27H PC18C PCCG CLKCG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

2.8.2 DVIO (IC3202) pin functions-1/4


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name YDAVREF YDABIAS YOUT AVDD AVSS CDAVREF CDABIAS COUT ADVDD ADVSS CRDAVREF CRDABIAS CROUT AVDD AVSS CBDAVREF CBDABIAS CBOUT ADVDD ADVSS PWDNADDA POFF27 POFF18 POFFCG FILSW27 FILSW18 EVFHD VBLK CGFD VSS CLK27IN CLK27OUT CLK18IN CLK18OUT VDD3V VDD2V CLKCGIN CLKCGOUT VSS PC27C PC27H PC18C PCCG CLKCG In/Out In In Out In In Out In In Out In In Out In Out Out Out Out In In Out In Out Y-DAC reference voltage Y-DAC bias Luminance signal output Power supply GND C-DAC reference voltage C-DAC bias Color signal output Power supply GND Cr-DAC reference voltage Cr-DAC bias Chroma signal output Power supply GND Cb-DAC reference voltage Cb-DAC bias Chroma signal output Power supply GND Not used H:fixed Not used 18M VCO power off control Not used H:fixed Not used 18M VCO input serect control H pulse for OSD Brank pulse for OSD Not used GND Not used L: fixed Not used Clock input 18MHz Feed back 3V power supply 2V power supply Not used Not used GND Not used Not used 18MHz phase comparison output Not used Not used REF.

Table 2-8-1 DVIO (IC3202) pin functions-1/4


2-29

DVIO (IC3202) pin functions-2/4


Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 XIN XOUT VSS MCVS APCRST RST VDD2V VSS LCDCK STP SCLK SDIO FRP CASHD CASVD CLK188M CLK18M2 CLK450K CLK18M1 VSS VDD23 VDD2V DSF0 DSF1 DSF2 DSF3 DSF4 DSF5 DSF6 DSF7 PBHS PBVS PBC0 PBC1 PBC2 PBC3 PBC4 PBC5 PBC6 PBC7 VSS VDD32 VDD2V Pin Name VDD3V In/Out In Out Out In In In In In/Out Out Out Out In Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out Out Out Out Out Out GND 2/3V power supply (2V or 3V) 2V power supply Not used Cr, Cb signal output for PB digital to DSP IC4301 H reference for PB digital V reference for PB digital Data bus from/to shuffle memory from/to IC3002 3V power supply 27MHz X'tal OSC input 27MHz X'tal OSC output GND Frame reference output Reset Reset 2V power supply GND Not used Serial communication enable from MSD IC1401 Serial clock from MSD IC1401 Serial data from MSD IC1401 Frame pulse output H reference for CAS IC3001 V reference for CAS IC3001 Memory write timing 18/8=2.25MHz Clock output 18MHz Clock output 450KHz Clock output 18MHz GND 2/3V power supply (2V or 3V) 2V power supply REF.

Table 2-8-1 DVIO (IC3202) pin functions-2/4


2-30

DVIO (IC3202) pin functions-3/4


Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pin Name PBY0 PBY1 PBY2 PBY3 PBY4 PBY5 PBY6 PBY7 REFCLK CAMCLK CSI0 CSI1 CSI2 CSI3 CSI4 CSI5 CSI6 CSI7 VSS VDD32 VDD2V YSI0 YSI1 YSI2 YSI3 YSI4 YSI5 YSI6 YSI7 INH INV DUMMY0 DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 VSS VDD3V VDD2V TEST0 TEST1 In/Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In In In In In In In In GND 3V power supply 2V power supply Not used Not used (L: fixed) H reference V reference Camera Y signal input from DSP IC4301 GND 2/3V power supply (2V or 3V) 2V power supply Camera Cr, Cb signal input from DSP IC4301 Data transfer clock 13.5MHz Not used Y signal output for PB digital to DSP IC4301 REF.

Table 2-8-1 DVIO (IC3202) pin functions-3/4


2-31

DVIO (IC3202) pin functions-4/4


Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin Name TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 SCAN VSS VDD3V VDD2V INF TRST TMS TCK TDI TDO VSS SHORTCUT VMASK PWROFF YADJ CPSYNC YIN YADVREFH YADVBSI AVSS YADVREFM YADVREFL AVDD AVSS CIN CADVREFH CADVBSI AVSS CADVREFM CADVREFL AVDD AVSS ADVSS ADVDD ADVSS ADVDD In/Out In In In In In Out Not used GND Not used (L: fixed) Not used Power supply GND Not used (L: fixed) Not used GND Not used Not used (L: fixed) Power supply GND GND Power supply GND Power supply Not used (L: fixed) Not used GND Not used (L: fixed) For boundaly scan Not used (L: fixed) GND 3V power supply 2V power supply Frame reference pulse from DV I/F IC8001 Not used (L: fixed) REF.

Table 2-8-1 DVIO (IC3202) pin functions-4/4


2-32

2.9

PLL (IC3201)

2.9.1 PLL circuit description The reference clock of the DVC circuit 18 MHz is generated by the VCO inside the PLL IC3201. During playback and camera picture recording, the switch in the PLL IC is connected to the Pin 33 input. At this time, the 18 MHz clock is locked to the 27 MHz of the crystal oscillator X1401. During DV input recording, the switch is set to the 1394 REC side, and the 18 MHz clock is synchronized with the frame pulse of the DV input (reception) signal from the digital interface. The PC (Phase Comparator) is located inside the MSD IC1401. This 18 MHz clock is sent to the shuffle memory as CLK18M1 from Pin 62 and output from Pin 64 to the CAS, EDA, and digital IF as the CLK18M2. The frequency-divided 450 KHz is sent to the EDA PC as the CLK450K from Pin 63, to become the reference of the recording clock VCO.

DVIO
X1401 XIN 46

IC3202 PLL
REF PLAY CAMERA REC

1/6

IC3201

27MHz CLK18IN 33

1/4

4.5MHz

PC

42

PC18C

33

18MHz

VCO
1394 REC

25

62/64

CLK18M1/M2 35 CLK540K

1/20

63

FRPGEN SSG YMCA


INV/INH 118/119 PBVS/PBHS 76/77

58

FRP

MSD
62

IC1401

DIF

INF 145

REF

49

MCVS

63

PC

95

VPLL

Fig. 2-9-1 PLL circuit block diagram IC3201 mode switching settings The mode of the IC3201 18 MHz PLL is switched by the settings of Pins 29 and 30, while the mode of the audio FS frequency PLL is switched by the settings of Pins 39 and 40.
CONTROL INPUT PB/CAMERA REC (Pin 33) 1394 REC (Pin 35) Power Save Pin 29 H L L Pin 30 L H L FSCLK (Pin46) CONTROL INPUT 12.3M (48K) 11.3M (44.1K) 8.2M (32K) Pin 40 H L H Pin 39 L L H

Table 2-9-1 PLL (IC3201) mode settings


2-33

2.9.2 PLL (IC3201) pin assignment


NC FSGND FSCLK FSGND FSf0ADJ FSVCC FSBFOUT FSBFIN FSSEL1 FSSEL0 NC 18AMP1OUT 27BFIN 27BFOUT 27AMP1IN 27AMP1OUT 27AMP2IN 27AMP2OUT 27GND 27SEL1 27SEL0 27OSCIN 27OSCOUT 27VCC 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37

36 35 34 33 32 31 30 29 28 27 26 25

18AMP1IN 18BFIN 18BFOUT 18AMP2IN 18AMP2OUT 18VCC 18SELO 18SEL1 18OSCIN 18OSCOUT 18GND 18CLK

Fig. 2-9-2 PLL (IC3201) pin assignment 2.9.3 PLL (IC3201) block diagram

Fig. 2-9-3 PLL (IC3201) block diagram


2-34

27CLK 27GND CGSEL CGBFIN CGBFOUT CGAMPIN CGAMPOUT CGGND CGf0ADJ CGVCC CGCLK 18GND

13 14 15 16 17 18 19 20 21 22 23 24

2.9.4 PLL (IC3201) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name 27BFIN 27BFOUT 27AMP1IN 27AMP1OUT 27AMP2IN 27AMP2OUT 27GND 27SEL1 27SEL0 27OSCIN 27OSCOUT 27VCC 27CLK 27GND CGSEL CGBFIN CGBFOUT CGAMPIN CGAMPOUT CGGND CGF0ADJ CGVCC CGCLK 18GND 18CLK 18GND 18OSCOUT 18OSCIN 18SEL1 18SEL0 18VCC 18AMP2OUT 18AMP2IN 18BFOUT 18BFIN 18AMP1IN 18AMP1OUT NC FSSEL0 FSSEL1 FSBFIN FSBFOUT FSVCC FSF0ADJ FSGND FSCLK FSGND NC In/Out Out Out In Out In In In Out In Out Out REF.

Not used

GND for 27MHz VCXO Not used (L: fixed) Not used VCC for 27MHz VCXO Not used GND for 27MHz VCXO Not used (L: fixed)

Not used

GND for CGVCO Not used (L: fixed) VCC for CGVCO Not used GND for 18MHz VCO 18MHz VCO clock output GND for 18MHz VCO 18MHz VCO OSC out 18MHz VCO OSC in 18MHz VCO operation mode select 18MHz VCO operation mode select VCC for 18MHz VCO 18MHz VCO control amp. Output 18MHz VCO control amp. Input Not used 18MHz VCO control buffer input 18MHz VCO control amp. Input 18MHz VCO control amp. Output Not used FSVCO operation mode select FSVCO operation mode select FSVCO control buffer input FSVCO control buffer output VCC for FSVCO VCO oscillation frequency adjustment VCC for FSVCO FSVCO clock output GND for FSVCO Not used

Table 2-9-2 PLL (IC3201) pin functions


2-35

2.10 SHUFFLE MEMORY (IC3002)


This IC is an about 5 Mbit DRAM. This memory capacity enables the storing of one sheet of screen (frame). In shuffling/de-shuffling during recording or play-back, the system controls the read-out/write-in addresses for each frame of data written into this memory. 2.10.1 Shuffle memory (IC3002) pin assignment

A2 A3 A4 NC A5 A6 NC A7 A8 VSS VSS VSS NC VDD1 VDD1 VDD1 NC CE VDD2 VDD2 SOC NC RS DOCTL OE

22 11 2 14 23 12 27 3 13 4 5 6 28 24 25 26 35 15 16 34 7 36 17 8 18

87 66 1 10 19 65 20 21 64 33 97 96 95 67 59 58 63 72 71 62 70 83 92 61 54

NC NC A1 A0 DOI8 NC DOI7 DOI6 NC DOI5 VSS VSS VSS VDD2 VDD2 DIO8 NC DIO7 DIO6 NC DIO5 A17 A16 NC VDD2

73 84 93 60 74 85 55 94 86 77 76 75 53 69 57 56 88 98 52 89 78 51 99 90 79

A15 A14 A13 NC A12 A11 NC A10 A9 VDD1 VDD1 VDD1 NC VSS VSS VSS WS SIC NC WE CS NC TCK TMS TDI

Fig. 2-10-1 Shuffle memory (IC3002) pin assignment

NC NC VSS DIOS DOI4 NC DOI3 DOI2 NC DOI1 VDD2 VDD2 NC VSS VSS DIO4 NC DIO3 DIO2 NC DIO1 TDO TRST NC NC

37 38 32 9 31 39 30 29 40 42 41 46 45 43 44 68 47 80 81 48 82 91 100 49 50

2-36

2.10.2 Shuffle memory (IC3002) pin functions-1/2


Pin No.
22 11 2 14 23 12 27 3 13 4 5 6 28 24 25 26 35 15 16 34 7 36 17 8 18 37 38 32 9 31 39 30 29 40 42 41 46 45 43 44 68 47 80 81 48 82 91 100 49 50

Pin Name A2 A3 A4 NC A5 A6 NC A7 A8 VSS VSS VSS NC VDD1 VDD1 VDD1 NC CE VDD2 VDD2 SOC NC RS DOCTL OE NC NC VSS DIOS DO14 NC DO13 DO12 NC DO11 VDD2 VDD2 NC VSS VSS DIO4 NC DIO3 DIO2 NC DIO1 TDO TRST NC NC

In/Out In In In In In In In In In In In In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out In -

REF. Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 GND Not used Power supply (+3 V) Not used Shuffle memory chip enable from CAS IC3001 Power supply Clock input (18 MHz) from CLK OSC IC Not used Shuffle memory read strobe rom CAS IC3001 Shuffle memory data output control Output enable (L: fixed) Not used Not used GND Shuffle memory data I/O select from CAS IC3001 Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Power supply (+3 V) Not used GND Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Boundary scan test data output Boundary scan test reset input Not used

Table 2-10-1 Shuffle memory (IC3002) pin functions-1/2


2-37

Shuffle memory (IC3002) pin functions-2/2


Pin No.
79 90 99 51 78 89 52 98 88 56 57 69 53 75 76 77 86 94 55 85 74 60 93 84 73 54 61 92 83 70 62 71 72 63 58 59 67 95 96 97 33 64 21 20 65 19 10 1 66 87

Pin Name TDI TMS TCK NC CS WE NC SIC WS VSS VSS VSS NC VDD1 VDD1 VDD1 A9 A10 NC A11 A12 NC A13 A14 A15 VDD2 NC A16 A17 DIO5 NC DIO6 DIO7 NC DIO8 VDD2 VDD2 VSS VSS VSS DOI5 NC DOI6 DOI7 NC DOI8 A0 A1 NC NC

In/Out In In In In In In In In In In In In In In In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In -

REF. Boundary scan test data input Boundary scan test mode select input Boundary scan test clock input Not used Chip select (H: fixed) Write enable from SHUFFLE Not used Clock input (18 MHz) Shuffle memory control write strobe GND Not used Power supply (+3 V) Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used Not used Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Power supply (+3 V) GND Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Not used Shuffle memory data (8 bit) from/to CAS IC3001 Shuffle memory address (18 MHz, 18 bit) from CAS IC3001 Not used

Table 2-10-1 Shuffle memory (IC3002) pin functions-2/2


2-38

2.11

COMPRESS/AUDIO/SHUFFLE (CAS) (IC3001)

This IC carries out digital signal processing of the video and audio signals on conforming to the DV format. Its comes equipped with the usual LSI functions such as COMPRESS, SHUFFLING, and AUDIO PROCESS. During recording, it controls the address read/write enable of the SHUFFLE MEMORY to shuffle the video signals. After that, it carries out, on the video data, adaptive two-dimensional discrete cosine transform (DCT), re-digitization, and variable length coding (VLC), and saves the data in the synchronization block, and outputs the data to the DVC bus. At the same time, it also performs 1 frame completion shuffling on audio signals, and outputs the data to the DVC bus after saving in the synchronization block. During playback, it performs the reverse process of recording. It extracts video synchronization block data and audio synchronization block data on the DVC bus, and decodes video data and audio data from the extracted data.
IC8001 IC3001 IC3003

D-IF

CAS
SSP DV BUS: BD0-3,SMP

EDA
SSP: Sector(1-track) Start/Stop Pulse SMP: DV BUS Start Mark Pulse

Fig. 2-11-1 DV-BUS connection 2.11.1 CAS (IC3001) pin assignment and block diagram
VSS FRP DIBCK DIMCK DOBCK DOMCK DOLRCK DODAT VSS XI XO VDDE3 VDDE3 VDDI2 AIDAT RECMUT VSS DIDAT DILRCK LKFRP SCK SDA STP CLK24 RST SHM225 HSP VSP DFD7 DFD6 DFD5 DFD4 VSS DFD3 DFD2 DFD1 DFD0 VDDE2 VDDE2 VDDI2 CLK18 VSS SMADD17 SMADD16 SMADD15 SMADD14 SMADD13 SMADD12 SMADD11 VSS 104 97 103 96 87 76 102 86 95 75 64 63 74 94 101 73 84 93 100 72 83 92 99 91 98 89 88 90 78 79 77 65 67 66 68 57 53 55 54 42 46 45 44 43 34 36 35 25 23 24 7 14 6 13 22 33 32 12 21 5 41 31 20 11 4 30 10 19 3 29 18 9 2 8 1

Audio ADC/DAC I/F Sample Conv.

m-com I/F

Video Compress DCT/VLC I-DCT/VLD

DV BUS I/F

Shuffle Address

VSS TDI TMS TCK TRST TDO PWMO FS0 FS1 VSS VCOI VCOO VDDE3 VDDI2 VSS TINT0 TINT1 TINT2 TINT3 TINT4 TINT5 TINT6 TINT7 SSP VSS

Fig. 2-11-2 CAS (IC3001) pin assignment and block diagram


2-39

SMADD10 SMADD9 SMADD8 SMADD7 SMADD6 SMADD5 SMADD4 VSS SMADD3 SMADD2 SMADD1 SMADD0 VDDE2 VDDI2 SMCE SMRS VSS SMWE SMWS SMDIOS SMP BD3 BD2 BD1 BD0

81 82 80 70 69 71 61 59 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16

2.11.2 CAS (IC3001) pin functions-1/3


Pin No. 104 97 103 96 87 76 102 86 95 75 64 63 74 94 101 73 84 93 100 72 83 92 99 91 98 81 82 80 70 69 71 61 59 HSP VSP DFD7 DFD6 DFD5 DFD4 VSS DFD3 DFD2 DFD1 DFD0 VDDE2 VDDE2 VDDI2 CLK18 VSS SMADD17 SMADD16 SMADD15 SMADD14 SMADD13 SMADD12 SMADD11 VSS SMADD10 SMADD9 SMADD8 SMADD7 SMADD6 SMADD5 SMADD4 VSS Pin Name SHM225 In/Out Out In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In Out Out Out Out Out Out Out Out Out Out Out Out Out Out GND Shuffle memory address output (18 bits) to SM IC3002 GND Shuffle memory address output (18 bits) to SM IC3002 External 2V power supply Internal 2V power supply System clock input 18MHz from DVIO IC3202 GND REC :from shuflle memory to DCT block PB :from IDCT block to shuffle memory (8 bits) from/to SM IC3002 GND REC :from shuflle memory to DCT block PB :from IDCT block to shuffle memory (8 bits) from/to SM IC3002 REF. Phase reference for shuffle memory (2.25MHz) Horizontal timing control for shuffle memory Vertical timing control for shuffle memory

Table 2-11-1 CAS (IC3001) pin functions-1/3

2-40

CAS (IC3001) pin functions-2/3


Pin No. 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16 1 8 2 9 18 29 3 19 10 30 4 11 20 31 41 Pin Name SMADD3 SMADD2 SMADD1 SMADD0 VDDE2 VDDI2 SMCE SMRS VSS SMWE SMWS SMDIOS SMP BD3 BD2 BD1 BD0 VSS SSP TINT7 TINT6 TINT5 TINT4 TINT3 TINT2 TINT1 TINT0 VSS VDDI2 VDDE3 VCOO VCOI In/Out Out Out Out Out Out Out Out Out Out In/Out In/Out In/Out In/Out In/Out Out In In In In In In In In Out In GND Internal 2V power supply External 3V power supply Clock for PB audio Mode select Not used :normal settings "00000000" GND DVC bus sector start pulse to EDA IC3003, DSP IC4301 DVC bus data (4 bits) from/to EDA IC3003, DIGITAL I/O IC8001, CAS IC3001, DSP IC4301 External 2V power supply Internal 2V power supply Shuffle memory chip enable to SM IC3002 Shuffle memory read strobe to SM IC3002 GND Shuffle memory write enable to SM IC3002 Shuffle memory write strobe to SM IC3002 Shuffle memory I/O control to SM IC3002 DVC start mark pulse to EDA IC3003 Shuffle memory address output (18 bits) to SM IC3002 REF.

Table 2-11-1 CAS (IC3001) pin functions-2/3

2-41

CAS (IC3001) pin functions-3/3


Pin No. 5 21 12 32 33 22 13 6 14 7 24 23 25 35 36 34 43 44 45 46 42 54 55 53 57 68 66 67 65 77 79 78 90 88 89 VSS FS1 FS0 PWMO TDO TRST TCK TMS TDI VSS RST CLK24 STP SDA SCK LKFRP DILRCK DIDAT VSS RECMUT AIDAT VDDI2 VDDE3 VDDE3 XO XI VSS DODAT DOLRCK DOMCK DOBCK DIMCK DIBCK FRP VSS Pin Name In/Out Out Out Out Out In In In In In In/Out In/Out In/Out In In In In In In Out In Out Out Out Out In In In GND Reset Clock output 24.576MHz Serial communication start/stop control Serial data Serial clock Frame pulse for audio L/R clock at audio digital input Serial data in at audio digital input GND REC mute control signal of audio data Data input from audio A/D converter IC2101 Internal 2V power supply External 3V power supply Clock for audio and digital I/F (24.576MHz) GND Serial data output to audio D/A converter IC2101 L/R clock output to audio A/D,D/A converter IC2101 Master clock output to audio A/D,D/A converter IC2101 Bit clock output to audio A/D,D/A converter IC2101 Master clock at audio digital input Bit clock at audio digital input Frame start signal input GND For boundaly scan GND Audio PLL mode select "00":44.1kHz /"01":off /"10":48kHz /"11":32kHz Voltage control for audio PLL REF.

Table 2-11-1 CAS (IC3001) pin functions-3/3

2-42

2.12 ECC/DCI/ATF (EDA) (IC3003)


This IC carries out error correction coding (ECC), 24-25 modulation/demodulation (DCI), tracking error detection (ATF), head switch signal generation, VITERBI decoding, and clock phase correction. During recording, the AUDIO and VIDEO data from the DV bus and the AUX and SUBCODE data from the microprocessor (MSD) are received, error correction coding and 24-25 modulation are performed according to the DV format to generate recording signals, which are the output to the REC amplifier. During playback, the playback signal from the PB equalizer is VITERBI decoded, sync block extraction, and corrected by error correction decoding. The AUDIO and VIDEO data are output to the DV bus and the AUX and SUBCODE data to the microprocessor (MSD). In VITERBI decoding, the clock phase for the VITERBI A/D converter is detected, and phase compensation control the PBEQ IC is carried out. At the same time, the ATF pilot signal components are detected from the playback signal prefiltered in the PBEQ, and the tracking error information is sent to the microprocessor (MSD). 2.12.1 EDA (IC3003) pin assignment and block diagram
RD BLW VSSO VDDO2M DT15 ADDT14 ADDT13 ADDT12 ADDT11 ADDT10 ADDT9 ADDT8 VSSO VDDO2M ADDT7 ADDT6 ADDT5 ADDT4 ADDT3 ADDT2 ADDT1 ADDT0 VDDO2M VDDI VSSI VSSO VDDO3 TSR SPA NC FE HID1 HID2 HID3 RECI PBH RECCTRL VDDO3 NC NC PHY_RST NC SKEW IDECO5 IDECO6 IDECO7 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79

ALE VDDI2M VSSI VDDI3 CS RST CYLFG CYLPG PTST0 PTST1 PTST2 PTST3 SCANM SCANI SCANO VDDI VSSI TRST TMS TDI TCK TDO VDDI3 SSP VSSO VDDO2B BD0 BD1 BD2 BD3 SMP VDDI2B

125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

HIDCTL MSD I/F AFTDET A/D SRAM


AUX

SPCTL

SRAM
SUBCODE

CKCTL

PC

ECC/DCI Viterbi

78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47

NC VITON TRICK MEMP REFCLK CKPHASE VCOCTL ADSTB VDDO3 VSSO ADDAT6 ADDAT5 ADDAT4 ADDAT3 ADDAT2 ADDAT1 ADDAT0 VDDI3 VSSI HSE VDDO2 VDDO3 RECCLK EQHLD VSSO PBCLK PBDAT VDDI3 DVCC3 AVCC3 ATFI VTOP

Fig. 2-12-1 EDA (IC3003) pin assignment and block diagram


2-43

VSSI CLK450 CLK18 VDDI2 VSSO VDDO3R LCAS UCAS OE A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS WE VSSO VDDO3R VSSI VDDI DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDO3R VSSO AGND AGND DGND VBTM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

2.12.2 EDA (IC3003) pin functions-1/4


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name VSSI CLK450 CLK18 VDDI2 VSSO VDDO3R LCAS UCAS OE A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS WE VSSO VDDO3R VSSI VDDI DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 In/Out In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Data from/to ECC memory (16 bits) from/to DRAM IC3004 Row address strobe to DRAM IC3004 Write enable to DRAM IC3004 Vss for output buffer section 3V Vdd for buffer of D-RAM I/F Vss for input buffer and inside logic section 2V Vdd for input buffer and inside logic section Address for ECC memory to IC3004 Reference for REC 42MHz VCO System clock input 18MHz from DVIO IC3202 2V Vdd for input buffer and inside logic section Vss for output buffer section 3V Vdd for buffer of D-RAM I/F Lower column address strobe to DRAM IC3004 Upper column address strobe to DRAM IC3004 Output enable to DRAM IC3004 REF. Vss for input buffer and inside logic section

Table 2-12-1 EDA (IC3003) pin functions-1/4

2-44

EDA (IC3003) pin functions-2/4


Pin No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 DQ0 VDDO3R VSSO AGND AGND DGND VBTM VTOP ATFI AVCC3 DVCC3 VDDI3 PBDAT PBCLK VSSO EQHLD RECCLK VDDO3 VDDO2 HSE VSSI VDDI3 ADDAT0 ADDAT1 ADDAT2 ADDAT3 ADDAT4 ADDAT5 ADDAT6 VSSO VDDO3 ADSTB VCOCTL CKPHASE REFCLK MEMP TRICK VITON NC Pin Name In/Out In/Out In In In In In Out In In In In In In In Out Out Out Out Out Vss for output buffer section 3V Vdd for output buffer section Viterbi-A/D power down Rec clock VCO control output Viterbi clock phase correction PWM output Auto EQ adjustment reference clock Not used Not used Viterbi on signal output to Viterbi-A/D IC3005 Not used PB data from Viterbi-A/D IC3005 3V Vdd for buffer of D-RAM I/F Vss for output buffer section GND for analog section of A/D GND for digital section of A/D A/D reference voltage (bottom) A/D reference voltage (top) A/D analog signal input 3V Vcc for analog section of A/D 3V Vcc for digital section of A/D 3V Vdd for input buffer section PB data PB clock Vss for output buffer section Vss for input buffer and inside logic section Rec clock 3V Vdd for output buffer section 2V Vdd for output buffer section Recording signal Vss for input buffer and inside logic section 3V Vdd for input buffer section REF. Data from/to ECC memory (16 bits) from/to DRAM IC3004

Table 2-12-1 EDA (IC3003) pin functions-2/4

2-45

EDA (IC3003) pin functions-3/4


Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Pin Name IDECO7 IDECO6 IDECO5 SKEW NC PHY-RST NC NC VDDO3 RECCTRL PBH RECI HID3 HID2 HID1 FE NC SPA TSR VDDO3 VSSO VSSI VDDI VDDO2M ADDT0 ADDT1 ADDT2 ADDT3 ADDT4 ADDT5 ADDT6 ADDT7 VDDO2M VSSO ADDT8 ADDT9 ADDT10 ADDT11 ADDT12 In/Out Out Out Out Out Out Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Address (15 bits) /data (16 bits) from/to MSD CPU IC1401 2V Vdd for output buffer of Micom I/F Vss for output buffer section Address (15 bits) /data (16 bits) from/to MSD CPU IC1401 Not used PHY reset output Not used 3V Vdd for output buffer section Recording on control Mode settings for PB EQ IC Head switch pulse 3 to PRE/REC IC3502 Not used Head switch pulse 1 to PRE/REC IC3502 Not used ATF sampling pulse HID reference (Drum 150Hz) 3V Vdd for output buffer section Vss for output buffer section Vss for input buffer and inside logic section 2V Vdd for input buffer and inside logic section 2V Vdd for output buffer of Micom I/F Not used (L: fixed) REF.

Table 2-12-1 EDA (IC3003) pin functions-3/4

2-46

EDA (IC3003) pin functions-4/4


Pin No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Name ADDT13 ADDT14 DT15 VDDO2M VSSO BLW RD ALE VDDI2M VSSI VDDI3 CS RST CYLFG CYLPG PTST0 PTST1 PTST2 PTST3 SCANM SCANI SCANO VDDI VSSI TRST TMS TDI TCK TDO VDDI3 SSP VSSO VDDO2B BD0 BD1 BD2 BD3 SMP VDDI2B In/Out In/Out In/Out In/Out In In In In In In In In In In In In In In In In In Out In In/Out In/Out In/Out In/Out In/Out Start mark pulse 2V Vdd for input buffer of DV-BUS I/F DV-BUS data from/to CAS IC3001 3V Vdd for input buffer section Sector start pulse from IC3001 Vss for output buffer section 2V Vdd for output buffer of DV-BUS I/F For boundaly scan Scan mode switching Scandata input Not used 2V Vdd for input buffer and inside logic section Vss for input buffer and inside logic section Vss for input buffer and inside logic section REF. Address (15 bits) /data (16 bits) from/to MSD CPU IC1401 Data (16 bits) from/to MSD CPU IC1401 2V Vdd for output buffer of Micom I/F Vss for output buffer section Write strobe from MSD CPU IC1401 Read strobe from MSD CPU IC1401 Address lutch enable from MSD CPU IC1401 2V Vdd for input buffer of Micom I/F Vss for input buffer and inside logic section 3V Vdd for input buffer section Vss for input buffer and inside logic section Reset Drum FG from MDA IC1601 Drum PG from MDA IC1601

Table 2-12-1 EDA (IC3003) pin functions-4/4

2-47

2.13

DYNAMIC DRAM (DRAM) (IC3004)

This IC is a CMOS (Complementary Metal Oxide Semiconductor) DRAM having a storage capacity of 256 words 16 bits. 2.13.1 DRAM (IC3004) pin assignment
DQ15 DQ14 DQ13 DQ12 DQ11 50 DQ10 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD VDD DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS 51

64

63

62

61

60

59

58

57

56

55

54

53

DQ6 DQ7 NC NC NC NC NC NC NC NC NC NC NC NC WE RAS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

52

DQ9 DQ8 VDD NC NC NC NC NC NC NC NC NC NC LCAS UCAS OE

VDD

NC

A0

A1

A2

A3

NC

NC

NC

NC

A4

A5

A6

A7

Fig. 2-13-1 DRAM (IC3004) pin assignment 2.13.2 DRAM (IC3004) block diagram
RAS UCAS LCAS
16 34 35

CLOCK GENERATOR

LOWER BYTE CLOCK UPPER BYTE CLOCK

VSS

LOWER WRITE CLOCK UPPER WRITE CLOCK

A8

15

WE

CBR REFRESH COUNTER

A0 A8 A0 - A8
18 -21, 28 -32

I/O SELECTOR

ROW ADDRESS BUFFER COLUMN ADDRESS BUFFER

WORD DRIVER

A0 - A8

ROW DECODER

MEMORY CELL

DATA INPUT BUFFER

DATA INPUT BUFFER DQ0 DQ7 DQ8 DQ15

58 - 61 63, 64, 1, 2 47 - 50, 52 - 55

SENSE AMP

V SS V DD

26, 56 23, 57

COLUMN DECODER ON CHIP V B B GENERATOR V BB

DATA OUTPUT BUFFER

DATA OUTPUT BUFFER


33

OE

Fig. 2-13-2 DRAM (IC3004) block diagram


2-48

2.13.3 DRAM (IC3004) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DQ6 DQ7 VSS NC NC NC NC NC NC NC NC NC NC NC WE RAS NC A0 A1 A2 A3 NC VDD NC NC VSS NC A4 A5 A6 A7 A8 Pin Name In/Out In/Out In/Out In In In In In In In In In In In Address input from EDA IC3003 (9bit) Not used Power supply (+3.0V) Not used GND Not used Address input from EDA IC3003 (9bit) Write enable input from EDA IC3003 Row address strobe from EDA IC3003 Not used Not used Data I/O from/to EDA IC3003 (16bit) GND REF.

Table 2-13-1 DRAM (IC3004) pin functions-1/2

2-49

DRAM (IC3004) pin functions-2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 OE UCAS LCAS NC NC NC NC NC NC NC NC NC NC VDD DQ8 DQ9 DQ10 DQ11 VSS DQ12 DQ13 DQ14 DQ15 VSS VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 Pin Name In/Out In In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Power supply (3.0V) Data I/O from/to EDA IC3003 (16bit) Data I/O from/to EDA IC3003 (16bit) GND Power supply (+3.0V) Data I/O from/to EDA IC3003 (16bit) GND Data I/O from/to EDA IC3003 (16bit) Power supply (+3.0V) Not used Output enable input from EDA IC3003 Upper bite, column address, strobe from EDA IC3003 Lower bite, column address, strobe from EDA IC3003 REF.

Table 2-13-1 DRAM (IC3004) pin functions-2/2

2-50

2.14 VITERBI A/D (IC3005)


This IC serves as a 7-bit sampling A-D converter IC. This IC converts 1+DOUT signal output (analog waveform) of the PB EQ (IC3501) into 7-bit digital signal by the internal A-D converter and it sends converted digital signal to the VITERBI circuit (IC3003). 2.14.1 VITERBI A/D (IC3005) pin assignment and block diagram

PWRDWN VREFOUT VREFIN GND VD AIN/ AIN VD GND ENCODE

1 2
REF

20 19 18 17 16 15 14 13 12
TIMING

D0 D1 D2 D3 GND VDD D4 D5 D6 D7

3 4 5 6
T/H ADC OUTPUT STAGING

7 8 9 10

11

Fig. 2-14-1 VITERBI A/D (IC3005) pin assignment and block diagram 2.14.2 VITERBI A/D (IC3005) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name PWRDWN VREFOUT VREFIN GND VD AIN/ AIN VD GND ENCODE D7 D6 D5 D4 VDD GND D3 D2 D1 D0 In/Out In Out In In In In In In Out Out Out Out Out Out Out Not used Digital signal output to EDA IC3003 (after the analog to digital converted) Power supply for digital output GND Digital signal output to EDA IC3003 (after the analog to digital converted) REF. Power down function select (H: Power down mode) Inside reference voltage output (+1.25V typ) Reference voltage input for ADC (+1.25V typ) GND Power supply for analog circuit Analog signal input for ADC Analog signal input for ADC Power supply for analog circuit GND Encode clock input for ADC

Table 2-14-1 VITERBI A/D (IC3005) pin functions


2-51

2.15 PRE/REC (IC3502)


This IC is a head amplifier for 3 channels, however only 2 channels are used in this unit. During recording, it inputs the recording signal HSE from the EDA IC3003 into Pin 7. At the same time, it also inputs the recording current adjustment value from the EVR into Pin 8. During playback, the playback signal is sent to the PB EQ IC3501 from the Pin 64 AGCOUT. The output from Pin 57 is for ATF. The ATF signal is extracted by the BPF in the PB EQ IC3501. From Pin 59, the ENV_OUT is sent to the JIG connector. 2.15.1 PRE/REC (IC3502) pin assignment and block diagram
HA2ACFB HA2DET MON2IN
34

PBSW2

VCC3V

HA2FB

HA2IN

RCUR

RECR

RCTL

HID3

HID2

HID1

RECI

48

47

46

45

44

43

42

41

40

39

38

37

36

35

STAB PBEN MMC INSRH EQHLD ENVDET ENVOUT TRICKH ATFOUT ENVCTL HAOUT VCC3V PBOUT AGCIN GND AGCOUT

49 50 51 52 53

LOGIC RA2 HA2

GND
33

PBH

32 31 30 29 28

PBH2 RA2OUT VCC5V RA1OUT PBH1 GND MON1IN VCC3V HA1IN PBSW1 HA1ACFB HA1FB HA1DET VCC5V RA3OUT PBH3

RA1
54 55 56 57 58 59 60 61 62 63 64 AGC DET AGC AMP 3rd AMP LPF 27

ENV DET

MONITOR

26 25 24

HSW HA1
VREF

23 22 21 20 19

RA3 HA3 GCA

18 17

10

11

12

13

14

15

16

VCC3V

HA3IN

RECR1

RECR2

HA3ACFB

HA3DET

VCC3V

HSE

EVR

HA3FB

GND

PBSW3

Fig. 2-15-1 PRE/REC (IC3502) pin assignment and block diagram

AGCDET

AGCCTL

2-52

MON3IN

GND

2.15.2 PRE/REC (IC3502) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name AGCCTL AGCDET VCC3V RECR1 RECR2 GND HSE EVR HA3DET HA3FB HA3ACFB PBSW3 HA3IN VCC3V MON3IN GND PBH3 RA3OUT VCC5V HA1DET HA1FB HA1ACFB PBSW1 HA1IN VCC3V MON1IN GND PBH1 RA1OUT VCC5V RA2OUT PBH2 In/Out In In Out In In In In In Out Out Out Out Main Vcc 3V Not used GND Not used REC Vcc 5V CH1 head amp detection CH1 head amp feed back CH1 head amp AC feed back CH1 PB-ON switch CH1 head amp in Main Vcc 3V CH1 REC monitor in GND PB-H1 switch control CH1 REC amp out REC Vcc 5V CH2 REC amp out PB-H2 switch control Not used AGC CTL AGC DET-C Main Vcc 3V Resistor for REC GCA Resistor for REC GCA GND REC IN REC GCA adjustment REF.

Table 2-15-1 PRE/REC (IC3502) pin functions-1/2

2-53

PRE/REC (IC3502) pin functions-2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND MON2IN VCC3V HA2IN PBSW2 HA2ACFB HA2FB HA2DET RECR RCUR RECI PBH HID1 HID2 HID3 RCTL STAB PBEN MMC INSRH EQHLD ENVDET ENVOUT TRICKH ATFOUT ENVCTL HAOUT VCC3V PBOUT AGCIN GND AGCOUT Pin Name In/Out In In In In In Out Out In In In In In In In In Out Out In Out Out In Out GND CH2 REC monitor in Main Vcc 3V CH2 head amp in CH2 PB-ON switch CH2 head amp AC feed back CH2 head amp feed back CH2 head amp detection Resistor for REC monitor REC monitor out REC insert switch PB:H control Head switch 1 Head switch 2 Head switch 3 REC ON/OFF control ON: H Stand by PB EN switch Capacitor for mono-mulch Insert: H output Not used Capacitor for envelope detect Not used Envelope control 1 ATF signal output Envelope control 2 PB envelope output Main Vcc 3V PB signal out AGC in GND AGC output to PB-EQ REF.

Table 2-15-1 PRE/REC (IC3502) pin functions-2/2

2-54

2.16 PB EQUALIZER (IC3501)


The PB equalizer equalizes the waveform of the playback signal to prevent coding errors by interference between coding processes when the high-density digital signal is magnetically recorded and played back. In the PLL circuit, the playback clock that is phase controlled for correctly identifying the playback data is generated. This IC also has an ATF signal extraction BPF and recording clock 41.85 MHz VCO for recording. 2.16.1 PB_EQ (IC3501) pin assignment and block diagram
1+D_OUT 1+D_OUT AGC_IN EQHLD ERRDL PLL_IN

DLADJ

GND7

GND6

VCC7

ERR2

ERR1
50

64

63

62

61

60

59

58

57

56

55

54

53

52

51

TFIL_OUT

VIT_ON ATF_IN GND1

1+D_IN

49

VCC6

PB_H

1 2 3 4 5

LOGIC DELAY CONT BPF BP_OUT AM_PIN AMP

48 AMP 1+D DATA DET 47 46 45 44 43 AMP A-EQ 42 41 VCO 40 39 PS

SDET2 GND5 SDET1 VCC5 PC_OUT AMP_IN AMP_OUT VCO_IN PHASEADJ MON3 CK_PHASE VCC4 AD_CLK PB_CLK GND4 PB_DAT

PC ERROR DET

VCC1 ATFC ATF_GAIN ATFI_OUT REFDET REFCLK TRICK_H TRICK_L BETA ALFA MON1

6 7 8 9 10 11 12 13 14

GCA TFIL REFF PRE-EQ

38 37 36 35 LATCH OUTPUT 34

OUTPUT LPF OUTPUT

15 PRE_EQ TFIL_IN 16 BUFF AMP VCO OUTPUT

33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

RECCLK

VCC2

VCC8

GND2

VCOCTL

Fig. 2-16-1 PB_EQ (IC3501) pin assignment and block diagram

2-55

AMP_OUT

VCO_IN

MON2

GND3

VCC3

DET1

DET2

DET3

DET4

32

2.16.2 PB_EQ (IC3501) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name VIT_ON ATF_IN GND1 BP_OUT AMP_IN VCC1 ATFC ATF_GAIN ATFI_OUT REFDET REFCLK TRICK_H TRICK_L BETA ALFA MON1 PRE_EQ TFIL_IN MON2 DET1 DET2 DET3 DET4 GND2 VCOCTL VCC2 AMP_OUT VCC8 VCO_IN GND3 RECCLK VCC3 In/Out In In Out In Out In Out In In Out In In Out In In Out In Out Bit by Bit/VITERBI select ATF BPF input GND1 ATF BPF output ATF AMP input VCC1 ATF AMP output ATF gain control adjustment ATF output Reference frequency control voltage detection Reference clock for ATF BRF (450KHz) Inverter input Inverter output PRE-EQ phase characteristic adjustment (b) PRE-EQ frequency characteristic adjustment (a) PRE-EQ delay monitor (not used) PRE-EQ output TFIL input Not used Auto-EQ detection 1 Auto-EQ detection 2 Auto-EQ detection 3 Auto-EQ detection 4 GND2 Phase error input VCC2 Phase error amp output VCC8 REC clock VCO input GND3 REC clock VCO output VCC3 REF.

Table 2-16-1 PB_EQ (IC3501) pin functions-1/2

2-56

PB_EQ (IC3501) pin functions-2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name PB_DAT GND4 PB_CLK AD_CLK VCC4 CK_PHASE MON3 PHASEADJ VCO_IN AMP_OUT AMP_IN PC_OUT VCC5 SDET1 GND5 SDET2 VCC6 ERR1 ERR2 GND6 1+D_OUT ERRDL PLL_IN 1+D_OUT VCC7 1+D_IN TFIL_OUT DLADJ GND7 AGC_IN PB_H EQHLD In/Out Out Out Out In In In Out In Out In Out In In Out In Out In In In In PB data output GND4 PB clock output VITERBI A/D converter clock output VCC4 Clock phase adjustment input from VITERBI Not used Clock phase adjustment input from EVR PB VCO input Phase error amp output Phase error amp input PLL phase error output VCC5 Slice level adjustment GND5 Slice level detection VCC6 For error signal detection For error signal detection GND6 PB 1+D signal output to Viterbi A/D Error timing adjustment PB data 3-state detect, PLL input 1+D output to 3-state detect, PLL VCC7 1+D input TFIL output Delay adjustment GND7 PRE-EQ input PB/REC select (PB: H) EQ hold select REF.

Table 2-16-1 PB_EQ (IC3501) pin functions-2/2

2-57

2.16.3 PB EQ circuit The playback enveropes input from the PREAMP is subjected to optimum waveform equalization suitable for decoding at the PRE-EQ and AUTO-EQ. After that it is added with 1+D characteristics, and output to the VITERBI A/D converter as 1+DOUT. The 1+DOUT signal is an analog waveform with tertiary value (1, 0, -1). It is converted to 7-bits digital signal by the A/D converter, and sent to the VITERBI circuit. The digitized tertiary information is corrected by the VITERBI detection method and converted into the binary (0, 1) playback data. The 1+DOUT signal is re-input into the IC3501, and output as the PB DATA after tertiary detection and binary conversion by the fixed threshold value method in the DATA DET circuit, to become the playback data when the VITERBI is OFF. However in this unit, as VITERBI is always ON for both SP and LP, this applies only when VITERBI is forcibly turned OFF using the service support software. The playback clock is constantly phase-compared with the playback data in the PLL circuit, and output synchronized with the playback data. One is output to the A/D converter as the AD CLK, and the other is sent to the EDA as the PB CLK. As the sampling point is also changed during A/D conversion by this AD CLK, there is a need for sampling to be carried out at the correct position for the VITERBI detection circuit to operate correctly. Therefore the phase correction information from the VITERBI circuit is output as the CK PHASE, and the PS (phase shift) of the PLL circuit carries out fine adjustments of the phase. The adjustment values are input from the EVR IC3503 based on the data written in the EEPROM. In the adjustments, the service support software adjusts the values to the standard values by VCO Center adjustment first, after which the error rates are sequentially adjusted to the minimum values according to the order in which the other adjustment points were specified in the PB EQ adjustment.
Delay ADJ PB EQ IC3501 From: PREAMP AGC IN 1+D OUT
IC3005

ADDAT 0:6 7bits

EDA IC3003 To:ECC/DCI

PRE-EQ

LPF

TFIL

1+D

A/D CONV.

VITERBI

A-EQ

ERR DET BUFFER


Q3501,3503

AD CLK

a ADJ b ADJ

Error Timing ADJ Slice Level ADJ DATA DET LATCH PB DATA PB CLK

PC

LPF

VCO Voltage ADJ PS VCO

CK PHASE

PLL Phase ADJ

Fig. 2-16-2 PB_EQ block diagram

2-58

2.17 EVR DA CONV. (IC3503)


This IC incorporates 14-bit shift register for chip control. Configuration of its 14-bit data is 8 bits for D-A output and the other 6 bits for channel selection. 2.17.1 DAC (IC3503) pin assignment
GND VSS AO3 AO2 AO1 CLK 26 LD 25 24 23 22 21 20 19 18 17 10 11 12 13 14 15 16 9 DI 27

31

32

30

AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11

1 2 3 4 5 6 7 8

29

28

DO AO24 AO23 AO22 AO21 AO20 AO19 AO18

VDD

AO12

AO13

AO14

VCC

AO15

AO16

Fig. 2-17-1 DAC (IC3503) pin assignment 2.17.2 DAC (IC3503) block diagram

DI CLK

27 26 D0 D1 D2 D3 14bit SHIFT RESISTOR D4 D5 D6 D7 D8 D9 D10 D11 D12

AO17

24

DO

CHANNEL DECODER 8 24 1 24

25

LD

8bit RESISTOR

8bit RESISTOR

24

8bit RESISTOR

8bit R-2R D/A CONV. VCC GND 13 28

8bit R-2R D/A CONV.

8bit R-2R D/A CONV. 12 29 VDD VSS

30 AO1

31 AO2

23 AO24

Fig. 2-17-2 DAC (IC3503) block diagram


2-59

2.17.3 DAC (IC3503) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 AO13 AO14 VDD VCC AO15 AO16 AO17 AO18 AO19 AO20 AO21 AO22 AO23 AO24 DO LD CLK DI GND VSS AO1 AO2 AO3 Pin Name In/Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In Out 8bit D/A output (built-in OP amp.) to PRE/REC IC3502 Not used Power supply for D/A converter Power supply for MCU interface and OP amp. Not used Not used 8bit D/A output (built-in OP amp.) to SYNC_ADJ Q3203 BASE 8bit D/A output (built-in OP amp.) ASPECT 8bit D/A output (built-in OP amp.) to C_GCTL VIDEO OUT IC3701 8bit D/A output (built-in OP amp.) to Y_GCTL VIDEO OUT IC3701 8bit D/A output (built-in OP amp.) TINT1 8bit D/A output (built-in OP amp.) TINT2 8bit D/A output (built-in OP amp.) YDAVREF Not used Not used Shift register data load: decoder and D/A output register Shift clock input Serial data input (14bit serial data) from SYSCON IC1001 GND for MCU interface and OP amp. GND for D/A converter Not used 8bit D/A output (built-in OP amp.) FS_ADJ 8bit D/A output (built-in OP amp.) to EQ IC3501 Not used 8bit D/A output (built-in OP amp. ) to EQ IC3501 REF.

Table 2-17-1 DAC (IC3503) pin functions

2-60

2.18 ENV D/A CONV. (IC1201)


This IC controls chips by inputting 12-bit data to the shift register. Input data to the shift register is composed of 4 bits of address selection signal and 8 bits of D-A converter control signal, namely 12 bits in total. 12-bit data is input to the sift register through the DI terminals in order from D11 (MSB) to D0 (LSB). 2.18.1 ENV D/A CONV. (IC1201) pin assignment

VSS A3 A4 A5 A6 A7 A8 A9 A10 VDD

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

GND A2 A1 DI CLK LD DO A12 A11 VCC

Fig. 2-18-1 ENV D/A CONV. (IC1201) pin assignment 2.18.2 ENV D/A CONV. (IC1201) block diagram

DI CLK

17 16 D0 D1 D2 D3 12bit SHIFT RESISTOR D4 D5 D6 D7 D8 D9 D10 D11

14

DO

ADDRESS DECODER 8 12 1 12

15

LD

D0 8bit LATCH

D7 1

D0 12 8bit LATCH

D7

8bit R-2R D/A CONV. VCC GND 11 20

8bit R-2R D/A CONV. 10 1 VDD VSS

18 AO1

13 AO12

Fig. 2-18-2 ENV D/A CONV. (IC1201) block diagram

2-61

2.18.3 ENV D/A CONV. (IC1201) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS A3 A4 A5 A6 A7 A8 A9 NC VDD VCC NC NC NC LD CLK DI A1 A2 GND Pin Name In/Out Out Out Out Out Out Out Out In In In Out Out 12 bit shift register data load: decoder and D/A output registor (H: load) Shift clock 12 bit serial data input 8bit D/A output H_GAIN 8bit D/A output H_OFFSET Power supply for MCU interface and OP amp. Not used GND for D/A converter 8 bit D/A output to SUB CONT V DRIVER IC4101 8 bit D/A output to HISCONT CCD 8 bit D/A output to AGCCONT1 CDS/AGC IC5101 8 bit D/A output to OFFSET1 CDS/AGC IC5101 8 bit D/A output to AGCCONT2 CDS/AGC IC5102 8 bit D/A output to OFFSET2 CDS/AGC IC5102 8 bit D/A output to SENS_EVR Not used Power supply for D/A converter Power supply for MCU interface and OP amp. REF.

Table 2-18-1 ENV D/A CONV. (IC1201) pin functions

2-62

2.19

DIGITAL INTERFACE (IC8001)

The digital interface of this unit corresponds to the input/output of the DV terminal (IEEE 1394). The digital interface IC8001 is mounted on one chip with the usual LINK IC and PHY IC. The structure is the same as the previous model, however with the use of the second generation DVC signal processing LSI incorporated from this unit, it eliminates the need for matching the DV BUS data using the gate array as done in the previous model, and the DVS BUS data can be input/output to and from the digital IF IC directly. The MSD IC serves as the host microprocessor. 2.19.1 Digital IF (IC8001) pin assignment and block diagram
SSP VCC CLK18 VCCB(2/3) ADB6/SMPB ADB7/DBB3 ADB8/DBB2 ADB9/DBB1 ADB10/DBB0 GND ADB11/SMPA AD12/DBA3 AD13/DBA2 AD14/DBA1 AD15/DBA0 VCCB(2/3) VCC VCCB(2/3) BCLK /DC ALE NC /LCNTD GND AD0 AD1 AD2 AD3 GND AD4 AD5 AD6 AD7 VCCA(2/3) AD8 AD9 GND ADB5 ADB4 ADB3 ADB2 VCC ADB1 ADB0 ADEN BKRDY GND UPPEN CYCLD CYCLS CLK25 VCC /RST FRP VFRP TEST0 GND TEST1 SI/TEST2 SO SCK VCC /SEN TMS TCK /TRST GND TDI TDO /LISO LLREQ VCC 21 10 1 22 11 2 36 23 12 3 50 37 24 13 4 51 38 25 5 14 6 15 26 39 52 7 16 27 40 53 8 17 28 41 9 18

20 19 35 34 33 32 49 48 47 46 45 62 61 60 59 58 69 68 70 71 72 78 79 80 81 82 88 89 90 91 101 102 103 114 115 116

DVC BUS I/F

ISO Control/ Buffer

m- c o m I/F

ATF ARF

LINK Control (CFR)

LINK

PHY

29 30 31 42 43 44 54 55 56 57 63 64 65 66 67 73 74 75 77 76 87 86 85 84 83 100 99 98 97 96 113 112 111 110 126 125

AD10 AD11 GND AD12 AD13 AD14 AD15 VCCA(2/3) VCC /INTP CYCLEIN NTZIHZ NTOUT GND NTCLK RANEZ LCNA LPWRDN VCC GND DVSS C/LKON LPS CNA TESTM1 TESTM2 /RESET /ISD AVCC PWRDN PLLFLT PLLVDD PLLGND PLLGND XI XO

Fig. 2-19-1 Digital IF (IC8001) pin assignment and block diagram


2-63

LD3 LD2 LD1 LD0 LCTL1 LCTL0 LSYSCLK VCC GND DGND DVCC PC0 PC1 PC2 LREQ CTL0 CTL1 D0 D1 SYSCLK DVCC DGND AGND AGND TPBIAS AGND AGND AVCC AVCC CPS R1 R0 TPBTPB+ TPATPA+

127 136 104 117 128 137 92 105 118 129 138 93 106 119 130 139 131 140 120 107 94 141 132 121 108 95 142 133 122 109 143 134 123 144 135 124

2.19.2 Digital IF (IC8001) pin functions-1/4


Pin No. 20 19 35 34 33 32 49 48 47 46 45 62 61 60 59 58 69 68 70 71 72 78 79 80 81 82 88 89 90 91 101 102 103 114 115 116 GND ADB5 ADB4 ADB3 ADB2 VCC ADB1 ADB0 ADEN BKRDY GND UPPEN CYCLD CYCLS CLK25 VCC /RST FRP VFRP TEST0 GND TEST1 SI/TEST2 SO SCK VCC /SEN TMS TCK /TRST GND TDI TDO /LISO LLREC VCC Pin Name In/Out In In Out In In In In Out Out GND For boundaly scan H:fixed Request signal output from LINK to PHY Power supply For boundaly scan GND Not used Not used (L: fixed) Not used Power supply Reset input Frame pulse input Frame pulse output (at DV input) Not used (L: fixed) GND Not used (L: fixed) Not used Power supply Not used Not used (L: fixed) Power supply Not used (L: fixed) GND REF.

Table 2-19-1 Digital IF (IC8001) pin functions-1/4

2-64

Digital IF (IC8001) pin functions-2/4


Pin No. 127 136 104 117 128 137 92 105 118 129 138 93 106 119 130 139 131 140 120 107 94 141 132 121 108 95 142 133 122 109 143 134 123 144 135 124 LD3 LD2 LD1 LD0 LCTL1 LCTL0 LSYSCLK VCC GND DGND DVCC PC0 PC1 PC2 LREQ CTL0 CTL1 D0 D1 SYSCLK DVCC DGND AGND AGND TPBIAS AGND AGND AVCC AVCC CPS R1 R0 TPBTPB+ TPATPA+ Pin Name In/Out In/Out In/Out In/Out In/Out In In In/Out In/Out In/Out In/Out Out Out In/Out In/Out In/Out In/Out DV terminal (twisted pair cable) Request signal input from LINK to PHY Control signal in/out between LINK and PHY Data in/out betweem LINK and PHY System clock output to LINK (49.152MHz) Power supply GND GND Bias supply for DV terminal GND Power supply Not used (L: fixed) For bias voltage Not used (L: fixed) Not used (L: fixed) Data in/out betweem LINK and PHY Control signal in/out between LINK and PHY System clock input from PHY (49.152MHz) Power supply GND GND Power supply REF.

Table 2-19-1 Digital IF (IC8001) pin functions-2/4

2-65

Digital IF (IC8001) pin functions-3/4


Pin No. 125 126 110 111 112 113 96 97 98 99 100 83 84 85 86 87 76 77 75 74 73 67 66 65 64 63 57 56 55 54 44 43 42 31 30 12 XO XI PLLGND PLLGND PLLVDD PLLFLT PWRDN AVCC /ISD /RESET TESTM2 TESTM1 CNA LPS C/LKON DVSS GND VCC LPWRDN LCNA RANEZ NTCLK GND NTOUT NTZIHZ CYCLEIN /INTP VCC VCCA(2/3) AD15 AD14 AD13 AD12 GND AD11 AD10 Pin Name In/Out In In In Out Out In Out In/Out In/Out In/Out In/Out In/Out In/Out GND Data/address from/to Host (MSD IC1401) Data/address from/to Host (MSD IC) Not used Clock (24.576MHz) GND Power supply For PLL filter PHY power down mode Power supply Not used (L: fixed) PHY reset Not used (L: fixed) 1394 connection detect (connected :L) Not used (L: fixed) Not used (L: fixed) GND GND Power supply Power down mode output to PHY 1394 connection detect input from PHY (connected :L) Not used (L: fixed) GND Not used Not used (L: fixed) DIF interrupt to MSD IC Power supply Power supply REF.

Table 2-19-1 Digital IF (IC8001) pin functions-3/4

2-66

Digital IF (IC8001) pin functions-4/4


Pin No. 18 9 41 28 17 8 53 40 27 16 7 52 39 26 15 6 14 5 25 38 51 4 13 24 37 50 3 12 23 36 2 11 22 1 10 21 AD9 AD8 VCCA(2/3) AD7 AD6 AD5 AD4 GND AD3 AD2 AD1 AD0 GND /LCNTD NC ALE /DC BCLK VCCB(2/3) VCC VCCB(2/3) AD15/DBA0 AD14/DBA1 AD13/DBA2 AD12/DBA3 ADB11/SMPA GND ADB10/DBB0 ADB9/DBB1 ADB8/DBB2 ADB7/DBB3 ADB6/SMPB VCCB(2/3) CLK18 VCC SSP Pin Name In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In Out In In/Out In/Out In/Out In/Out In/Out In In Power supply System clock input 18MHz Power supply DV-BUS sector start pulse Not used (L: fixed) DV-BUS start mark pulse GND DV-BUS data GND Not used (L: fixed) Not used Address lutch enable Access completion signal to Host (MSD IC1401) System clock from MSD IC1401 Power supply Power supply Power supply Data/address from/to Host (MSD IC1401) GND Data/address from/to Host (MSD IC1401) REF. Data/address from/to Host (MSD IC1401) Power supply

Table 2-19-1 Digital IF (IC8001) pin functions-4/4

2-67

2.20

2.20.1 MSD CPU (IC1401) pin assignment

E_SENS S_SENS AVREF AVCC VCC2 VSS AGC_RST BCLK DC R/W ALE RD BLW BHW DO0 DO1/A16 DO2/A17 DO3/A18 DO4/A19 DO5/A20 DO6/A21 DO7/A22 DO8/A23 DO9/A24 D10/A25 D11/A26 D12/A27 D13/A28 D14/A29 D15/A30 VSS VCC2

MSD CPU (IC1401)

125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

Fig. 2-20-1 MSD CPU (IC1401) pin assignment

2-68

VSS HLDA HOLD RESET MODO MOD1 VCC VSS VPP ADC_DEM0 ADC_DEM1 ADC_PWD0 ADC_PWD1 DIC_STP1 DIC_STP2 TRG_OUT P97 VSS OSCVCC XIN XOUT OSCVSS VSS VCC AH_CTL2 AH_CTL1 SLOW TALLY_LED P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 P117 VCC VSS VCC CAM0 CAM1 CAM2 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

DEW_SENS AV/H_DET ANO4 ANO5 ANO6 BCID1 BCID2 BCID3 AN10 AN11 AN12 AVSS P87/ADTRG P86/TC5 P85/TB5 P84/TA5 P77/TB4 P76/TA4 P75/TB3 P74/TA3 P73/TB2 P72/TA2 VCC VSS TAPE_LED FRP MIC_SCK MIC_SDA MIC_CTL A_PLL V_PLL CAP_REF DRUM_REF NMI MSELECT P_DET S_DET P55/INT3 DIF_INT VSS VCC SYS_OUT SYS_IN SYS_CLK MREADY DIC_OUT

DIC_IN DIC_CLK DIF_RST MDA_OUT MDA_IN MDA_CLK MDA_CS RXD TXD CAP_BRK LD_ON DIC_RST VCC VSS PWMD MCVS FRP SSP S_REEL T_REEL SPA HID TSR CAP_FG DRUM_FG VSS VCC RF_STAB RF_FAST RF_TRICK REEL_LED REC_SAFE

2.20.2 MSD CPU (IC1401) pin functions-1/4


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VSS HLDA HOLD RESET MOD0 MOD1 VCC VSS VPP ADC_DEM0 ADC_DEM1 ADC_PWD0 ADC_PWD1 DIC_STP1 DIC_STP2 TRIG_OUT P97 VSS OSCVCC XIN XOUT OSCVSS VSS VCC AH_CTL2 AH_CTL1 SLOW TALLY_LED P104 P105 P106 P109 P110 P111 P112 P113 P114 P115 P116 Pin Name In/Out In Out Out Out Out Out In/Out Out In Out Out Out Out Out Not used GND Not used H: fixed Reset input from SYSCON CPU IC1001 L: fixed H: fixed Power supply GND Power supply REG 5V Sampling frequency select to AUDIO AD/DA IC2101 ADC_DEM0/ADC_DEM1:frequency (L/L:44.1k, L/H:48k, H/L:OFF, H/H:32k) D/A power control power down: L to AUDIO AD/DA IC2101 A/D power control power down: L to AUDIO AD/DA IC2101 Serial communication enable to DVIO IC3202 Communication start/stop signal to/from CAS IC3001 Remote signal output Not used GND Power supply X'tal 27MHz X'tal 27MHz GND GND Power supply REF.

Table 2-20-1 MSD CPU (IC1401) pin functions-1/4

2-69

MSD CPU (IC1401) pin functions-2/4


Pin No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 VCC VSS VCC CAM0 CAM1 CAM2 REC_SAFE REEL_LED RF_TRICK RF_FAST RF_STAB VCC VSS DRUM_FG CAP_FG TSR HID SPA T_REEL S_REEL SSP FRP MCVS PWMO VSS VCC DIC_RST LD_ON CAP_BRK TXD RXD MDA_CS MDA_CLK MDA_IN MDA_OUT DIF_RST DIC_CLK DIC_IN Pin Name P117 In/Out In In In In Out Out Out Out In In In In In In In In In In In Out Out Out Out Out In Out Out Out MDA IC1601 chip select Serial clock to MDA IC1601 Serial data output to MDA IC1601 Serial data input from MDA IC1601 Reset to DIF IC8001 Serial clock to CAS IC3001 and DVIO IC3202 Serial data output to CAS IC3001 and DVIO IC3202 REC safety switch Reel sensor LED control Slow/still: H (for EQ PLL gain adjustment) to PB EQ IC3501 Search: H (for EQ PLL gain adjustment) to PB EQ IC3501 Safety tab (REC prohibition) to PRE/REC IC3502 Power supply GND Drum FG Capstan FG HID reference (drum 150Hz) Head switch pulse ATF sample pulse TU reel pulse SUP reel pulse DVC bus sector start signal from CAS IC3001 Frame reference pulse from DVIO IC3202 1394 frame reference pulse from DVIO IC3202 PWM output for audio PLL GND Power supply Not used Loading motor ON/OFF control Capstan motor brake control Not used Mechanism position detect from rotary encoder Not used Power supply GND Power supply REF.

Table 2-20-1 MSD CPU (IC1401) pin functions-2/4

2-70

MSD CPU (IC1401) pin functions-3/4


Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Pin Name DIC_OUT MREADY SYS_CLK SYS_IN SYS_OUT VCC VSS DIF_INT P55/INT3 S_DET P_DET MSELECT NMI DRUM_REF CAP_REF V_PLL A_PLL MIC_CTL MIC_SDA MIC_SCK FRP TAPE_LED VSS VCC P72/TA2 P73/TB2 P74/TA3 P75/TB3 P76/TA4 P77/TB4 P84/TA5 P85/TB5 P86/TC5 P87/ADTRG AVSS AN12 AN11 AN10 BCID3 In/Out In Out In Out In In In In In In Out Out Out Out Out Out Out In Out Out In Cassette tape ID board information Not used (L: fixed) Write recording data for memory in cassette GND Not used Frame reference pulse from DVIO IC3202 Tape LED control GND Power supply REF. Serial data input from CAS IC3001 and DVIO IC3202 Serial bus ready to SYSCON CPU IC1001 Serial clock to SYSCON CPU IC1001 Serial data output to SYSCON CPU IC1001 Serial data input from SYSCON CPU IC1001 Power supply GND DIF interrupt from DIF IC8001 Not used AV plug detect S-VHS plug detect MSD chip select input from SYSCON CPU IC1001 H: fixed Drum offset voltage output to MDA IC1601 Capstan offset voltage output to MDA IC1601 PLL output to PLL IC3201 (18MHz when 1394 input) Audio PLL output (PWM) to PLL IC3201 For memory in cassette only information of recorded or brand-new tape

Table 2-20-1 MSD CPU (IC1401) pin functions-3/4

2-71

MSD CPU (IC1401) pin functions-4/4


Pin No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Name BCID2 BCID1 AN06 AN05 AN04 AV/H_DET DEW_SENS E_SENS S_SENS AVREF AVCC VCC2 VSS AGC_RST BCLK DC R/W ALE RD BLW BHW D00 D01/A16 D02/A17 D03/A18 D04/A19 D05/A20 D06/A21 D07/A22 D08/A23 D09/A24 D10/A25 D11/A26 D12/A27 D13/A28 D14/A29 D15/A30 VSS VCC2 In/Out In In In In In In Out Out In Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out GND Power supply REG 2.2V Data (16 bits) /address (15 bits) from/to EDA,DIF AV plug/Head phone plug detect (AV: H, HP: L) Dew sensor detect End sensor detect Start sensor detect Reference Voltage 1/2VCC Power supply Power supply REG 2.2V GND Reset to VIDEO OUTPUT DRIVER IC3701 System clock 13.5MHz to DIF IC8001 Access comletion signal from DIF IC8001 Not used Address latch enable Read strobe to EDA IC3003 Write strobe to EDA IC3003 Not used Not used Cassette tape ID board information REF.

Table 2-20-1 MSD CPU (IC1401) pin functions-4/4

2-72

2.21 SYSCON CPU (1001)

2.21.1 SYSCON CPU (1001) pin assignment

OPEN_SW CLOSE_SW AD0 AD1 AD2 AD3 VDD VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 PWR_CTL M16_RDY AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 M16_CS WB_IR_DET F/Z_CS VDD OSCI OSCO VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Fig. 2-21-1 SYSCON CPU (1001) pin assignment

2-73

VF_LD FLDFMC RST GATE_PULSE V_MUTE JLIP_INT VD OMT EXTINDET MENU_P_A BEND RTC_INT AFBEND SLOW LCD_LD OSD_CS EEPROM_CS VDD TIMER_OUT STORDBE_CHG M_P_ON STBY_TG REMOTE S_DT_IN S_DT_OUT S_CLK VF_CTL OSD_DATA OSD_CLK RXD TXD AUDIO_CS 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RE HWE LWE DAC_CS RTC_CS MENU_SET_SW BUZZER M16_RST STO_FOLL AVDD VRefH MONI_RVS PHOTO_MODE KEY_C STOROBE_AD CAM_DAC_CS TG_CS F_PTR_AD Z_PTR_AD HALL_AD IR_AD ZOOM_SW KEY_B KEY_A BATT_CHK VRefL AVSS VSS VDD AFZ_CLK AFZ_DATA RESERVE4

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97

A_MUTE AFADER FADE_H LCD_CS S_SPK_ON SMUTE S_OPEN S_CLOSE IRIS_O/C VDD(VPP) V_P_ON MO_BK_ON M_LR M_U/D F/Z_RST DSP_RST_3 DSP_RST_2 DSP_RST_1 MENU_P_B VF_SW MONITOR_SW CAS_SW EJECT_SW DIAL_PLAY DIAL_OFF DIAL_AUTO DIAL_MANU DIAL_PROGRE DIAL_5S VSS VDD CALE

2.21.2 SYSCON CPU (IC1001) pin functions-1/4


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name OPEN_SW CLOSE_SW AD0 AD1 AD2 AD3 VDD VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 PWR_CTL M16_RDY AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 M16_CS WB_IR_DET F/Z_CS VDD OSCI OSCO VSS In/Out In In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out In In/Out In/Out In/Out In/Out In/Out In In In Out In Out In Out L: fixed L: fixed H: fixed Chip select to MSD IC1401 Not used Chip select to F/Z DRIVER IC4851 Power supply System clock (16MHz) System clock (16MHz) GND Address/Data from/to MPX BUS 16bits YMCA IC4301 Power control MSD IC1401 READY Address/Data from/to MPX BUS 16bits YMCA IC4301 Power supply GND Address/Data MPX BUS 16bits from/to YMCA IC4301 Lens shutter switch (Open control) Lens shutter switch (Close control) REF.

Table 2-21-1 SYSCON CPU (IC1001) pin functions-1/4

2-74

SYSCON CPU (IC1001) pin functions-2/4


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name VF_LD FLDFMC RST GATE_PULSE V_MUTE JLIP_INT VD OMT EXTINDET MENU_P_A BEND RTC_INT AFBEND SLOW LCD_LD OSD_CS EEPROM_CS VDD TIMER_OUT STROBE_CHG M_P_ON STBY_TG REMOTE S_DT_IN S_DT_OUT S_CLK VF_CTL OSD_DATA OSD_CLK RXD TXD AUDIO_CS In/Out In/Out In In Out Out In In In In In Out In Out In Out Out Out Out Out Out Out In In Out Out Out Out Out In Out Out VF data load Feeld decision signal from DSP IC4301 Reset input from RESET IC6004 Strobe flash pulse output Video mute JLIP interrupt Vertical sync. Signal EIS data read-out timing EXT_DC detect (Battery mounting detect) Menu dial pulse Frame reference pulse 1 second interrupt (Clock) DSP write-in inhibition Jack select Jack select Chip select signal to OSD IC1002 Chip select signal to EEPROM IC1003 Power supply Not used Tally lamp Charge control Plug detect Remote pulse input Serial data input from MSD EEPROM RTC Serial data output to MSD TG CDS/AGC EEPROM DAC RTC Serial clock VF back light OSD data OSD clock RS232C data input RS232C data output Chip select to AUDIO IC2201 REF.

Table 2-21-1 SYSCON CPU (IC1001) pin functions-2/4

2-75

SYSCON CPU (IC1001) pin functions-3/4


Pin No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name RESERVE4 AFZ_DATA AFZ_CLK VDD VSS AVSS VRefL BATT_CHK KEY_A KEY_B ZOOM_SW IR_DA HALL_AD Z_PTR_AD F_PTR_AD TG_CS CAM_DAC_CS STROBE_AD KEY_C PHOTO_MODE MONI_RVS VRefH AVDD STO_FULL M16_RST BUZZER MENU_SET_SW RTC_CS DAC_CS LWE HWE RE In/Out Out Out In In In In In In In In Out Out In In In In Out Out Out In Out Out Out Out Not used Serial data output to AUDIO FZ_MDA Serial clock output to AUDIO FZ_MDA Power supply GND GND ADCGND Battery DC input Deck operation switch input Camera operation switch input Zoom switch input AWB IR sensor AD input Iris hall generator AD input ZOOM position sensor AD input FOCUS position sensor AD input Chip select to TG IC5002 Chip select to CDS/AGC IC5601 Plug detect input AV: H, HP: L Battery mount detect PHOTO MODE (without FRAME/with FRAME/PINUP/4MUL/9MUL/NAGA) LCD reverse switch input Power supply for ADC REG 3V Power supply Strobe full flash control (sensor stop) Full flash: H Reset signal to MSD IC1401 Buzzer sound output Menu set switch input Chip select to RTC IC1004 Chip select to DAC IC3503 Not used Write enable Read enable REF.

Table 2-21-1 SYSCON CPU (IC1001) pin functions-3/4

2-76

SYSCON CPU (IC1001) pin functions-4/4


Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VDD VSS DIAL_5S DIAL_PROGRE DIAL_MANU DIAL_AUTO DIAL_OFF DIAL_PLAY EJECT_SW CAS_SW MONITOR_SW VF_SW MENU_P_B DSP_RST_1 DSP_RST_2 DSP_RST_3 F/Z_RST M_U/D M_LR MO_BK_ON V_P_ON VDD(VPP) IRIS_O/C S_CLOSE S_OPEN SMUTE S_SPK_ON LCD_CS FADE_H AFADER A_MUTE Pin Name CALE In/Out Out In In In In In In In In In In In Out Out Out Out Out Out Out Out In/Out Out Out Out Out Out Out Out Out Address latch enable Power supply GND Dial 5second shot Progressive mode Dial manual Dial auto Dial OFF Dial PLAY Eject switch detect Cassette switch detect Monitor switch detect View finder switch detect Menu dial pulse Reset signal to DSP IC4301 (TRST) Reset signal to DSP IC4301 (RESET) Reset signal to DSP IC4301 (FSET) Reset signal to F/Z DRIVER IC4851 Monitor up/down, right/left and turn over select (3-state output) H: NORMAL, M: at PB (U/D), L: at EE (U/D+L/R) Back light control 3-state output H: Monitor + Back light, M: Monitor, L: VF ON Power supply IRIS OPEN/CLOSE Lens shutter close control Lens shutter open control Shutter sound mute Speaker ON Chip select to LCD EEPROM IC7302 fader last pulse AF fader: H Audio mute REF.

Table 2-21-1 SYSCON CPU (IC1001) pin functions-4/4

2-77

2.22

MDA (IC1601)

2.22.1 MDA (IC1601) pin assignment


D.WH D.VH D.UH DCC DCC1 DCC2 DCC3 D.COM D.WIN D.VIN D.UIN GND1 D.FGSOUT D.FGOUT D.FGD.FGPG+ D.PGD.PGOUT D.PGSOUT TEST2 GND1 D.U D.VM D.V D.RNF L.REF DW L.FWD GND2 L.GND NC UNREG L.REV C.U NC C.RNF C.V C.VM C.W C.UH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

TEST1 DETECT START D.OSC D.PCV D.PCI D.ECR D.EC NC GND2 D4 D3 D2 D1 D0 DOUT DIN CS CLK NC

C.VH C.WH C.HWC.HW+ C.HVC.HV+ C.HUC.HU+ C.FGSOUT C.FGOUT C.FGC.FG+ VCC C.VS C.PCV C.PCI C.ECR C.EC C.RCC C.BRK

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Fig. 2-22-1 MDA (IC1601) pin assignment

2-78

2.22.2 MDA (IC1601) block diagram

DRUM_PWR VCC UNREG DCC1 DCC2 DCC3 DCC

D.VM D.UH D. U D.VH D.V

UPPER/LOWER DIVISION

D.UIN

DRIVE SIGNAL LOGIC

D.VIN

D.WH D.W

D.WIN D.COM

IC1602
D.OSC

OSC

START TIMING

D.GND

DRUM.M

D.FG-

D.BRK D.EC D.ECR TORQUE CTL

BRAKE
D . P G-

DRUM_REF REG_5V

D . F G P G+ CURRENT FEED BACK D.PG.SM UNREG L.REF

DRUM_FG DRUM_PG

D.FGSOUT D.PGSOUT

L.FWD MDA_CS MDA_CLK MDA_IN MDA_OUT CS CLK DIN DOUT

SHIFT REGISTER & LATCH

C.FR C.MODE C.TL D.PG.SM D.BRK L.FIN L.RIN PW_SAVE

POWER SAVE

CTL LOGIC

L.REV L.GND

LOAD.M

PW_SAVE

L.FIN

L.RIN

D.FGD.FG+ CAP_PWR

REG_5V DRUM_FG

C.FR

DIRECTION UPPER/LOWER DIVISION

C.VM C.UH C. U C.VH C.V

HALL

C.HU+ C.HU-

DRIVE SIGNAL LOGIC

HALL

C.HV+ C.HV-

C.WH C.W

HALL

C.HW+ C.HW-

IC1603 CAP.M
C.RCC

RIPPLE CANCEL
C.EC C.VS C.MODE C.VM C.MODE

C.GND

CAP.M

CAP_REF REG_5V

C.EC C.ECR TORQUE CTL

CAP_ERR

DC/DC

C.TL C.BRK

CURRENT LIMIT BRAKE

CAP_BRK

Fig. 2-22-2 MDA (IC1601) block diagram


2-79

2.22.3 MDA (IC1601) pin functions-1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D.U D.VM D.V D.RNF L.REF D.W L.FWD GND2 L.GND NC UNREG L.REV C.U NC C.RNF C.V C.VM C.W C.CH C.VH C.WH C.HWC.HW+ C.HVC.HV+ C.HUC.HU+ C.FGSOUT C.FGOUT C.FGC.FG+ VCC C.VS C.PCV C.PCI C.ECR C.EC C.RCC C.BRK Pin Name GND1 In/Out Out In Out In Out Out Out Out Out In Out Out Out Out In In In In In In Out Out In In In In In In In In In Capstan FG schmitt output Capstan FG amp. Output Capstan FG input Power supply for BIP control section Capstan motor power control Terminal for prevent saturation (Upper side) Terminal for prevent saturation (Lower side) Capstan torque reference Capstan torque control Capstan ripple cancel Capstan brake :H Capstan motor hall signal input Capstan motor output (pre-drive) Sub GND Drum motor output Drum power Drum motor output Drum GND (current detect resistor) Loading motor output reference voltage Drum motor output Loading motor output Sub GND Loading motor GND Not used Power for load motor driver, drum BEMF comparater (REG 5V) Loading motor output Capstan motor output Not used Capstan GND (current detect resistor) Capstan motor output Drum power Capstan motor output REF.

Table 2-22-1 MDA (IC1601) pin functions-1/2

2-80

MDA (IC1601) pin functions-2/2


Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NC CLK CS DIN DOUT D0 D1 D2 D3 D4 GND2 NC D.EC D.ECR D.PCI D.PCV D.OSC START DETECT TEST1 TEST2 D.PGSOUT D.PGOUT D.PGD.FGPG+ D.FGD.FGOUT D.FGSOUT GND1 D.UIN D.VIN D.WIN D.COM DCC3 DCC2 DCC1 DCC D.UH D.VH D.WH Pin Name In/Out In In In Out In In In In In In In Out Out In In In Out Out In In In In Out Out Out Drum motor output (pre-drive) Drum current control Drum slope shape Drum motor common Drum BEMF comparater input GND Not used Drum torque control Drum torque reference Terminal for prevent saturation (Lower side) Terminal for prevent saturation (Upper side) Drum OSC Drum start mode time setting Drum detect mode time setting Not used Drum PG schmitt output Drum PG amp output Drum PG input Drum FG/PG common input Drum FG input Drum FG amp output Drum FG schmitt output GND Not used Not used Clock input Chip select input Serial data input Serial data output REF.

Table 2-22-1 MDA (IC1601) pin functions-2/2

2-81

2.23

ON SCREEN (OSD) (IC1002)

2.23.1 OSD (IC1002) pin assignment

SBT2 CS DATA PCL VDD CKO OSCO OSCI TEST VSS

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

HD VD NC NC NC NC VC2 BLK2 VC1 BLK1

Fig. 2-23-1 OSD (IC1002) pin assignment 2.23.2 OSD (IC1002) block diagram
9 DATA SBT2 CS 3 1 2
DATA INPUT SHIFT RESISTOR INSTRUCTION DECODER

TEST

CONTROL SIGNAL

VDD 10 G N D 4 PCL

BACKGROUND CONTROL DATA RESISTOR

CHARACTER DATA 8bit X 256 word

CKO

6
HORIZONTAL SIZE COUNTER HORIZONTAL SIZE COUNTER HORIZONTAL ADDRESS COUNTER

OSCO

OSC DISPLAY POSITION VERTICAL ADDRESS RESISTOR CHARACTER GENERATOR ROM 12 X 18bit X 256word VERTICAL SIZE COUNTER SYNC. PROTECT VERTICAL POSITION COUNTER VERTICAL ADDRESS COUNTER OUTPUT CONTORLLER

OSCI

H D 20

V D 19 11 12 13 14 BLK1 VC1 BLK2 VC2

Fig. 2-23-2 OSD (IC1002) block diagram


2-82

DISPLAY CONTROL DATA RESISTOR

DATA SELECTOR

CHARACTER SIZE RESISTOR

DISPLAY POSITION HORIZONTAL ADDRESS RESISTOR

WRITE-IN ADDRESS COUNTER

VIDEO RAM

INVERTER DATA 8bit X 256 word

OUTPUT DATA 1bit X 256 word

COLOR DATA 3bit X 256 word

BLINK DATA 1bit X 256 word

2.23.3 OSD (IC1002) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name STB2 CS DATA PCL VDD CKO OSCO OSCI TEST VSS BLK1 VC1 BLK2 VC2 NC NC NC NC VD HD In/Out In In In In Out Out In Out Out Out Out In In Vertical sync. signal input from DVIO IC3202 Horizontal sync. signal input from DVIO IC3202 Not used REF. Clock input from SYSCON CPU IC1001 (via the IC1008) Chip select input from SYSCON CPU IC1001 Serial data input from SYSCON CPU IC1001 Power on clear Power supply Clock out LC OSC I/O External clock input Test terminal GND Blanking signal output 1 Character signal output 1 Blanking signal output 2 Character signal output 2

Table 2-23-1 (IC1002) pin functions

2-83

2.24

FOCUS & ZOOM DRIVER (IC4851)

This IC drives and controls the FOCUS and ZOOM pulse motors. It is composed of the serial data decoder, drive pulse generator, and current setting and output driver. The serial data is input from the SYSCON CPU, after which first the initial data is sent when the power is turned on, and initial settings are performed. Next, standard data such as pulse width, number of pulses, rotation direction (CW/CCW), and current settings are synchronized with the VD, and input sequentially to drive the motor. 2.24.1 Focus & Zoom driver (IC4851) pin assignment and block diagram

PGND EXP3 EXTa Vm1 A1 FBa A2 Vm2 B1 FBb B2 EXTb VD LATCH SDATA SCLK OSCin OSCout RESET

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1/N OSC SERIAL DECODER PULSE GENERATER H BRIDGE a 2ch H BRIDGE b 2ch H BRIDGE a 1ch H BRIDGE b 1ch

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

EXP2 EXP1 EXP0 C1 FBc C2 Vm4 D1 FBd D2 Vm3 Vdd Vref FILd FILc FILb FILa Cosc LGND

C U R R E N T S E Ta EVR2 EVR1

C U R R E N T S E Tb EVR1 EVR2

Fig. 2-24-1 Focus & Zoom driver (IC4851) pin assignment and block diagram

2-84

2.24.2 Focus & Zoom driver (IC4851) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name LGND Cosc FILa FILb FILc FILd Vref Vdd Vm3 D2 FBd D1 Vm4 C2 FBc C1 EXP0 EXP1 EXP2 PGND EXP3 EXTa Vm1 A1 FBa A2 Vm2 B1 FBb B2 EXTb VD LATCH SDATA SCLK OSCin OSCout RESET In/Out In Out Out Out Out Out Out Out Out Out Out Out Out In In In In In In GND for power section Monitor (open drain) Logic monitor (not used) Power supply for output section Focus 1ch output Focus 1ch feed back Focus 1ch output Power supply for output section Focus 2ch output Focus 2ch feed back Focus 2ch output Logic monitor (not used) Vertical drive pulse Latch signal Serial data input from SYSCON IC1001 Serial clock input from SYSCON IC1001 Master clock Not used Reset input from SYSCON IC1001 Monitor (open drain) GND for logic section Chopping capacitor Focus 1ch filter capacitor Focus 2ch filter capacitor Zoom 1ch filter capacitor Zoom 2ch filter capacitor Reference voltage Power supply for logic section Power supply for output section Zoom 2ch output Zoom 2ch feed back Zoom 2ch output Power supply for output section Zoom 1ch output Zoom 1ch feed back Zoom 1ch output REF.

Table 2-24-1 Focus & Zoom driver (IC4851) pin functions

2-85

2.25 VIDEO OOUTPUT DRIVER (IC3701)


2.25.1 VIDEO OOUTPUT DRIVER (IC3701) pin assignment and block diagram

YIN1

ATT -12dB

LPF

20

CLAMPREF

GCACTL1

BPF

ATT -12dB

19

CIN1

YIN2

ATT -12dB GCA 6 12dB

PWR SAVE

18

GCACTL2

CLAMP

CLAMP

ATT -12dB

17

CIN2/INSEL

CHARA

5
LOGIC

CLAMP

16

VCC2

BLANK

6
COMP

15

VCC1

WIDE

7
6dB +12dB 75 W BUF

14

COUT

GND

8
220k W

13

SDCOUT

YOUT

9
75 W BUF +12dB

-6dB +18dB 75 W BUF

12

VOUT

YSAG

10

11

VSAG

Fig. 2-25-1 VIDEO OOUTPUT DRIVER (IC3701) pin assignment and block diagram

2-86

2.25.2 VIDEO OOUTPUT DRIVER (IC3701) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 YIN1 GCACTL1 YIN2 CLAMP CHA BLK WIDE GND YOUT YSAG VSAG VOUT SDCOUT COUT VCC1 VCC2 CIN2/INSEL GCACTL2 CIN1 CLAMP_REF Pin Name In/Out In In In In In Out In In Out Out Out In In In C signal output Power supply Power supply INSEL control signal (L: fixed) CGCA control from EVR DA CONV. IC3503 C signal input from DVIO IC3202 (via the Q3201) Reference clamp terminal REF. Y signal input 1 from DVIO IC3202 (via the Q3202/Q3204) Y GCA control from EVR DA CONV. IC3503 Y signal input 2 (Not used) Clamp terminal Character control Blank control Aspect ratio control signal input GND Y signal output Y signal feedback V signal feedback V signal output

Table 2-25-1 VIDEO OOUTPUT DRIVER (IC3701) pin functions

2-87

2.26 VF LCD DRIVER (IC7401)


This IC that integrates the RGB recorder, RGB driver, timing generator for driving LCD panel into one chip drives the VF color LCD. Although this IC is conformable to composite video signal, Y/C signal and Y/color difference signal as video inputs to it, Y/color difference signal is used as video input to this IC of the DVL7. The input system and TV system (NTSC/PAL) can be respectively switched by setup of serial data to be input to the pin 34 of this IC. 2.26.1 VF LCD DRIVER (IC7401) pin assignment and block diagram
H_FIL_OUT S_SEP_IN

VCO_ADJ

SYNC_IN

16

15

14

13

12

11

10

PD

VCO ADJ
PLL

H. FILTER SYNC SEP

VDD2 CLR HST HCK2 HCK1 HD FLD_OUT FLD_IN T1 VST1 VCK2 VCK1 EN VD1 VD2 VSS2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SERIAL BAS I/F
BUF PALSW

PWRST

EXT_G

EXT_R

EXT_B

VD_IN

GND1

TRAP

VDD1

VSS1

CKO

RPD

CKI

64 63

T0 PICT Y_IN GND3 F_ADJ C_IN ST_UP V_REG VXO_I VXO_O APC BK_LIM C_OUT R-Y_IN B-Y_IN VCC1

H GATE H SKEW DET


CLP BGP SBLK

V SEP

DL1

TRAP

CLAMP

62 61

HCNT H-PULSE

HAFC PLL-COUNTER & DECODER

D/A FILT ADJ PIC CONT ACC AMP EXT SW


g-2

60 59 58
REG

HD KILLER ACC DET CONTRAST MATRIX BRIGHT


BRT B-BRT

BPF

GAMMA
g-1

57 56

VWIN S/H VGATE VPAL


FRP
CONTRAST

COLOR HUE PS

COLOR CONT HUE APC VXO

55 54 53

LPF INT/EXT PAL SW COLOR HUE PAL ID

VTST

SUBBRIGHT
R-BRT

EXT COLOR & BALANCE CLAMP

52 51 50 49

POL SW WIDE

DEMOD

BUF

BUF

33

34

35

36

37

38

39

40

41

42

43

44

46

47 VCC_2

B_OUT

G_OUT

R_OUT

DATA

RGT

T2

T3

T4

45

Fig. 2-26-1 VF LCD DRIVER (IC7401) pin assignment and block diagram
2-88

SIG_CENTER

GND2

LOAD

SCLK

FB_G

FB_R

FB_B

48

2.26.2 VF LCD DRIVER (IC7401) pin functions -1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name PWRST VD_IN TRAP GND1 SYNC_IN H_FIL_OUT S_SEP_IN EXT_R EXT_G EXT_B VCO_ADJ RPD VSS1 CKI CKO VDD1 VDD2 CLR HST HCK2 HCK1 HD FLD_OUT FLD_IN T1 VST1 VCK2 VCK1 EN VD1 VD2 VSS2 In/Out In Out In In In In Out Out In Out Out Out Out Out Out Out In Out Out Out System reset Not used Not used GND for analog 4.5 V Image input for Sync. Separator Image output for sync. Input Sync. Separator circuit input External digital input R External digital input G External digital input B VCO adjustment output Phase comparator output GND for OSC cell digital 3V OSC cell input OSC cell output Power supply for OSC cell digital 3V Power supply for digital 3V CLR pulse output H start pulse output H clock pulse 2 output H clock pulse 1 output HD pulse output Field discrimination output Field discrimination input Not used V start pulse output V clock pulse 2 output Not used EN pulse output Not used Not used GND for digital 3V REF.

Table 2-26-1 VF LCD DRIVER (IC7401) pin functions -1/2

2-89

VF LCD DRIVER (IC7401) pin functions -2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name SCLK DATA LOAD T2 T3 T4 RGT GND2 B_OUT FB_B G_OUT FB_G R_OUT FB_R VCC2 SIG_CENTER VCC1 B-Y_IN R-Y_IN C_OUT BK_LIM APC VXO_O VXO_I V_REG ST_UP C_IN F_ADJ GND3 Y_IN PICT T0 In/Out In In In In Out Out Out Out Out Out In In In Out In Out Out Out In In Serial interface clock input Serial interface data input Serial interface load input Not used Not used Not used Scan direction select (H: Forward scan, L: Reverse scan) GND for analog 12V B output DC feedback capacitor for B signal G output DC feedback capacitor for G signal R output DC feedback capacitor for R signal Power supply for analog 12V RGB output adjust Power supply for analog 4.5V B-Y demodulation input (or B-Y color signal input) R-Y demodulation input (or R-Y color signal input) Chroma signal output Black peek limiter level adjust Not used Not used Not used Capacitor for voltage regulator Start up time constant setting Not used Resistor for internal filter adjustment GND for analog 4.5V Y signal input Frequency response adjustment of Y singnal Not used REF.

Table 2-26-1 VF LCD DRIVER (IC7401) pin functions -2/2

2-90

2.27

LCD MONITOR DRIVER (IC7301)

This IC that integrates the RGB recorder, RGB driver, timing generator for driving LCD panel into one chip drives the color LCD monitor. Although this IC is conformable to composite video signal, Y/C signal and Y/color difference signal as video input to it, Y/color difference signal is used as video input to this IC of the DVL7. The input system and TV system (NTSC/PAL) can be respectively switched by setup of serial data to be input to the pin 51 of this IC. 2.27.1 LCD MONITOR DRIVER (IC7301) pin assignment
YCLAMP QHSEL RMONI BMONI

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

APC VXOO VXOI CHROMA BCHCLAMP VCC1 VREF GCHCLAMP RCHCLAMP YS COM BCHDC VCC2 GCHDC RCHDC BOUT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

49

LOAD

R-YIN

TRAP

STUP

DATA

B-YIN

SCLK

HMC

GND

ACC

RST

YIN

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

COMPIN CSYNC HSYNC COMDC FOADJQH QH VSS AW VDD STV3 AFC CPV1 CPV2 STV1 STV2 VCC3

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 CPH2

DEV

CPH2

CPH1

OSDB

OSDG

Fig. 2-27-1 LCD MONITOR DRIVER (IC7301) pin assignment

GOUT

OSDR

ROUT

2-91

CPH1

VD

HD

STH3

STH2

STH1

GND

32

2.27.2 LCD MONITOR DRIVER (IC7301) block diagram

Fig. 2-27-2 LCD MONITOR DRIVER (IC7301) block diagram

2-92

2.27.3 LCD MONITOR DRIVER (IC7301) pin functions -1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 APC VXOO VXOI CHROMA BCHCLAMP VCC1 VREF GCHCLAMP RCHCLAMP YS COM BCHDC VCC2 GCHDC RCHDC BOUT GOUT ROUT GND OSDB OSDG OSDR VDD HD STH3 STH2 STH1 OEV CPH2 CPH1 CPH2 CPH1 Pin Name In/Out In Out Out Out Out In In In Out Out Out Out Out Out Out Out Not used Not used Not used Not used Bch clamp deteciton Power supply (4.8V) Reference voltage Gch clamp detection Rch clamp detection Character draw out pulse input Common reverse signal output DC feedback detection for Bch output Power supply (12.0V) DC feedback detection for Gch output DC feedback detection for Rch output Bch output Gch output Rch output GND1 Bch character signal input Gch character signal input Rch character signal input Not used Horizontal sync.signal output Not used Horizontal display start pulse 2 output Horizontal display start pulse 1 output Gate driver enable pulse output Horizontal shift clock 4 output Horizontal shift clock 3 output Horizontal shift clock 2 output Horizontal shift clock 1 output REF.

Table 2-27-1 LCD MONITOR DRIVER (IC7301) pin functions -1/2

2-93

LCD MONITOR DRIVER (IC7301) pin functions -2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name VCC3 STV2 STV1 CPV2 CPV1 AFC STV3 VDD AW VSS QH FOADJQH COMDC HSYNC CSYNC COMPIN LOAD SCLK DATA STUP RST HMC QHSEL RMONI GND2 BMONI YIN TRAP YCLAMP B-YIN R-YIN ACC In/Out Out Out Out Out Out In Out In In In In In In In In In In In VCC3 (3.3V) Vertical display start pulse 2 output Vertical display start pulse 1 output Not used Vertical shift clock 1 output ACF loop filter terminal Not used Power supply for clock (3.6V) Not used GND for clock (VSS) Array select signal VCO frequency adjust DAC output for common DC control Vertical sync.signal input Composite sync.signal output Sync.signal input Serial data write-in pulse input Serial data shift clock input Serial data input Control signal output inhibit control Power ON reset detection Display right/left inversion control signal input Display up/down inversion control signal input Not used GND2 Not used Luminance signal input Not used Clanp detection for Y system B-Y input Chroma/R-Y input Not used REF.

Table 2-27-1 LCD MONITOR DRIVER (IC7301) pin functions -2/2

2-94

2.28

AUDIO AMP (IC2201)

This IC serves as an analog signal input/output interface (Audio I/O) that the input amplifier, wind noise filter circuit to eliminate blast sound, ALC circuit, 30-kHz LPF, line amplifier, stereo headphone amplifier, BTL monaural speaker amplifier are integrated into one chip. Since this IC incorporates the serial control decoder circuit inside, internal operation mode of this IC is set up by serial data control. 2.28.1 AUDIO AMP (IC2201) pin assignment
SP OUT_2 SP OUT_1 HP OUT_R HP OUT _L MUTE OUT LINE OUT_R LINE OUT_L EXT MIC IN_R EXT MIC IN_L MIC SEL INT MIC IN_R INT MIC IN_L SP VCC SP ON/OFF SP GND BEEP IN MIX OUT MUTE GENC MUTE CTRL BIAS VREFC AGND1 RGND2 AVCC 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37

36 35 34 33 32 31 30 29 28 27 26 25

EXT NFB_L INT NFB_L EXT NFB_R INT NFB_R WINDC IN_L WINDC1_L WINDC2_L WINDC IN_R WINDC1_R WINDC2_R FADE CTRL FRDE DELAY

Fig. 2-28-1

CS CLK DATA IN DGND DVCC PB IN_R PB IN_L REC OUT_R REC OUT_L REC NFB_R REC NFB_L ALC FILTER

13 14 15 16 17 18 19 20 21 22 23 24

AUDIO AMP (IC2201) pin assignment

2-95

2.28.2 AUDIO AMP (IC2201) block diagram

Fig. 2-28-2

AUDIO AMP (IC2201) block diagram

2-96

2.28.3 AUDIO AMP (IC2201) pin functions


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name SP VCC SP ON/OFF SP GND BEEP IN MIX OUT MUTE GENC MUTE CTRL BIAS VREFC AGND1 AGND2 AVCC CS CLK DATA IN DGND DVCC PB IN_R PB IN_L REC OUT_R REC OUT_L REC NFB_R REC NFB_L ALC FILTER FADE DELAY FADE CTRL WIND C2_R WIND C1_R WIND CIN_R WINE C2_L WIND C1_L WIND CIN_L INT NFB_R EXT NFB_R INT NFB_L EXT NFB_L INT MIC IN_L INT MIC IN_R MIC SEL EXT MIC IN_L EXT MIC IN_R LINE OUT_L LINE OUT_R MUTE OUT HP OUT_L HP OUT_R SP OUT_L SP OUT_R In/Out In In Out In In In In In In Out Out In In In In In In In In In In In In Out Out Out Out Out Out Out REF. Speaker VCC Speaker ON/OFF control input Speaker GND Speaker input Head phone AMP L/R MIX output Delay for power on mute Mute control Bias Reference VCC/2 Analog GND1 Analog GND2 Analog VCC Serial control chip select input from SYSCON CPU IC1001 Serial control clock input from SYSCON CPU IC1001 Serial control data input from SYSCON CPU IC1001 GND for serial control VCC for serial control PB input (R ch) PB input (L ch) REC output (R ch) REC output (L ch) ALC AMP feedback (R ch) ALC AMP feedback (L ch) ALC filter Fade delay Fade control Wind cut filter 2 (R ch) Wind cut filter 1 (R ch) Wind cut filter in (R ch) Wind cut filter 2 (L ch) Wind cut filter 1 (L ch) Wind cut filter in (L ch) MIC AMP feedback (INT) MIC AMP feedback (EXT) MIC AMP feedback (INT) MIC AMP feedback (EXT) Internal MIC input (L ch) Internal MIC input (R ch) MIC select control input External MIC input (L ch) External MIC input (R ch) Line AMP output (L ch) Line AMP output (R ch) Mute output Head phone AMP output (L ch) Head phone AMP output (R ch) BTL speaker output (positive) BTL speaker output (negative)

Table 2-28-1 AUDIO AMP (IC2201) pin functions


2-97

2.29 16BIT A/D, D/A CONV. (IC2101)


The DAC internally incorporates the de-emphasis filter (50/15 m property) that is capable of dealing with three frequencies (32 kHz, 44.1 kHz and 48 kHz) by the IIR filter. The de-emphasis filter whose conformable frequency is selected by the DEM0 and DThis IC serves as an A-D/D-A converter for digital audio. The audio I/F format comprises of an ADC (16 bits from the highest place) and a DAC (16 bits from the lowest place). One of 256 fs, 384 fs and 512 fs can be selected as the master clock (MCK) by the CMODE terminal (MCK = 256/384/512 fs). Relation between the master clock to be input to the MCLK terminal and sampling rate is shown in Table 2-29-1.
MCLK fs CMODE="L" 256fs 32.0kHz 44.1kHz 48.0kHz 8.1920MHz 11.2896MHz 12.2880MHz CMODE="H" 384fs 12.2880MHz 16.9344MHz 18.4320MHz 512fs 16.3840MHz 22.5792MHz 24.5760MHz 2.048MHz 2.822MHz 3.072MHz 1.0240MHz 1.4112MHz 1.5360MHz 64fs SCLK 32fs

Table 2-29-1 Relation between clock and sampling rate When the CMODE terminal is set at "H" level, 384 fs or 512 fs can be input as a master clock. Input clock is automatically detected and it is internally divided into 256 fs and the rest. EM1 terminals has effect on input data. The de-emphasis filter is disabled when the DEM0 is set at 1 and DEM1 is set at 0 (DEM0 = 1, DEM1 = 0).
DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz

Table 2-29-2 De-emphasis filter control

2-98

2.29.1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram
CMODE AOUTR AOUTL VCOM DGND
13 12

AGND

DEM0

DEM1

SDTI
15
8x Interpolator 8X Interpolator

24

23

22

21

20

19

18

17

16

14

Clock Divider

Common Voltage

LPF

DS Modulator DS Modulator

LPF

Decimation Filter DS Modulator DS Modulator

Decimation Filter

Serial I/O Interface

10

11

VCMR

VCML

MCLK

VRDA

VRAD

LRCK

SCLK

VD

VA

VB

PWAD

Fig. 2-29-1 16BIT A/D, D/A CONV. (IC2101) pin assignment and block diagram 2.29.2 16BIT A/D, D/A CONV. (IC2101) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VRDA VRAD AINR VCMR VCML AINL PWAD PWDA MCLK LRCK SCLK SDTO DGND VD SDTI CMODE DEM1 DEM0 AOUTL AOUTR VCOM AGND VB VA In/Out In In In Out Out In In In In In In Out In In In In Out Out Out REF. Reference voltage input for DAC, VA Refernce voltage input for ADC, VA Rch analog input Rch common voltage output Lch common voltage output Lch analog input ADC power down mode (L: Power down) DAC poewr down mode (L: Power down) Master clock input I/O channel clock input Audio serial data clock Audio serial data output GND (for digital) Power supply (for digital) Audio serial data input Master clock select (H: 384fs or 512fs , L: 256fs) Deemphasis frequency select Deemhpasis frequency select Lch analog output Rch analog output Common voltage output GND (for analog) Sub straight Power supply (for analog)

Table 2-29-3 16BIT A/D, D/A CONV. (IC2101) pin functions


2-99

PWDA

SDTO

AINR

AINL

2.30

REGULATOR CTL (IC6101)

This IC serves as a six-channel switching regulator controller, and it internally incorporates the triangular wave generator, reference voltage regulator, error amplifier, PWM comparator, totem pole driver, various protection circuits into one chip. For channel control, all channels are turned off if the STB terminal is set at "L" level, and only the channel 3 is turned off if the STB3 terminal is set at "L" level. 2.30.1 REGULATOR CTL (IC6101) pin assignment
GND456 GND123

CAPH4

CAPH3

GATE4

CAPL4

CAPL3

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

CAPL5 CAPH5 BIAS5 OUT6 CAPL6 CAPH6 BIAS6 DTC2 SCP6 NON6 INV6 FB6 COMP SCP5 NON5 INV5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

CAPL2

BIAS4

BIAS3

Vcc56

Vcc24

OUT5

OUT4

OUT3

OUT2

CAPH2 BIAS2 OUT1 CAPL1 CAPH1 Vcc13 BIAS1 SCP1 INV1 FB1 GATE1 INV2 FB2 SCP2 SCP3 INV3

SCP4

INV4

FB5

FB4

SCP

DUTY

VREF

Fig. 2-30-1 REGULATOR CTL (IC6101) pin assignment

2-100

SOFT

DTC3

STB3

GND

STB

FB3

RT

CT

Vcc

2.30.2 REGULATOR CTL (IC6101) pin functions -1/2


Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name CAPL5 CAPH5 BIAS5 OUT6 CAPL6 CAPH6 BIAS6 DTC2 SCP6 NON6 INV6 FB6 COMP SCP5 NON5 INV5 FB5 SCP4 INV4 FB4 RT CT SCP DUTY GND SOFT VREF VCC STB3 STB DTC3 FB3 In/Out Out In In In Out In In In Out In In Out In In Out REF. Capacitor for off transistor current setting: L (CH5) Capacitor for off transistor current setting: H (CH5) Output bias setting (CH5) Power transistor base (CH6) Capacitor for off transistor current setting: L (CH6) Capacitor for off transistor current setting: H (CH6) Output bias setting (CH6) Dead time control (CH2) Output voltage monitor for CH6 protect opration Noninverted input for error amp. (CH6) Inverted input for error amp. (CH6) Error amp. Output (CH6) Not used Output voltage monitor for CH5 protect operation Noninverted input for error amp. (CH5) Inverted input for error amp. (CH5) Error amp. Output (CH5) Output voltage monitor for CH4 protect operation Inverted input for error amp. (CH4) Error amp. Output (CH4) Triangle waveform frequency timing resistor Triangle waveform frequency timing capacitor Capacitor for timer latch delay setting Not used GND Capacitor for soft start setting Reference voltage output Power supply CH3 on/off switch All channel on/off switch Dead time control (CH3) Error amp. output (CH3)

Table 2-30-1 REGULATOR CTL (IC6101) pin functions -1/2

2-101

REGULATOR CTL (IC6101) pin functions -2/2


Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name INV3 SCP3 SCP2 FB2 INV2 GATE1 FB1 INV1 SCP1 BIAS1 VCC13 CAPH1 CAPL1 OUT1 BIAS2 CAPH2 CAPL2 OUT2 VCC24 BIAS3 GND123 CAPH3 CAPL3 OUT3 OUT4 CAPL4 CAPH4 GATE4 GND456 BIAS4 VCC56 OUT5 In/Out In In In Out In Out In In Out Out Out Out Out Out Inverted input for error amp. (CH3) Output voltage monitor for CH3 protect operation Output voltage monitor for CH2 protect operation Error amp. output (CH2) Inverted input for error amp. (CH2) Not used Error amp. Output (CH1) Inverted input for error amp. (CH1) Output voltage monitor for CH1 protect operation Output bias setting (CH1) Power supply for CH1, 3 Capacitor for off transistor current setting: H (CH1) Capacitor for off transistor current setting: L (CH1) Power transistor base (CH1) Output bias setting (CH2) Capacitor for off transistor current setting: H (CH2) Capacitor for off transistor current setting: L (CH2) Power transistor base (CH2) Power supply for CH2,4 Output bias setting (CH3) GND for CH1, 2, 3 Capacitor for off transistor current setting: H (CH3) Capacitor for off transistor current setting: L (CH3) Power transistor base (CH3) Power transistor base (CH4) Capacitor for off transistor current setting: L (CH4) Capacitor for off transistor current setting: H (CH4) Not used GND for CH4, 5, 6 Output bias setting (CH4) Power supply for CH5, 6 Power transistor base (CH5) REF.

Table 2-30-1 REGULATOR CTL (IC6101) pin functions -2/2

2-102

VICTOR COMPANY OF JAPAN, LIMITED

Printed in Japan 9912 (IY)

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