JVC Gr-dvm5 Technical Guide

VIDEO TECHNICAL GUIDE
DIGITAL VIDEO MOVIE
GR-DVM5 NTSC/PAL
COPYRIGHT 1999 VICTOR COMPANY OF JAPAN, LTD.
March 1999
INDEX
SECTION 1 OUTLINE OF THE PRODUCT 1.1 DIFFERING POINTS BETWEEN MODELS ................................................................................. 1-1 1.1.1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3) ........................................................ 1-1 SECTION 2 OPERATION OF MECHANISM 2.1 OPERATION OF LOADING CONTROL ....................................................................................... 2-1 2.1.1 Motor bracket assembly and Rotary encoder operation ......................................................... 2-3 2.1.2 Tension arm and pad arm assembly operation....................................................................... 2-4 2.1.3 Slide deck assembly and loading brake assembly operation.................................................. 2-4 2.1.4 Rail assembly and slant pole arm assembly operation........................................................... 2-4 2.1.5 Sub brake assembly and release guide operation.................................................................. 2-4 2.1.6 Charge arm assembly and pinch roller arm assembly operation ............................................ 2-5 2.2 OPERATION OF MECHANISM.................................................................................................... 2-6 2.2.1 Outline ................................................................................................................................... 2-6 2.2.2 Mechanism modes................................................................................................................. 2-6 SECTION 3 CIRCUIT DESCRIPTION 3.1 DESCRIPTION OF CCD OPERATIONS ...................................................................................... 3-1 3.1.1 CCD pin assignment .............................................................................................................. 3-3 3.1.2 CCD pin functions.................................................................................................................. 3-3 3.1.3 Electrical Image Stabilizer...................................................................................................... 3-4 3.2 V. DRIVER ................................................................................................................................... 3-5 3.2.1 V. DRIVER (IC5501) pin functions.......................................................................................... 3-5 3.3 T. G .............................................................................................................................................. 3-6 3.3.1 T. G (IC5502) pin functions .................................................................................................... 3-6 3.4 CDS AGC..................................................................................................................................... 3-7 3.4.1 CDS AGC (IC5601) pin assignment....................................................................................... 3-7 3.4.2 CDS AGC (IC5601) pin functions........................................................................................... 3-8 3.5 ADC FUNCTION .......................................................................................................................... 3-9 3.5.1 ADC (IC4201) pin functions ................................................................................................... 3-9 3.6 Focus & zoom driver .................................................................................................................. 3-10 3.6.1 Focus & Zoom driver (IC4851) pin assignment .................................................................... 3-10 3.6.1 Focus & Zoom driver (IC4851) pin functions ........................................................................ 3-11 3.7 YMCA & SSG............................................................................................................................. 3-12 3.7.1 YMCA & SSG (IC4301) pin assignment ............................................................................... 3-12 3.7.2 YMCA & SSG (IC4301) pin functions................................................................................... 3-13 3.8 FM.............................................................................................................................................. 3-17 3.8.1 FM (IC4302) pin functions.................................................................................................... 3-17 3.9 DVIO FUNCTION ....................................................................................................................... 3-17 3.9.1 DVIO (IC3202) pin assignment ............................................................................................ 3-17 3.9.2 DVIO (IC3202) pin functions ................................................................................................ 3-19 3.9.3 PLL circuit description.......................................................................................................... 3-23
INDEX-1
3.10 COMPRESS/AUDIO/SHUFFLE (CAS) FUNCTION.................................................................. 3-24 3.10.1 CAS IC3001 pin assignment .............................................................................................. 3-24 3.10.2 CAS IC3001 pin functions .................................................................................................. 3-25 3.11 ECC/DCI/ATF (EDA) FUNCTION ............................................................................................. 3-28 3.11.1 EDA IC3003 pin assignment .............................................................................................. 3-28 3.11.2 EDA (IC3003) pin functions................................................................................................ 3-29 3.12 PB EQ FUNCTION................................................................................................................... 3-33 3.12.1 PB EQ (IC3501) pin assignment ........................................................................................ 3-33 3.12.2 PB EQ (IC3501) pin functions ............................................................................................ 3-34 3.12.3 PB EQ circuit ..................................................................................................................... 3-36 3.13 PRE/REC FUNCTION .............................................................................................................. 3-37 3.13.1 PRE/REC (IC3502) pin assignment ................................................................................... 3-37 3.13.2 PRE/REC (IC3502) pin functions ....................................................................................... 3-38 3.14 Digital interface FUNCTION ..................................................................................................... 3-40 3.14.1 Digital IF (IC8001) pin assignment ..................................................................................... 3-40 3.14.2 Digital IF (IC8001) pin functions ......................................................................................... 3-41 3.15 monitor function........................................................................................................................ 3-44 3.15.1 LCD driver (IC7201) pin assignment .................................................................................. 3-47 3.15.2 LCD driver (IC7201) pin functions ...................................................................................... 3-48 3.15.3 LCD SUBTG (IC7203) pin assignment............................................................................... 3-50 3.15.4 LCD SUBTG (IC7203) pin functions................................................................................... 3-50 3.16 MIC CIRCUIT ........................................................................................................................... 3-51 3.17 SYSCON CPU ......................................................................................................................... 3-52 3.17.1 SYSCON CPU (IC1001) pin functions................................................................................ 3-52 3.18 MSD CPU................................................................................................................................. 3-56 3.18.1 MSD CPU (IC1401) pin functions....................................................................................... 3-56 3.19 MDA FUNCTION...................................................................................................................... 3-60 3.19.1 MDA (IC1601) pin assignment ........................................................................................... 3-60 3.19.2 MDA (IC1601) pin functions ............................................................................................... 3-61 SECTION 4 ERROR RATE ADJUSTMENT PB EQ (Error Rate) Adjustment......................................................................................................... 4-1
1-2
SECTION 1 OUTLINE OF THE PRODUCT

1.1 DIFFERING POINTS BETWEEN MODELS
1.1.1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-1/4
Model Function Battery GR-DV1 Single cell BN-V712 (3.6V, 1250 mAh) When charging two batteries, charging of both is completed at the same time Charging one battery: 140 min. Charging two batteries: 210 min. Continuous shooting time: 30 min. GR-DVM1 2 cells BN-V812 (2.2V, 1250 mAh) When charging two batteries continuously, they are charged in the order attached Charging one battery: 100 min. Charging two batteries: 200 min. Continuous shooting time: 60 min. GR-DVX 2 cells BN-V907 (7.2V, 750 mAh) When charging two batteries continuously, they are charged in the order attached Charging one battery: 100 min. Charging two batteries: 200 min. Continuous shooting time: 45 min. (When VF is used) GR-DVL9000 2 cells BN-V814 (7.2V, 1400 mAh) (BN-V812 available) When charging two batteries continuously, they are charged in the order attached Charging one battery: 110 min. Charging two batteries: 220 min. Continuous shooting time: 100 min. GR-DVM5/DV3 2 cells BN-V607 (7.2V, 770 mAh) (BN-V615 available) At AA-V68 used: When charging two batteries continuously, they are charged in the order attached Charging one battery: 90 min. (BN-V607) / 180 min. (BN-V615) Charging two batteries: 180 min. (BN-V607) / 360 min. (BN-V615) At AA-V60 used: To charge the battery pack installed in the camcorder, be sure to switch off the camcorder first. If two battery packs are attached to the AC charger station (one attached to the AC charger station and one in the camcorder attached to it), they will be charged in the order that they were attached. The charging time for two BN-V607 battery packs is approx. 190 min.
Continuous shooting time: 40 min. (When LCD is used)
(When VF is used) Continuous shooting time: 80 min. (When LCD is used)
Charging of Battery Yes in the unit by docking station Weight main unit: Approx. 450g during shooting: Approx. 520g (Including battery BNV712, tape M-DV30ME, hand strap)
No
No (Can be performed by GV-DS2) main unit: Approx. 500g during shooting: Approx. 590g (Including battery BNV907, tape M-DV30ME)
No docking station
main unit: Approx. 520g during shooting: Approx. 730g (Including battery BNV812, tape M-DV30ME, hand strap)
main unit: Approx. 670g during shooting: Approx. 780g (Including battery BNV814, tape M-DV30ME)
main unit: Approx. 440g (GR-DVM5) / 630g (GR-DV3) during shooting: Approx. 530g (GR-DVM5) / 510g (GR-DV3) (Including battery BNV607, tape M-DV30ME)
Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-1/4
1-1
Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-2/4

Model Function Viewfinder GR-DV1 Yes 0.55" Horizontal resolution 260 lines High temperature polycrystal silicon transistor Yes (Finder operation linked) No GR-DVM1 GR-DVX Yes 0.55" Horizontal resolution: 260 lines High temperature polycrystal silicon transistor Yes (Finder/LCD linked) GR-DVL9000 GR-DVM5/DV3
Lens cover
No (With lens protection glass)
Yes Motor-driven (Power SW/Finder/LCD linked) Yes (Priority to Viewfinder) 4" Horizontal resolution: 240 lines Amorphous silicon transistor Yes (Priority to Viewfinder) 2.5" Horizontal resolution: 350 lines Low temperature polycrystal silicon transistor
LCD monitor
None
Yes The image can be turned off 2.5" Horizontal resolution: 400 lines Low temperature polycrystal silicon transistor
Yes (Priority to Viewfinder) The image can not be turned off 2.5" Horizontal resolution: 400 lines Low temperature polycrystal silicon transistor
Image device
1/3" 570k (670k) pixels Effective area 330k (420k) pixels 2-line accumulation transfer
1/3" 380k (450k) pixels Effective aria 360k (420k) pixels Progressive scan CCD JVC original Complementary Color filter Yes Magnification method 4.7 lux (shutter 1/60 second) F1.2 f=5.0 to 50 mm Optical zoom: 10X Electronic zoom: 4X/20X(10X) Total zoom: 200X(100X)
1/4" 460k (540k) pixels Effective aria 290k (350k) pixels
Progressive scanning Electric Image Stabilizer Sensitivity
No Excess pixel method 7 lux (Shutter 1/30 seconds) F1.6 f=4.5 to 45 mm
No 6 lux (GR-DVM5) 7lux (GR-DV3) (shutter 1/60 second) F1.8 f=3.6 to 36 mm Optical zoom: 10X Electronic zoom: 4X/10X Total zoom: 100X
Lens specification Zoom Ratio
Optical zoom: 10x Electronic zoom: 2x/10x Total zoom: 100x
1-2

Model Function Snapshot GR-DV1 Only frame GR-DVM1 Can select whether to set the frame or not The shutter sound can be turned on and off using the "Buzzer/tarry" of the system menu (Forcibly recorded on the tape) Only by the remote control unit Yes GR-DVX GR-DVL9000 6 mode With frame, no-frame, negative/positive (During recording) Pin-up, Pin-up 4division Pin-up 9-division GR-DVM5/DV3 5 mode With frame, no-frame, Pin-up, Pin-up 4-division Pin-up 9-division
Snapshot in Playback Zoom in Playback Auto flash LP mode
No
Yes (Excluding negative-positive) (Maximum 10 times) No
(Maximum 10 times)
By main unit/remote control unit No No
Yes (After LP recording, Audio dubbing and Insert editing cannot be performed)
Audio
2 ch (48k)/4 ch (32k) 2 ch (48k)/4 ch (32k) initial setting 48 kHz initial setting 32 kHz (After recording editing cannot be performed for 48 kHz recording) Yes No In the case of shooting from the unrecorded portion of the tape, the time code is recorded from 00:00:00
2 ch (48k)/4 ch (32k) initial setting 48 kHz (After recording editing cannot be performed for 48 kHz recording) No
Snapshot search
No Docking station is not required
Record end search Yes Audio dubbing and Docking station is Insert editing required Time code In the case of shooting from an unrecorded portion of the tape, the approximate time code is calculated and recorded (changed to DVM1/DVX specifications from halfway)
1-3

Model Function Headphone terminal No AV-integrated output terminal S output terminal Yes No (only Docking station) No (only Docking station) No (only Docking station) No No GR-DV1 Yes No (Audio, video separately) GR-DVM1 GR-DVX Yes (Shared with AV terminal) Yes (Shared with headphone terminal) JLIP video capture docking station GV-DS2 JLIP video capture JLIP video producer Yes main unit (GRDVX) only Provided for GV-DS2 (When using GV-DS2, the GR-DVX lightreceiving sensor becomes ineffective) Yes GR-DVL9000 No (only AC charging station) No (only AC charging station) No (only AC charging station) No (Digital In/Out) JLIP video capture box GV-CB1 JLIP video producer HS-V5KIT GR-DVM5/DV3
JLIP terminal Editing terminal Still image output terminal DV output terminal JLIP related
Yes (Shared with still image output terminal) Yes Yes (Shared with JLIP terminal) Yes JLIP video capture kit HS-V3KIT JLIP video producer HS-V5KIT Yes
Software JLIP ID number Remote control sensor
JLIP video capture box JLIP video capture docking station GV-CB1 GV-DS1 JLIP video capture JLIP video capture JLIP movie player JLIP movie player 7 No (Docking station only) 6
Power ON/OFF button in Remote control unit
Yes
No No (However, it can be turned OFF only by the remote control unit of GR-DV1) Equipped with secondary battery (Life about 3 months) soldering Unit has a Reset button
System backup button battery
Primary battery (life about 1 year) can be attached and detached Resetting is performed by removing the battery
1-4
SECTION 2 OPERATION OF MECHANISM

2.1 OPERATION OF LOADING CONTROL
For flow chart of main parts, refer to Fig. 2-1-1 with the numbers in square brackets following the part name. For further details, refer to the disassembled view, mechanism parts list, electrical parts list in the service manual.
[Refer to 2.1.1] SYSCON CPU (IC1001)
MDA (IC1601)
[M3-413]
MOTOR BRACKET ASSY (MODE CONTROL MOTOR)

[M3-415]
WORM WHEEL
[M3-417]
ROTARY ENCODER
[M3-427]
CONNECT GEAR
[M3-401]
MAIN DECK (RELAY GEAR)

[M3-422] [M3-429]
MAIN CAM [Refer to 2.1.2]

[M3-425]
SUB CAM
[Refer to 2.1.3]
[M3-426]
TC LEVER ASSY
[M3-444]
SLIDE LEVER ASSY
TENSION ARM
[M3-446]
[M3-442]
SLIDE GUIDE PLATE

[M3-458]
[Refer to 2.1.6]
[M3-435] [M3-433]
PAD ARM ASSY
LOADING BRAKE ASSY
[M3-472]
SLIDE DECK ASSY
BRAKE CONTROL ASSY

[M3-456]
CHARGE ARM ASSY
[Refer to 2.1.4]
[M3-410] [M3-441] [M3-405]
CONTROL PLATE ASSY GUIDE ARM ASSY

[M3-410]
CATCHER (T) ASSY
RAIL ASSY
[M3-431]
[M3-184]
PINCH ROLLER ARM ASSY [Refer to 2.1.5]
CASSETTE HOUSING ASSY (RELEASE LEVER)
CATCHER (T) ASSY

[M3-402]
SLANT POLE ARM ASSY

[M3-404]
[M3-458]
[M3-460]
RELEASE GUIDE
SUB BRAKE ASSY
CLEANER ARM ASSY
Fig. 2-1-1 Loading operation chart

2-1
2.1.1 Motor bracket assembly and Rotary encoder operation 1. Motor bracket assembly [M3-413] The motor bracket assembly includes the Mode control motor and worm gear. The Mode control motor drives the rotary encoder via the worm wheel. The mode control motor performs loading and unloading operations and selects the mechanism mode. Motor on/off and forward/reverse are controlled by the syscon CPU (IC1001). The mode control motor rotation is transmitted via the worm wheel to the rotary encoder of the switch board for detecting and changing the mechanism mode. 2. Rotary encoder [M3-417] The rotary encoder is composed of the switches and a gear. The switch on/off states are detected from the gear rotation. The switch on/off states correspond to each mechanism mode and the data are sent to the syscon CPU (IC1001), The CPU determines the mechanism states from these data and controls the mode control, drum and capstan motors. The mode control motor drive force is transmitted by the worm wheel to the rotary encoder, which controls the main cam and sub cam. 3. Main cam [M3-422] The main cam control operations of the supply and take-up loading mechanism and slide deck assembly. Refer to Fig. 2-1-2. There are two control grooves on the main cam. One functions to control the tension arm and pad arm assembly through the TC lever assembly, and the other functions to control the loading brake assembly and slide guide plate through the slide lever assembly.
To control the TC lever assembly [M3-433]
To control the Slide lever assembly [M3-426]
Fig. 2-1-2 Main cam 4. Sub cam The sub cam control operations of the take-up mechanism, cassette housing assembly and sub brake assembly. Refer to Fig. 2-1-3. There are two control grooves on the sub cam . One functions to control the control plate assembly through the brake control assembly, and the other functions to control the pinch roller arm assembly and cassette housing assembly through the charge arm assembly.
To control the charge arm assembly [M3-433] To control the brake control assembly [M3-435]
Fig. 2-1-3 Sub cam

2-2
2.1.2 Tension arm and pad arm assembly operation The TC lever assembly drives the tension arm and pad arm assembly being controlled by the control groove on the main cam. 1. Tension arm [M3-444] With operation of the main cam, the tension arm functions to draw out the tape from the supply side as well as to drive the pad arm assembly being controlled by the control pin on the tension arm. 2. Pad arm assembly [M3-446] With operation of the tension arm, the pad arm assembly applies the brake on the supply reel disk to prevent the tape from slackening in the stand-by status (STOP mode) after the tape was pulled out of the cassette. 2.1.3 Slide deck assembly and loading brake assembly operation The slide lever assembly drives the slide deck assembly through the slide guide plate and loading brake assembly being controlled by the control groove on the main cam. 1. Loading brake assembly [M3-458] With operation of the slide lever assembly, the loading brake assembly applies the brake on the supply reel disk to prevent the tape from slacking in the loading and unloading mode. 2. Slide deck assembly [M3-472] The slide deck assembly slides for inserting and taking out the digital video cassette tape according to operation of the slide lever assembly. The slide deck assembly drives the guide arm assembly and the rail assembly being controlled by the control groove on the main cam via the slide lever assembly. 2.1.4 Rail assembly and slant pole arm assembly operation 1. Rail assembly [M3-405] With operation of the slide deck assembly, the rail assembly (supply/take-up guide rail) controls loading/unloading the cassette tape. 2. Slant pole arm assembly [M3-402] The slide deck assembly drives the slant pole assembly through the guide arm assembly and catcher (T) assembly. With operation of the slide deck assembly, the slant pole arm assembly functions to draw out the tape from take-up side as well as to drive the cleaner arm assembly. 2.1.5 Sub brake assembly and release guide operation The brake control assembly, which is controlled by the control groove on the sub cam, functions to drive the sub brake assembly (take-up side) and release guide through the control plate assembly. 1. Sub brake assembly [M3-460] With operation of the brake control assembly, the sub brake assembly applies the brake on the take-up reel disk to prevent the tape from slackening in the stand-by status (STOP mode) after the tape was pulled out of the cassette. 2. Release guide [M3-458] In the EJECT mode, the release guide is moved by the control plate assembly so that the digital video cassette tape is correctly sent in place. The release guide also serves to control reel to cassette locking.
2-3
2.1.6 Charge arm assembly and pinch roller arm assembly operation 1. Charge arm assembly [M3-433] Being controlled by the control groove on the sub cam, the charge arm assembly drives the pinch roller arm assembly and release lever of cassette housing assembly. The charge arm assembly functions to unlock and eject the cassette housing assembly. However, the cassette housing assembly cannot be ejected without slide operation of the slide deck assembly because the cassette housing assembly is otherwise locked by it. 2. Pinch roller arm assembly [M3-431] With operation of the charge arm assembly, the pinch roller arm assembly presses the tape to the capstan shaft.
2-4
2.2 OPERATION OF MECHANISM

2.2.1 Outline Mechanism mode is switched by rotation of the mode control motor. Mechanism mode is switched and controlled by the syscon CPU (IC1001) that detects the mechanism status with 3-bit signals supplied from the rotary encoder. This model has six mechanism modes. 2.2.2 Mechanism modes The following roughly explains the six mechanism modes. For details of the respective modes and operation timing of main mechanism parts, refer to the mechanism modes chart (Fig. 2-2-1). 1. EJECT mode (Assembling mode) This mode is used for ejecting the cassette tape and for assembling the mechanism. When disassembling/re-assembling the mechanism, enter the mechanism into this mode before starting the job. Since the mechanism is generally set in the STOP mode, make sure to refer to the service manual for shifting the mechanism mode from the STOP mode to the EJECT mode. Namely, set the mechanism to the EJECT mode while applying DC 3V to the motor similarly according to the tape taking-out method in Section 1 "TO TAKE OUT CASSETTE TAPE" of service manual. 2. STD-BY mode The mechanism automatically enters the C-IN mode after it completes the eject operation, and it continues to stand by in this mode until a digital video cassette tape is inserted or the cassette housing is closed. 3. SHORT FF mode The Short FF mode operation is the tape transported in the forward direction to take-up tape slack during shift to STOP mode from C-IN mode. 4. STOP mode The STOP mode is the reference position of the mechanism. With insertion of a digital video cassette tape into the cassette housing, the mechanism performs the full loading operation and then automatically enters the STOP mode again. Therefore, mode shift of the mechanism to another mode is carried out in a short time. The mechanism enters the STOP mode in the following conditions. 1) When the set is turned on or off (power on/off). 2) When a digital video cassette tape is inserted, the mechanism automatically enters the STOP mode from the EJECT mode. 3) When the STOP button is pressed in the PLAY, REV, FF/REW mode. 4) When the tape reaches the end in the FF/REW mode. 5. PLAY mode When the PLAY button is pressed, the mechanism is shifted to this mode from the STOP mode. 6. REV mode When the FF/REV button is pressed, the mechanism enters this mode.
2-5
Mechanism mode timing chart

Parts Mode
EJECT
0 0 0 HIGH
C IN
31.7 30 33 45.6 49.5 43.1 46.8 47.4 51.5
SHORT FF
74.04 70 77 129.5 122.5 134.7 156.6 148.1 162.9
STOP
169.2 160 176
REV
211.5 200 220
PLAY
280.3 265 291.5
Main Cam Sub Cam Encoder Cam SW1

LOW HIGH
Cam SW2
LOW HIGH
Cam SW3
LOW
<Slide Deck>
SLIDE END
SLIDE START
Slide Lever Assy
SUP/TU Pole Base (Rail Assy) Eject Lever (Change Arm Assy)
Loading Brake Assy
Release Guide
Sub Brake Assy (TU Brake)
Pinch Roller Arm Assy
Tension Arm
Pad Arm Assy (SUP Brake)
Main Cam Sub Cam Encoder
47.2 52.0
155.5
265.0
44.6 49.2
147.0
250.5
49.1 54.1
161.7
275.6
Fig. 2-2-1 Mechanism mode timing chart

2-6
SECTION 3 CIRCUIT DESCRIPTION

3.1 DESCRIPTION OF CCD OPERATIONS
Transfer system Optical size Total pixels Effective pixels Horizontal drive frequency Chip size Unit cell size Optical black Dummy bits Color filter Interline transfer CCD image sensor 1/4 inch size format 766 H 596 V approx. 460k pixels (* for PAL model :766H 711V approx. 540k pixels) 724 H 582 V approx. 420k pixels (* for PAL model :724H 697V approx. 500k pixels) 13.5MHz drive (DV standard SD mode ) 4.60mm (H) 3.97mm (V) 5.15m (H) 4.70m (V) (* for PAL model :5.15m (H) 3.95m (V)) Horizontal (H) Front 2 / Back 40 Vertical (V) Front 12 / Back 2 Horizontal 20 Vertical 1 (only even field) Ye, Cy, Mg, G Complementary color filter
1pin 2
12 2 8pin H 40
Fig. 3-1-1 Optical black diagram
3-1
3.1.1 CCD pin assignment

VOUT GND V1 V2 V3 V4
1
Ye G Ye Mg Ye G
VL
5
Cy Mg Cy G Cy Mg
Ye G Ye Mg Ye G
Cy Mg Cy G Cy Mg
Vertical-Register
Horizontal-Register
10
11
12
13
14
Photo Sensor
GND
CSUB
RG
VDD
H1
SUB
Fig. 3-1-2 CCD pin location 3.1.2 CCD pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vf 4 Vf 3 Vf 2 Vf 1 VL GND VOUT VDD GND Label In/Out In In In In Out In In In In Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Protect transistor bias GND Video signal output Power supply GND Substrate clock Substrate bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Description
f SUB CSUB f RG Hf 1 Hf 2
Table 3-1-1 pin functions

3-2
H2
3.1.3 Electrical Image Stabilizer In this unit, the extra area in the vertical direction is used as the handshake correction area by using the PAL CCD (effective pixels 724H x 582V) for the NTSC format. Handshake correction in the vertical direction is carried out by the extra pixel framing method in which the position for the valid area of the 494 pixels is corrected based on movement vector detection from the 582-pixel area. However there is no extra pixel area in the horizontal direction, and reproducing images using the NTSC format will also result in oblong pictures. In this case, electronic zooming is carried out in which 611 pixels in the horizontal direction are enlarged 1.2 times to 720 pixels with interpolation pixels. By controlling the reading position of the line memory and changing the framing position of the 611 pixels, handshake in the horizontal direction is corrected. The camera images of this unit are always electronic-zoomed in the horizontal direction by 1.2 times (even when handshake correction is OFF), therefore the angle of view cannot be changed by turning handshake correction ON or OFF. The actual resolution (number of pixels) is however 611H x 480V, approx. 290000 pixels. (*For PAL models, a CCD called special PAL (effective pixels 724H x 697V) is used, the actual resolution (number of pixels) is 601H x 576V, approx. 350000 pixels.)
724
582 (*697)
494 (*582)
Using PAL C C D for NTSC camera Vertical EIS operation controlled cutting out position 6 1 1 (*601)
The image in NTSC monitor
494 (*582)
1.2 X Digital Zoom Horizontal :611 7 2 0 (*601 720) Horizontal EIS operation controlled line memory access
The image on NTSC monitor
Fig. 3-1-3 Electrical Image Stabilizer
3-3
3.2 V. DRIVER
3.2.1 V. DRIVER (IC5501) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VL OV2 VM13 OV1 VCC IV1 CH1 IV2 ISUB NC IV4 CH2 IV3 GND VH OV3 OV4 VM24 VHH Label OSUB In/Out Out Out Out In In In In In In In Out Out Substrate pulse output Low level power supply (-6.5V) V2 transmission pulse output (2 state) Middle level power supply (GND) V1 transmission pulse output (3 state) Power supply for input section (3V) V1 transmission pulse input Signal charge gate pulse V2 transmission pulse input Substrate pulse input Not used V4 transmission pulse input Signal charge gate pulse V3 transmission pulse input GND High level power supply (16.5V) V3 transmission pulse output (3 state) V4 transmission pulse output (2 state) Middle level power supply (GND) High level power supply (16.5V) Description
Table 3-2-1 V. DRIVER (IC5501) pin functions
3-4
3.3 T. G
3.3.1 T. G (IC5502) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Label XSG2 XV3 XSG1 VSS1 XV1 XV2 XSUB VDD1 RG VSS2 VSS3 H1 H2 VDD2 VDD3 XRS SHP SHD VSS4 ADCKO CP2 PBLK OBCLP CLPDM CKO OSCI OSCO VDD4 CKI TEST1 CLO VSS5 CKSW1 CKSW2 VGAT RCNT RST SSCK SSI SEN VDD5 AHD AVD VSS6 ID CAMVTR TEST2 XV4 In/Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In Out In In Out In In In In In In In In In In Out In In Out Description CCD signal charge gate pulse CCD vertical transfer clock CCD signal charge gate pulse GND CCD vertical transfer clock CCD vertical transfer clock CCD signal charge sweep out pulse (for high speed shutter) Power supply CCD reset gate pulse GND GND CCD horizontal transfer clock CCD horizontal transfer clock Power supply Power supply Sampling pulse CDS precharge level S/H pulse CDS data level S/H pulse GND A/D converter clock A/D converter OB clamp pulse Pre block clean pulse CDS OB clamp pulse Dummy signal clamp pulse Not used Not used Not used Power supply Main clock (27MHz) Not used Not used GND A/D converter clock phase select A/D converter clock phase select Vertical transfer clock reduce control Reset gate pulse control (L:positive /H:negative) Reset Serial data clock Serial data input Serial data strobe Power supply HD input VD input GND Line ID Mode select after reset Not used CCD vertical transfer clock
Table 3-3-1 T. G (IC5502) pin functions
3-5
3.4 CDS AGC

This IC incorporates the usual correlation double sampling, AGC, A/D converter reference voltage circuit, as well as the 15-CH EVR-DAC based on serial data inputs. However the number of channels actually used are four channels (OB setup adjustment, gamma correction setting, optical block hall gain adjustment, and hall offset adjustment) only. The serial data is input from the SYSCON CPU IC1001 based on adjustment values written on the EEPROM. 3.4.1 CDS AGC (IC5601) pin assignment
AGC_REF_OUT G_MODE_SW
AGC_OUT2
AGC_OUT1 26
TRAP_OUT
CDS_OUT
AGC_DET
PBLK_IN
AGC_IN
VCC1
36
35
34
33
32
31
30
29
28
27
25 P.sepa 24 OBCLB_IN GND G_IN VRM_OUT PreApa_OUT SUBAMP_IN SUBAMP_DET A/D_OUT OB_CONT SETUP_ADJ
TEST DS2 GND CCDOUT_IN VRMH 37 38 39 40 41 PreApa.DL_IN VCC3 G_MODE_SW GND 42 43 + 44 45 46 VRT VRB 47 48 VrefH 3.0V VrefB 1.0V VCO Serial_Control 15CH_DAC GC 560 S/H BIAS VrefMH 2.75V Knee_Cont 9dB S/H 3dB GC DC Cont
VCC2
DS1
23 22 VrefM 1.8V 21 20 19 18
GAMMA
DL
GC
DC_Cont
17 16 15 14 13
10
11
12
S_CLK
CDS_CS
H_GAIN
GND
S_DT
Fig. 3-4-1 CDS AGC (IC5601) pin assignment
3-6
H_OFFSET
VDD_OUT
3.4.2 CDS AGC (IC5601) pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Label DAC CH1 OUT VDD OUT VSS DI SCLK LOAD DAC CH8 OUT DAC CH9 OUT DAC CH12 OUT DAC CH10 OUT DAC CH11 OUT DAC CH15 OUT DAC CH14 OUT DAC CH13 OUT DAC CH4 OUT OB CONTROL A/D OUT SUB AMP DET SUB AMP IN PREAPA OUT VREFM OUT GAMMA IN GND2 CPOB IN VCC2 AGC OUT1 AGC OUT2 PBLK IN AGC DET AGC IN TRAP OUT GAMMA MODE AGC REF OUT CDS OUT VCC2 DS1 IN DS2 IN GND1 CCDOUT IN VREFMH OUT GAMMA OUT PREAPA DL IN VCC3 DAC CH6 OUT GND3 DAC CH7 OUT VREFH OUT VREFB OUT In/Out Out Out In In In Out Out Out Out Out Out Out Out Out In Out In Out Out In In Out Out In In In Out Out In In In Out Out In Out Out Out Out Description Not used Power supply output (3.5V) GND Serial data input Serial data clock Chip select Hole gain adjustment output Hole offset adjustment output Not used Not used Not used Not used Not used Not used Optical black set up adjustment output Optical black set up adjustment input Signal output to A/D converter Sub amplifier input Not used Reference voltage output (1.8V) GND Optical black clamp pulse input Power supply AGC signal output AGC signal output Blanking pulse input AGC input
CDS signal output Power supply CDS signal level S/H pulse CDS pre-charge level S/H pulse GND CCD signal input Reference voltage output (2.75V) Not used Not used Power supply Gamma mode select GND Not used Top reference voltage for A/D converter (3.0V) Bottom reference voltage for A/D converter (1.0V)
Table 3-4-1 CDS AGC (IC5601) pin functions

3-7
3.5 ADC FUNCTION

3.5.1 ADC (IC4201) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Label NC NC AVSS VRTS VRT AVSS AVDD VRM AVDD VIN NC NC NC NC AVSS VRB VRBS AVSS AVDD AVDD TEST D0 NC NC NC NC D1 D2 D3 AVSS DVDDL D4 D5 D6 NC NC NC NC D7 D8 NC AVSS AVDD CLK NOE POWD NC NC In/Out In In In In Out Out Out Out Out Out Out Out Out In In In Description Not used Not used GND (analog) Not used Top reference voltage (3.0V) GND (analog) Power supply (analog) Middle reference Power supply (analog) Analog signal input Not used Not used Not used Not used GND (analog) Bottom reference voltage (1.0V) Not used GND (analog) Power supply (analog) Power supply (analog) Not used Digital signal output (LSB) Not used Not used Not used Not used Digital signal output GND (analog) Power supply (digital) Power supply (analog) Not used Not used Not used Not used Digital signal output Digital signal output (MSB) Not used GND (analog) Power supply (analog) Clock input 13.5MHz L: normal fixed OB clamp input H:power down mode (no output) /L:normal mode Not used Not used
Table 3-5-1 ADC (IC4201) pin functions

3-8
3.6 FOCUS & ZOOM DRIVER

This IC drives and controls the FOCUS and ZOOM pulse motors. It is composed of the serial data decoder, drive pulse generator, and current setting and output driver. The serial data is input from the SYSCON CPU, after which first the initial data is sent when the power is turned on, and initial settings are performed. Next, standard data such as pulse width, number of pulses, rotation direction (CW/CCW), and current settings are synchronized with the VD, and input sequentially to drive the motor. 3.6.1 Focus & Zoom driver (IC4851) pin assignment
PGND EXP3 EXTa Vm1 A1 FBa A2 Vm2 B1 FBb B2 EXTb VD LATCH SDATA SCLK OSCin OSCout RESET
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 1/N OSC SERIAL DECODER PULSE GENERATER H BRIDGE a 2ch H BRIDGE b 2ch H BRIDGE a 1ch H BRIDGE b 1ch
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EXP2 EXP1 EXP0 C1 FBc C2 Vm4 D1 FBd D2 Vm3 Vdd Vref FILd FILc FILb FILa Cosc LGND
C U R R E N T S E Ta EVR2 EVR1
C U R R E N T S E Tb EVR1 EVR2
Fig. 3-6-1 Focus & Zoom driver (IC4851) pin assignment
3-9
3.6.1 Focus & Zoom driver (IC4851) pin functions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Label LGND COSC FILa FILb FILc FILd Vref Vdd Vm3 D2 FBd D2 Vm4 C2 FBc C1 EXP0 EXP1 EXP2 PGND EXP3 EXTa Vm1 A1 FBa A2 Vm2 B1 FBb B2 EXTb VD LATCH SDATA SCLK OSCin OSCout RESET In/Out In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In In In Out In Description GND for logic section Chopping capacitor Focus 1ch filter capacitor Focus 2ch filter capacitor Zoom 1ch filter capacitor Zoom 2ch filter capacitor Reference voltage Power supply for logic section Power supply for output section Zoom 2ch output Zoom 2ch feed back Zoom 2ch output Power supply for output section Zoom 1ch output Zoom 1ch feed back Zoom 1ch output Monitor (not used) GND for power section Monitor (not used) Logic monitor (not used) Power supply for output section Focus 1ch output Focus 1ch feed back Focus 1ch output Power supply for output section Focus 2ch output Focus 2ch feed back Focus 2ch output Logic monitor (not used) Vertical drive pulse Latch signal Serial data input from SYSCON IC1001 Serial clock input from SYSCON IC1001 Master clock Master clock output Reset input from SYSCON IC1001
Table 3-6-1 Focus & Zoom driver (IC4851) pin functions
3-10
3.7 YMCA & SSG

This IC is the DV camera signal processing DSP. In addition to the current YCA and EISFMC, the SSG, microprocessor IF, and shutter sound generator have been mounted on one chip. The YCA inputs video data from the color difference line sequential method CCD and carries out Y/C signal processing and high picture quality processing. The Y/C signal processing and high picture quality processing optimizes video outputs by setting data from the SYSCON. It also carries out various calculations using the Y/C signal, and outputs the AWB/AE data and AF data to the SYSCON. The YCA also incorporates a screen photometry circuit and iris control PWM. The EISFMC carries out digital effects and handshake correction by movement vector detection, and field memory access control. 3.7.1 YMCA & SSG (IC4301) pin assignment
GND CORE_VDD GND ROMOUT RAMOUT MEMCLK MEMTEST MEMIN SCANOUT SCANIN SCANMODE GND VDD TDO TDI TMS JTAGMODEB TCK GND CORE_VDD MCLR KRST GND VDD TMC3 TMC2 TMC1 TMC0 TMY7 TMY6 TMY5 GND TMY4 TMY3 TMY2 TMY1 TMY0 GND VDD MCLK RADO WADO RAEO WAEO FMWR FMREO FMWEO IEO VDD GND ADI8 ADI7 ADI6 ADI5 ADI4 ADI3 ADI2 ADI1 ADI0 VDD GND FH2 LHFIN FLDYCA VDYCAR HDYCAR OSCAO CLKYCA FLDTG VDTGR HDTGR OSCBO VDD GND LHF XIA XOA GND XIB XOB VDD CMPA CMPB FLDFMC VDFMC HDFMC GND AFBEND BEND PWM TNW OMT VDD GND CORE_VDD GND 1 31 30 15 76 45 60 29 44 75 43 59 58 74 57 89 73 72 71 88 87 86 85 90 102 97 98 99 100 109 110 101 111 123 124 112 113 137 138 125 151 126 152 139 165 127 166 140 46 16 61 2 32 17 47 3 33 18 4 62 48 19 5 34 63 20 6 49 35 21 7 77 78 8 22 36 50 9 23 37 64 10 51 24 38 11 65 25 12 52 39 79 13 26 40 14 53 27 66 28 54 41 67 42 68 55 56 80 81 69 70 82 92 83 84 93 94 95 96 91 103 108 107 106 105 122 121 120 104 136 119 135 134 150 118 149 164 133 148 117 178 163 162 192
Y/C AUTO
m- c o m IF
YC SELECT
EIS FMC
KASHA
OUTPUT SELECT
SSG
GND VDD FMY0 FMY1 FMY2 FMY3 FMY4 FMY5 FMY6 FMY7 FMC0 FMC1 FMC2 FMC3 GND CORE_VDD AGND AVDD KOUT GND 2.2VDD YOUT0 YOUT1 YOUT2 YOUT3 GND YOUT4 YOUT5 YOUT6 YOUT7 GND 2.2VDD COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 COUT6 COUT7 GND VTR45M INH INV GND 2.2VDD GND CORE_VDD
MAD15 MAD14 MAD13 MAD12 MAD11 VDD GND MAD10 MAD9 MAD8 MAD7 MAD6 MAD5 VDD GND MAD4 MAD3 MAD2 MAD1 MAD0 GND ALE NRE NHWE NLWE OSC27 VDD GND CLKTST CRCB CSYNC CORE_VDD GND PBVS PBHS DDFSK CVID3 CVID2 CVID1 CVID0 YVID7 YVID6 YVID5 YVID4 YVID3 YVID2 YVID1 YVID0
179 153 167 180 114 154 141 181 168 128 182 155 169 142 183 129 156 170 184 143 157 171 185 115 116 186 172 158 144 187 173 130 159 188 174 145 131 189 175 160 190 146 176 161 191 132 177 147
Fig. 3-7-1 YMCA & SSG (IC4301) pin assignment

3-11
3.7.2 YMCA & SSG (IC4301) pin functions-1/4

Pin No. 1 31 30 15 76 45 60 29 44 75 43 59 58 74 57 89 73 72 71 88 87 86 85 90 102 97 98 99 100 109 110 101 111 123 124 112 113 137 138 125 151 126 152 139 165 127 166 140 Label VDD GND ADI8 ADI7 ADI6 ADI5 ADI4 ADI3 ADI2 ADI1 ADI0 VDD GND FH2 LHFIN FLDYCA VDYCAR HDYCAR OSCAO CLKYCA FLDTG VDTGR HDTGR OSCBO VDD GND LHF XIA XOA GND XIB XOB VDD CMPA CMPB FLDFMC VDFMC HDFMC GND AFBEND BEND PWM TNW OMT VDD GND CORE_VDD GND In/Out In In In In In In In In In In Out Out Out Out Out Out Out Out Out Description Power supply 3V GND (MSB)
Signal input from A/D IC4202
(LSB) Power supply 3V GND Line distinction Not used VD output to TG HD output to TG Clock 27MHz to TG
Not used
Power supply 3V GND Not used GND Not used Power supply 3V Not used Field distinction to SYSCON CPU IC1001 VD to SYSCON CPU IC1001 HD to SYSCON CPU IC1001 GND Not used IRIS control output FMC busy EIS data read out timing Power supply 3V GND Power supply 3V GND
Table 3-7-1 YMCA & SSG (IC4301) pin functions-1/4
3-12
YMCA & SSG (IC4301) pin functions-2/4

Pin No. 179 153 167 180 114 154 141 181 168 128 182 155 169 142 183 129 156 170 184 143 157 171 185 115 116 186 172 158 144 187 173 130 159 188 174 145 131 189 175 160 190 146 176 161 191 132 177 147 Label MAD15 MAD14 MAD13 MAD12 MAD11 VDD GND MAD10 MAD9 MAD8 MAD7 MAD6 MAD5 VDD GND MAD4 MAD3 MAD2 MAD1 MAD0 GND ALE NRE NHWE NLWE OSC27 VDD GND CLKTST CRCB CSYNC CORE_VDD GND PBVS PSHS DDFSK CVID3 CVID2 CVID1 CVID0 YVID7 YVID6 YVID5 YVID4 YVID3 YVID2 YVID1 YVID0 In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In In In In In In In In In In In In In In In In In In Description (MSB) CPU data/address 16bits MPX BUS
Power supply 3V GND
CPU data/address 16bits MPX BUS
Power supply 3V GND
CPU data/address 16bits MPX BUS (LSB) GND Address latch enable Read enable write enable write enable Clock 27MHz Power supply 3V GND Not used Power supply 3V GND VTR PB horizontal reference signal VTR PB vertical reference signal Reference clock 13.5MHz PB chroma input from deck section
PB luminance input from deck section
3-13

Pin No. 192 162 163 178 117 148 133 164 149 118 150 134 135 119 136 104 120 121 122 105 106 107 108 103 91 96 95 94 93 84 83 92 82 70 69 81 80 56 55 68 42 67 41 54 28 66 27 53 Label CORE_VDD GND 2.2VDD GND INV INH VTR45M GND COUT7 COUT6 COUT5 COUT4 COUT3 COUT2 COUT1 COUT0 2.2VDD GND YOUT7 YOUT6 YOUT5 YOUT4 GND YOUT3 YOUT2 YOUT1 YOUT0 2.2VDD GND KOUT AVDD AGND CORE_VDD GND FMC3 FMC2 FMC1 FMC0 FMY7 FMY6 FMY5 FMY4 FMY3 FMY2 FMY1 FMY0 VDD GND In/Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In In Description Power supply 3V GND Power supply 2.2V GND Vertical reference to VTR Horizontal reference to VTR Clock output to FOCUS/ZOOM IC4851 GND
Chroma signal output to deck section
Power supply 2.2V GND Luminance signal output to deck section GND Luminance signal output to deck section Power supply 2.2V GND Shutter sound Power supply 3V GND Power supply 3V GND Chroma signal input from field memory
Luminance signal input from field memory
Power supply 3V GND
3-14

Pin No. 14 40 26 13 79 39 52 12 25 65 11 38 24 51 10 64 37 23 9 50 36 22 8 78 77 7 21 35 49 6 20 63 34 5 19 48 62 4 18 33 3 47 17 32 2 61 16 46 Label IEO FMWEO FMREO FMWR WAEO RAEO WADO RADO MCLK VDD GND TMY0 TMY1 TMY2 TMY3 TMY4 GND TMY5 TMY6 TMY7 TMC0 TMC1 TMC2 TMC3 VDD GND KRST MCLR CORE_VDD GND TCK JTAGMODEB TMS TDI TDO VDD GND SCANMODE SCANIN SCANOUT MEMIN MEMTEST MEMCLK RAMOUT ROMOUT GND CORE_VDD GND In/Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In In In In In In Out Description Input enable Write enable Read enable Not used Read address enable Write address Read address Clock output to field memory Power supply 3V GND
Luminance signal output to field mamory
GND Luminance signal output to field mamory
Chroma signal output to field mamory Power supply 3V GND Shutter sound reset Main reset Power supply 3V GND
Not used (for boundaly scan test)
Power supply 3V GND
Not used
GND Power supply 3V GND
3-15
3.8 FM
3.8.1 FM (IC4302) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Label NC GND D11(CIN3) D10(CIN2) D9(CIN1) D8(CIN0) D7(YIN7) D6(YIN6) D5(YIN5) D4(YIN4) D3(YIN3) D2(YIN2) D1(YIN1) D0(YIN0) SWCK RSTW WE IE VCC NC VCC OE RE RSTR SRCK Q0(YOUT0) Q1(YOUT1) Q2(YOUT2) Q3(YOUT3) Q4(YOUT4) Q5(YOUT5) Q6(YOUT6) Q7(YOUT7) Q8(COUT0) Q9(COUT1) Q10(COUT2) Q11(COUT3) GND In/Out In In In In In In In In In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Description Not used GND
Data iuput
Serial write clock Reset write Write enable Input enable Power supply Not used Power supply Output enable Read enable Reset read Serial read clock
Data output
GND
Table 3-8-1 FM (IC4302) pin functions
3-16
3.9 DVIO FUNCTION

During recording, 4:2:2 video data (Y: 8 bits /Cr, Cb: 8bits 13.5 MHz) from the camera is converted to the 4:1:1 (*4:2:0) (Y/C: 8 bits 18 MHz) and output to the shuffle memory. During playback, the 4:1:1 (*4:2:0) DVC data is converted to the 4:2:2 internal data and sent to the analog video output. In the playback digital mode, the 4:1:1 data is sent to the camera (YMCA). At this time, the color difference signal is sent by the method which divides the data into upper 4 bits and lower 4 bits. The analog output has four DACs-Y, C, Cr, and Cb while a synchronization block has been added for the Y signal. A color encoder and burst function are also incorporated for the C signal. 3.9.1 DVIO (IC3202) pin assignment
TEST1 TEST0 VDD2V VDD3V VSS DUMMY7 DUMMY6 DUMMY5 DUMMY4 DUMMY3 DUMMY2 DUMMY1 DUMMY0 INV INH YSI7 YSI6 YSI5 YSI4 YSI3 YSI2 YSI1 YSI0 VDD2V VDD32 VSS CSI7 CSI6 CSI5 CSI4 CSI3 CSI2 CSI1 CSI0 CAMCLK REFCLK PBY7 PBY6 PBY5 PBY4 PBY3 PBY2 PBY1 PBY0 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 SCAN VSS VDD3V VDD2V INF TRST TMS TCK TDI TDO VSS SHORTCUT VMASK PWROFF YADJ CPSYNC YIN YADVREFH YADVBSI AVSS YADVREFM YADVREFL AVDD AVSS CIN CADVREFH CADVBSI AVSS CADVREFM CADVREFL AVDD AVSS ADVSS ADVDD ADVSS ADVDD 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
Signal Selector
4:2:24:1:1
Color Bar Generator
Clock Conv.
4:2:24:1:1
PLL
FRPGEN
1/20
Y DAC
C DAC
Cr DAC
Cb DAC
PC 1/2
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
VDD2V VDD32 VSS PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBVS PBHS DSF7 DSF6 DSF5 DSF4 DSF3 DSF2 DSF1 DSF0 VDD2V VDD23 VSS CLK18M1 CLK450K CLK18M2 CLK188M CASVD CASHD FRP SDIO SCLK STP LCDCK VSS VDD2V RST APCRST MCVS VSS XOUT XIN VDD3V
YDAVREF YDABIAS YOUT AVDD AVSS CDAVREF CDABIAS COUT ADVDD ADVSS CRDAVREF CRDABIAS CROUT AVDD AVSS CBDAVREF CBDABIAS CBOUT AVDD AVSS PWDNADDA POFF27 POFF18 POFFCG FILSW27 FILSW18 EVFHD VBLK CGHD VSS CLK27IN CLK27OUT CLK18IN CLK18OUT VDD3V VDD2V CLKCGIN CLKCGOUT VSS PC27C PC27H PC18C PCCG CLKCG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Fig. 3-9-1 DVIO (IC3202) pin assignment
3-17
3.9.2 DVIO (IC3202) pin functions-1/4

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Label YDAVREF YDABIAS YOUT AVDD AVSS CDAVREF CDABIAS COUT ADVDD ADVSS CRDAVREF CRDABIAS CROUT AVDD AVSS CBDAVREF CBDABIAS CBOUT AVDD AVSS PWDNADDA POFF27 POFF18 POFFCG FILSW27 FILSW18 EVFHD VBLK CGHD VSS CLK27IN CLK27OUT CLK18IN CLK18OUT VDD3V VDD2V CLKCGIN CLKCGOUT VSS PC27C PC27H PC18C PCCG CLKCG In/Out In In Out In In Out In In Out In In Out In Out Out Out Out Out In In Out In Out Description Y-DAC reference voltage Y-DAC bias Luminance signal output Power supply GND C-DAC reference voltage C-DAC bias Color signal output Power supply GND Cr-DAC reference voltage Cr-DAC bias Chroma signal output Power supply GND Cb-DAC reference voltage Cb-DAC bias Chroma signal output Power supply GND Not used H:fixed Not used 18M VCO power off control Not used H:fixed Not used 18M VCO input serect control H pulse for OSD Brank pulse for OSD Not used GND Not used Not used Clock input 18MHz Feed back 3V power supply 2V power supply Not used Not used GND Not used Not used 18MHz phase comparison output Not used Not used
Table 3-9-1 DVIO (IC3202) pin functions-1/4
3-18
DVIO (IC3202) pin functions-2/4

Pin No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Label VDD3V XIN XOUT VSS MCVS APCRST RST VDD2V VSS LCDCK STP SCLK SDIO FRP CASHD CASVD CLK188M CLK18M2 CLK450K CLK18M1 VSS VDD23 VDD2V DSF0 DSF1 DSF2 DSF3 DSF4 DSF5 DSF6 DSF7 PBHS PBVS PBC0 PBC1 PBC2 PBC3 PBC4 PBC5 PBC6 PBC7 VSS VDD32 VDD2V In/Out In Out Out In In In In In/Out Out Out Out In Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out Out Out Out Out Out Description 3V power supply 27MHz X'tal OSC input 27MHz X'tal OSC output GND Frame reference output Reset Reset 2V power supply GND Not used Serial communication enable from MSD IC Serial clock from MSD IC Serial data from MSD IC Frame pulse output H reference for CAS IC V reference for CAS IC Memory write timing 18/8=2.25MHz Clock output 18MHz Clock output 450KHz Clock output 18MHz GND 2/3V power supply (2V or 3V) 2V power supply
Data bus from/to shuffle memory
H reference for PB digital V reference for PB digital Cr,Cb signal output for PB digital
Not used
GND 2/3V power supply (2V or 3V) 2V power supply
3-19

Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Label PBY0 PBY1 PBY2 PBY3 PBY4 PBY5 PBY6 PBY7 REFCLK CAMCLK CSI0 CSI1 CSI2 CSI3 CSI4 CSI5 CSI6 CSI7 VSS VDD32 VDD2V YSI0 YSI1 YSI2 YSI3 YSI4 YSI5 YSI6 YSI7 INH INV DUMMY0 DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 VSS VDD3V VDD2V TEST0 TEST1 In/Out Out Out Out Out Out Out Out Out Out In In In In In In In In In In In In In In In In In In Description
Y signal output for PB digital
Data transfer clock 13.5MHz PLL reference 4.5MHz
Camera Cr,Cb signal input
GND 2/3V power supply (2V or 3V) 2V power supply
Camera Y signal input
H reference V reference
Not used
GND 3V power supply 2V power supply Not used
3-20

Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Label TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 SCAN VSS VDD3V VDD2V INF TRST TMS TCK TDI TDO VSS SHORTCUT VMASK PWROFF YADJ CPSYNC YIN YADVREF YADVBSI AVSS YADVREFM YADVREFL AVDD AVSS CIN CADVREFH CADVBSI AVSS CADVREFM CADVREFL AVDD AVSS ADVSS ADVDD ADVSS ADVDD In/Out In In In In In Out Description
Not used
Not used GND 3V power supply 2V power supply Frame reference pulse from DV I/F
For boundaly scan
GND
Not used
GND Not used Power supply GND Not used GND Not used Power supply GND GND Power supply GND Power supply
3-21
3.9.3 PLL circuit description The reference clock of the DVC circuit 18 MHz is generated by the VCO inside the PLL IC3201. During playback and camera picture recording, the switch in the PLL IC is connected to the Pin 33 input. At this time, the 18 MHz clock is locked to the 27 MHz of the crystal oscillator X1401. During DV input recording, the switch is set to the 1394 REC side, and the 18 MHz clock is synchronized with the frame pulse of the DV input (reception) signal from the digital interface. The PC (Phase Comparator) is located inside the MSD IC1401. This 18 MHz clock is sent to the shuffle memory as CLK18M1 from Pin 62 and output from Pin 64 to the CAS, EDA, and digital IF as the CLK18M2. The frequency-divided 450 KHz is sent to the EDA PC as the CLK450K from Pin 63, to become the reference of the recording clock VCO.
DVIO
X1401 XIN 4 6
IC3202 PLL
REF PLAY CAMERA REC
1/6
IC3201
27MHz CLK18IN 33
1/4
4.5MHz
PC
42
PC18C
33
18MHz
VCO
1394 REC
25
62/64
CLK18M1/M2 35 CLK540K
1/20
63
FRPGEN SSG YMCA

INV/INH 118/119 P B V S / P B H S 76/77
58
FRP
MSD
62
IC1401
DIF
INF 145
REF
49
MCVS
63
PC
95 VPLL
Fig. 3-9-2 PLL circuit block diagram IC3201 mode switching settings The mode of the IC3201 18 MHz PLL is switched by the settings of Pins 29 and 30, while the mode of the audio FS frequency PLL is switched by the settings of Pins 39 and 40.
29 33 PB/CAMERA REC 35 1394 REC Power Save 30 40 46 FSCLK 12.3M(48K) 11.3M(44.1K) 8.2M(32K) 39
H L L
L H L
H L H
L L H
Table 3-9-2 PLL mode settings
3-22
3.10 COMPRESS/AUDIO/SHUFFLE (CAS) FUNCTION

This IC carries out digital signal processing of the video and audio signals on conforming to the DV format. Its comes equipped with the usual LSI functions such as COMPRESS, SHUFFLING, and AUDIO PROCESS. During recording, it controls the address read/write enable of the SHUFFLE MEMORY to shuffle the video signals. After that, it carries out, on the video data, adaptive two-dimensional discrete cosine transform (DCT), re-digitization, and variable length coding (VLC), and saves the data in the synchronization block, and outputs the data to the DVC bus. At the same time, it also performs 1 frame completion shuffling on audio signals, and outputs the data to the DVC bus after saving in the synchronization block. During playback, it performs the reverse process of recording. It extracts video synchronization block data and audio synchronization block data on the DVC bus, and decodes video data and audio data from the extracted data.
IC8001 IC3001 IC3003
D-IF
CAS
SSP DV BUS: BD0-3,SMP
EDA
SSP: Sector(1-track) Start/Stop Pulse SMP: DV BUS Start Mark Pulse
Fig. 3-10-1 DV-BUS connection 3.10.1 CAS IC3001 pin assignment

VSS FRP DIBCK DIMCK DOBCK DOMCK DOLRCK DODAT VSS XI XO VDDE3 VDDE3 VDDI2 AIDAT RECMUT VSS DIDAT DILACK LKFRP SCK SDA STP CLK24 RST SHM225 HSP VSP DFD7 DFD6 DFD5 DFD4 VSS DFD3 DFD2 DFD1 DFD0 VDDE2 VDDE2 VDDI2 CLK18 VSS SMADD17 SMADD16 SMADD15 SMADD14 SMADD13 SMADD12 SMADD11 VSS 104 97 103 96 87 76 102 86 95 75 64 63 74 94 101 73 84 93 100 72 83 92 99 91 98 89 88 90 78 79 77 65 67 66 68 57 53 55 54 42 46 45 44 43 34 36 35 25 23 24 7 14 6 13 22 33 32 12 21 5 41 31 20 11 4 30 10 19 3 29 18 9 2 8 1
Audio ADC/DAC I/F Sample Conv.
m-com I/F
Video Compress DCT/VLC I-DCT/VLD
DV BUS I/F
Shuffle Address
VSS TDI TMS TCK TRST TDO PWMO FS0 FS1 VSS VCOI VCOO VDDE3 VDDI2 VSS TINT0 TINT1 TINT2 TINT3 TINT4 TINT5 TINT6 TINT7 SSP VSS
SMADD10 SMADD9 SMADD8 SMADD7 SMADD6 SMADD5 SMADD4 VSS SMADD3 SMADD2 SMADD1 SMADD0 VDDE2 VDDI2 SMEC SMRS VSS SMWE SMWS SMDIOS SMP BD3 BD2 BD1 BD0
81 82 80 70 69 71 61 59 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16
Fig. 3-10-2 CAS IC3001 pin assignment
3-23
3.10.2 CAS IC3001 pin functions-1/3

Pin No. 104 97 103 96 87 76 102 86 95 75 64 63 74 94 101 73 84 93 100 72 83 92 99 91 98 81 82 80 70 69 71 61 59 HSP VSP DFD7 DFD6 DFD5 DFD4 VSS DFD3 DFD2 DFD1 DFD0 VDDE2 VDDE2 VDDI2 CLK18 VSS SMADD17 SMADD16 SMADD15 SMADD14 SMADD13 SMADD12 SMADD11 VSS SMADD10 SMADD9 SMADD8 SMADD7 SMADD6 SMADD5 SMADD4 VSS Label SHM225 In/Out Out In In In/Out In/Out REC :from shuflle memory to DCT block PB :from IDCT block to shuffle memory In/Out (8 bits) In/Out In/Out In/Out REC :from shuflle memory to DCT block PB :from IDCT block to shuffle memory In/Out (8 bits) In/Out In In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out GND Shuffle memory address output (18 bits) GND Shuffle memory address output (18 bits) External 2V power supply Internal 2V power supply System clock input 18MHz GND GND Description Phase reference for shuffle memory (2.25MHz) Horizontal timing control for shuffle memory Vertical timing control for shuffle memory
Table 3-10-1 CAS IC3001 pin functions-1/3
3-24
CAS IC3001 pin functions-2/3

Pin No. 60 62 58 51 49 50 47 37 39 38 40 28 26 27 15 17 16 1 8 2 9 18 29 3 19 10 30 4 11 20 31 41 Label SMADD3 SMADD2 SMADD1 SMADD0 VDDE2 VDDI2 SMCE SMRS VSS SMWE SMWS SMDIOS SMP BD3 BD2 BD1 BD0 VSS SSP TINT7 TINT6 TINT5 TINT4 TINT3 TINT2 TINT1 TINT0 VSS VDDI2 VDDE3 VCOO VCOI In/Out In/Out In/Out Shuffle memory address output In/Out (18 bits) In/Out Out Out Out Out Out In/Out In/Out In/Out In/Out Out In In In In In In In In Out In GND Internal 2V power supply External 3V power supply Clock for PB auodio Mode select Not used :normal settings "00000000" GND DVC bus sector start pulse DVC bus data (4 bits) External 2V power supply Internal 2V power supply Shuffle memory chip enable Shuffle memory read strobe GND Shuffle memory write enable Shuffle memory write strobe Shuffle memory I/O control Description
In/Out DVC start mark pulse
3-25
CAS IC3001 pin functions-3/3

Pin No. 5 21 12 32 33 22 13 6 14 7 24 23 25 35 36 34 43 44 45 46 42 54 55 53 57 68 66 67 65 77 79 78 90 88 89 VSS FS1 FS0 PWMO TDO TRST TCK TMS TDI VSS RST CLK24 STP SDA SCK LKFRP DILRCK DIDAT VSS RECMUT AIDAT VDDI2 VDDE3 VDDE3 XO XI VSS DODAT DOLRCK DOMCK DOBCK DIMCK DIBCK FRP VSS Label In/Out Out Out Out Out In In In In In GND Reset For boundaly scan GND Audio PLL mode select "00":44.1kHz /"01":off /"10":48kHz /"11":32kHz Voltage control for audio PLL Description
In/Out Clock output 24.576MHz In/Out Serial communication start/stop control from/to MSD CPU In/Out Serial data from/to MSD CPU In In In In In In Out In Out Out Out Out In In In Serial clock from MSD CPU Frame pulse for audio Not used Not used GND Not used Data input from audio A/D converter Internal 2V power supply External 3V power supply Clock for audio and digital I/F (24.576MHz) GND Serial data output to audio D/A converter L/R clock output to audio A/D,D/A converter Master clock output to audio A/D,D/A converter Bit clock output to audio A/D,D/A converter Not used Not used Frame pulse GND
3-26
3.11 ECC/DCI/ATF (EDA) FUNCTION

This IC carries out error correction coding (ECC), 24-25 modulation/demodulation (DCI), tracking error detection (ATF), head switch signal generation, VITERBI decoding, and clock phase correction. During recording, the AUDIO and VIDEO data from the DV bus and the AUX and SUBCODE data from the microprocessor (MSD) are received, error correction coding and 24-25 modulation are performed according to the DV format to generate recording signals, which are the output to the REC amplifier. During playback, the playback signal from the PB equalizer is VITERBI decoded, sync block extraction, and corrected by error correction decoding. The AUDIO and VIDEO data are output to the DV bus and the AUX and SUBCODE data to the microprocessor (MSD). In VITERBI decoding, the clock phase for the VITERBI A/D converter is detected, and phase compensation control the PBEQ IC is carried out. At the same time, the ATF pilot signal components are detected from the playback signal prefiltered in the PBEQ, and the tracking error information is sent to the microprocessor (MSD). 3.11.1 EDA IC3003 pin assignment
RD BLW VSSO VDDO2M DT15 ADDT14 ADDT13 ADDT12 ADDT11 ADDT10 ADDT9 ADDT8 VSSO VDDO2M ADDT7 ADDT6 ADDT5 ADDT4 ADDT3 ADDT2 ADDT1 ADDT0 VDDO2M VDDI VSSI VSSO VDDO3 TSR SPA NC FE HID1 HID2 HID3 RECI PBH RECCTRL VDDO3 NC NC NC NC VSSI VSSI VSSI VSSI 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79
ALE VDDI2M VSSI VDDI3 VSSI RST CYLFG CYLPG VSSI VSSI VSSI VSSI VSSI VSSI NC VDDI VSSI TRST TMS TDI TCK TDO VDDI3 SSP VSSO VDDO2B BD0 BD1 BD2 BD3 SMP VDDI2B
HIDCTL MSD I/F AFTDET A/D SRAM

AUX
SPCTL
SRAM
SUBCODE
CKCTL
PC
ECC/DCI Viterbi
78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47
NC VITON TRICK MEMP REFCLK CKPHASE VCOCTL ADSTB VDDO3 VSSO ADDAT6 ADDAT5 ADDAT4 ADDAT3 ADDAT2 ADDAT1 ADDAT0 VDDO3 VSSI HSE VDDO2 VDDO3 RECCLK VSSI VSSO PBCLK PBDAT VDDI3 DVCC3 AVCC3 ATFI VTOP
VSSI CLK450 CLK18 VDDI2 VSSO VDDO3R LCAS UCAS OE A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS WE VSSO VDDO3R VSSI VDDI DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDDO3R VSSO AGND AGND DGND VBTM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Fig. 3-11-1 EDA IC3003 pin assignment
3-27
3.11.2 EDA (IC3003) pin functions-1/4

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Label VSSI CLK450 CLK18 VDDI2 VSSO VDDO3R LCAS UCAS OE A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS WE VSSO VDDO3R VSSI VDDI DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 In/Out In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Description Vss for input buffer and inside logic section Reference for REC 24MHz VCO System clock input 18MHz 2V Vdd for input buffer and inside logic section Vss for output buffer section 3V Vdd for buffer of D-RAM I/F Lower column address strobe Upper column address strobe Output enable
Address for ECC memory
Row address strobe Write enable Vss for output buffer section 3V Vdd for buffer of D-RAM I/F Vss for input buffer and inside logic section 2V Vdd for input buffer and inside logic section
Data from/to ECC memory (16 bits)
Table 3-11-1 EDA (IC3003) pin functions-1/4
3-28

Pin No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Label DQ0 VDDO3R VSSO AGND AGND DGND VBTM VTOP ATFI AVCC3 DVCC3 VDDI3 PBDAT PBCLK VSSO VSSI RECCLK VDDO3 VDDO2 HSE VSSI VDDI3 ADDAT0 ADDAT1 ADDAT2 ADDAT3 ADDAT4 ADDAT5 ADDAT6 VSSO VDDO3 ADSTB VCOCTL CKPHASE REFCLK MEMP TRICK VITON N.C. In/Out In/Out In In In In Out In In In In In In In Out Out Out Out Out Out Out Description Data from/to ECC memory (16 bits) 3V Vdd for buffer of D-RAM I/F Vss for output buffer section GND for analog section of A/D GND for digital section of A/D A/D reference voltage (top) A/D reference voltage (bottom) A/D analog signal input 3V Vcc for analog section of A/D 3V Vcc for digital section of A/D 3V Vdd for input buffer section PB data PB clock Vss for output buffer section Vss for input buffer and inside logic section Rec clock 3V Vdd for output buffer section 2V Vdd for output buffer section Recording signal Vss for input buffer and inside logic section 3V Vdd for input buffer section
PB data from Viterbi-A/D
Vss for output buffer section 3V Vdd for output buffer section Viterbi-A/D power down Rec clock VCO control output Viterbi clock phase correction PWM output Auto EQ adjustment reference clock Mode settings for PB EQ IC Not used
3-29

Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Label VSSI VSSI VSSI VSSI N.C. N.C. N.C. N.C. VDDO3 RECCTRL PBH RECI HID3 HID2 HID1 FE N.C. SPA TSR VDDO3 VSSO VSSI VDDI VDDO2M ADDT0 ADDT1 ADDT2 ADDT3 ADDT4 ADDT5 ADDT6 ADDT7 VDDO2M VSSO ADDT8 ADDT9 ADDT10 ADDT11 ADDT12 In/Out Out Out Out Out Out Out Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Description Vss for input buffer and inside logic section
Not used 3V Vdd for output buffer section Recording on control Mode settings for PB EQ IC Head switch pulse 3 Head switch pulse 2 Head switch pulse 1 Flying erase timing pulse Not used ATF sampling pulse HID reference (Drum 150Hz) 3V Vdd for output buffer section Vss for output buffer section Vss for input buffer and inside logic section 2V Vdd for input buffer and inside logic section 2V Vdd for output buffer of Micom I/F
Address (15 bits) /data (16 bits)
2V Vdd for output buffer of Micom I/F Vss for output buffer section
Address (15 bits) /data (16 bits)
3-30

Pin No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Label ADDT13 ADDT14 DT15 VDDO2M VSSO BLW RD ALE VDDI2M VSSI VDDI3 VSSI RST CYLFG CYLPG VSSI VSSI VSSI VSSI VSSI VSSI N.C. VDDI VSSI TRST TMS TDI TCK TDO VDDI3 SSP VSSO VDDO2B BD0 BD1 BD2 BD3 SMP VDDI2B In/Out In/Out In/Out In/Out In In In In In In In In In In Out In In/Out In/Out In/Out In/Out In/Out Description Address (15 bits) /data (16 bits) Data (16 bits) 2V Vdd for output buffer of Micom I/F Vss for output buffer section Write strobe Read strobe Address lutch enable 2V Vdd for input buffer of Micom I/F Vss for input buffer and inside logic section 3V Vdd for input buffer section Vss for input buffer and inside logic section Reset Drum FG Drum PG
Vss for input buffer and inside logic section
Not used 2V Vdd for input buffer and inside logic section Vss for input buffer and inside logic section
For boundaly scan
3V Vdd for input buffer section Sector start pulse Vss for output buffer section 2V Vdd for output buffer of DV-BUS I/F DV-BUS data Start mark pulse 2V Vdd for input buffer of DV-BUS I/F
3-31
3.12 PB EQ FUNCTION
The PB equalizer equalizes the waveform of the playback signal to prevent coding errors by interference between coding processes when the high-density digital signal is magnetically recorded and played back. In the PLL circuit, the playback clock that is phase controlled for correctly identifying the playback data is generated. This IC also has an ATF signal extraction BPF and recording clock 41.85 MHz VCO for recording. 3.12.1 PB EQ (IC3501) pin assignment
1+DOUT 1+DOUT EQHLD ERRDL AGCIN DLADJ
GND7
GND6
PLLIN
VCC7
ERR2
ERR1
50
64
63
62
61
60
TFILOUT 59
1+DIN 58
57
56
55
54
53
52
51
VITON ATFIN GND
49
VCC6
PBH
1 2 3 4 5
LOGIC DELAY CONT BPF BPOUT AMPIN AMP
48 AMP 1+D DATA DET 47 46 45 PC 44 43 AMP A-EQ 42 41 VCO 40 39 PS
SDET2 GND5 SDET1 VCC5 PCOUT AMPIN AMPOUT VCOIN PHASEADJ MON3 CKPHASE VCC4 ADCLK PBCLK GND4 PBDAT
VCC1 ATFC ATFGAIN ATFIOUT REFDET REFCLK TRICKH TRICKL BETA ALFA MON1
ERROR DET
6 7 8 9 10 11 12 13 14
GCA TFIL REFF PRE-EQ
38 37 36 35 LATCH OUTPUT 34
OUTPUT LPF OUTPUT
15 17 PREEQ 18 TFILIN 16 BUFF AMP VCO OUTPUT
33
19
20
21
22
23
24
25
26
27
28
29
30
31
VCC2
VCC8
Fig. 3-12-1 PB EQ (IC3501) pin assignment
3-32
AMPOUT
VOCCTL
RECCLK
GND2
VCOIN
MON2
GND3
VCC3
DET1
DET2
DET3
DET4
32
3.12.2 PB EQ (IC3501) pin functions-1/2

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Label VIT_ON ATF_IN GND1 BP_OUT AMP_IN VCC1 ATFC ATF_GAIN ATFI_OUT REFDET REFCLK TRICK_H TRICK_L BETA ALFA MON1 PRE_EQ TFIL_IN MON2 DET1 DET2 DET3 DET4 GND2 VCOCTL VCC2 AMP_OUT VCC8 VCO_IN GND3 RECCLK VCC3 In/Out In In Out In In Out In In Out In In Out In In Out In Out Bit by Bit/VITERBI select ATF BPF input GND1 ATF BPF output ATF AMP input VCC1 ATF AMP output ATF gain control adjustment ATF output Reference frequency control voltage detection Reference clock for ATF BRF (450KHz) Inverter input Inverter output Pre-EQ phase characteristic adjustment (b) Pre-EQ characteristic adjustment (a) Pre-EQ delay monitor (not used) Pre-EQ output TFIL input Not used Auto-EQ detection 1 Auto-EQ detection 2 Auto-EQ detection 3 Auto-EQ detection 4 GND2 Phase error input VCC2 Phase error amp output VCC8 Rec clock VCO input GND3 Rec clock VCO output VCC3 Description
Table 3-12-1 PB EQ (IC3501) pin functions-1/2
3-33
PB EQ (IC3501) pin functions-2/2

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Label PB_DAT GND4 PB_CLK AD_CLK VCC4 CK_PHASE MON3 PHASEADJ VCO_IN AMP_OUT AMP_IN PC_OUT VCC5 SDET1 GND5 SDET2 VCC6 ERR1 ERR2 GND6 1+D_OUT ERRDL PLL_IN 1+D_OUT VCC7 1+D_IN TFIL_OUT DLADJ GND7 AGC_IN PB_H EQHLD In/Out Out Out Out In In In Out In Out In Out In In Out In Out In In In In PB data output GND4 PB clock output VITERBI A/D converter clock output VCC4 Clock phase adjustment input from VITERBI Not used Clock phase adjustment input from EVR PB VCO input Phase error amp output Phase error amp input PLL phase error output VCC5 Slice level adjustment GND5 Slice level detection VCC6 For error signal detection For error signal detection GND6 PB 1+D signal output to Viterbi A/D Error timing adjustment PB data 3-state detect, PLL input 1+D output to 3-state detect, PLL VCC7 1+D input TFIL output Delay adjustment GND7 Pre-EQ input PB/REC select (PB:H) EQ hold select Description
Table 3-12-1 PB EQ (IC3501) pin functions-2/2
3-34
3.12.3 PB EQ circuit The playback enveropes input from the PREAMP is subjected to optimum waveform equalization suitable for decoding at the PRE-EQ and AUTO-EQ. After that it is added with 1+D characteristics, and output to the VITERBI A/D converter as 1+DOUT. The 1+DOUT signal is an analog waveform with tertiary value (1, 0, -1). It is converted to 7-bits digital signal by the A/D converter, and sent to the VITERBI circuit. The digitized tertiary information is corrected by the VITERBI detection method and converted into the binary (0, 1) playback data. The 1+DOUT signal is re-input into the IC3501, and output as the PB DATA after tertiary detection and binary conversion by the fixed threshold value method in the DATA DET circuit, to become the playback data when the VITERBI is OFF. However in this unit, as VITERBI is always ON for both SP and LP, this applies only when VITERBI is forcibly turned OFF using the service support software. The playback clock is constantly phase-compared with the playback data in the PLL circuit, and output synchronized with the playback data. One is output to the A/D converter as the AD CLK, and the other is sent to the EDA as the PB CLK. As the sampling point is also changed during A/D conversion by this AD CLK, there is a need for sampling to be carried out at the correct position for the VITERBI detection circuit to operate correctly. Therefore the phase correction information from the VITERBI circuit is output as the CK PHASE, and the PS (phase shift) of the PLL circuit carries out fine adjustments of the phase. The adjustment values are input from the EVR IC3503 based on the data written in the EEPROM. In the adjustments, the service support software adjusts the values to the standard values by VCO Center adjustment first, after which the error rates are sequentially adjusted to the minimum values according to the order in which the other adjustment points were specified in the PB EQ adjustment.
Delay ADJ PB EQ IC3501 From: PREAMP AGC IN 1+D OUT
IC3005
ADDAT 0:6 7bits
EDA IC3003 To:ECC/DCI
PRE-EQ
LPF
TFIL
1+D
A/D CONV.
VITERBI
A-EQ
ERR DET BUFFER

Q3501,3503
AD CLK
a ADJ b ADJ
Error Timing ADJ Slice Level ADJ DATA DET PB DATA LATCH PB CLK
PC
LPF
VCO Voltage ADJ PS VCO
CK PHASE
PLL Phase ADJ
Fig. 3-12-2 PB EQ block diagram
3-35
3.13 PRE/REC FUNCTION

This IC is a head amplifier for 3 channels, however only 2 channels are used in this unit. During recording, it inputs the recording signal HSE from the EDA IC3003 into Pin 7. At the same time, it also inputs the recording current adjustment value from the EVR into Pin 8. During playback, the playback signal is sent to the PB EQ IC3501 from the Pin 64 AGCOUT. The output from Pin 57 is for ATF. The ATF signal is extracted by the BPF in the PB EQ IC3501. From Pin 59, the ENV_OUT is sent to the JIG connector. 3.13.1 PRE/REC (IC3502) pin assignment
HA2ACFB HA2DET MON2IN
34
PBSW2
VCC3V
HA2FB
HA2IN
RCUR
RECR
RCTL
HID3
HID2
HID1
RECI
48
47
46
45
44
43
42
41
40
39
38
37
36
35
STAB PBEN MMC INSRH EQHLD ENVDET ENVOUT TRICKH ATFOUT ENVCTL HAOUT VCC3V PBOUT AGCIN GND AGCOUT
49 50 51 52 53
LOGIC RA2 HA2
GND
33
PBH
32 31 30 29 28
PBH2 RA2OUT VCC5V RA1OUT PBH1 GND MON1IN VCC3V HA1IN PBSW1 HA1ACFB HA1FB HA1DET VCC5V RA3OUT PBH3
RA1
54 55 56 57 58 59 60 61 62 63 64 AGC DET AGC AMP 3rd AMP LPF 27
ENV DET
MONITOR
26 25 24
HSW HA1
VREF
23 22 21 20 19
RA3 HA3 GCA
18 17
10
11
12
13
14
15
16
RECR1
RECR2
VCC3V
HA3IN
VCC3V
GND
HA3DET
HA3FB
AGCCTL
HA3ACFB
AGCDET
Fig. 3-13-1 PRE/REC (IC3502) pin assignment
3-36
MON3IN
PBSW3
GND
HSE
EVR
3.13.2 PRE/REC (IC3502) pin functions-1/2

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Label AGCCTL AGCDET VCC3V RECR1 RECR2 GND HSE EVR HA3DET HA3FB HA3ACFB PBSW3 HA3IN VCC3V MON3IN GND PBH3 RA3OUT VCC5V HA1DET HA1FB HA1ACFB PBSW1 HA1IN VCC3V MON1IN GND PBH1 RA1OUT VCC5V RA2OUT PBH2 In/Out In In Out In In In In In Out Out Out In In In In In Out Out Out Out Main Vcc 3V Not used GND Not used Rec Vcc 5V CH1 head amp detection CH1 head amp feed back CH1 head amp AC feed back CH1 PB-ON switch CH1 head amp in Main Vcc 3V CH1 REC monitor in GND PB-H1 switch control CH1 REC amp out Rec Vcc 5V CH2 REC amp out PB-H2 switch control Not used AGC CTL AGC DET-C Main Vcc 3V Resistor for Rec GCA Resistor for Rec GCA GND Rec IN Rec GCA adjustment Description
Table 3-13-1 PRE/REC (IC3502) pin functions-1/2
3-37
PRE/REC (IC3502) pin functions-2/2

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND MON2IN VCC3V HA2IN PBSW2 HA2ACFB HA2FB HA2DET RECR RCUR RECI PBH HID1 HID2 HID3 RCTL STAB PBEN MMC INSRH EQHLD ENVDET ENVOUT TRICKH ATFOUT ENVCTL HAOUT VCC3V PBOUT AGCIN GND AGCOUT Label In/Out In In In In In Out In Out In In In In In In In Out Out Out Out In Out In Out Out In Out ATF signal output Not used PB envelope output Main Vcc 3V PB signal out AGC in GND AGC output to PB-EQ Not used GND CH2 REC monitor in Main Vcc 3V CH2 head amp in CH2 PB-ON switch CH2 head amp AC feed back CH2 head amp feed back CH2 head amp detection Resistor for REC monitor REC monitor out REC insert switch PB:H control Head switch 1 Head switch 2 Head switch 3 Rec ON/OFF control ON:H Stand by Not used Capacitor for mono-mulch Insert :H output Not used Description
Table 3-13-1 PRE/REC (IC3502) pin functions-2/2
3-38
3.14 DIGITAL INTERFACE FUNCTION

The digital interface of this unit corresponds to the input/output of the DV terminal (IEEE 1394). The digital interface IC8001 is mounted on one chip with the usual LINK IC and PHY IC. The structure is the same as the previous model, however with the use of the second generation DVC signal processing LSI incorporated from this unit, it eliminates the need for matching the DV BUS data using the gate array as done in the previous model, and the DVS BUS data can be input/output to and from the digital IF IC directly. The MSD IC serves as the host microprocessor. 3.14.1 Digital IF (IC8001) pin assignment
SSP VCC CLK18 VCCB(2/3) NC NC NC NC NC GND SMP BD3 BD2 BD1 BD0 VCCB(2/3) VCC VCCB(2/3) BCLK /DC ALE NC /LCNTD GND AD0 AD1 AD2 AD3 GND AD4 AD5 AD6 AD7 VCCA(2/3) AD8 AD9 21 10 1 22 11 2 36 23 12 3 50 37 24 13 4 51 38 25 5 14 6 15 26 39 52 7 16 27 40 53 8 17 28 41 9 18
GND NC NC NC NC VCC NC NC NC NC GND NC NC NC NC VCC /RST FRP VFRP TEST0 GND TEST1 SI/TEST2 SO SCK VCC /SEN TMS TCK /TRST GND TDI TDO /LISO LLREQ VCC
20 19 35 34 33 32 49 48 47 46 45 62 61 60 59 58 69 68 70 71 72 78 79 80 81 82 88 89 90 91 101 102 103 114 115 116
DVC BUS I/F
ISO Control/ Buffer
m-c o m I/F
ATF ARF
LINK Control (CFR)
LINK
PHY
12 30 31 42 43 44 54 55 56 57 63 64 65 66 67 73 74 75 77 76 87 86 85 84 83 100 99 98 97 96 113 112 111 110 126 125
AD10 AD11 GND AD12 AD13 AD14 AD15 VCCA(2/3) VCC /INTP CYCLEIN NTZIHZ NTOUT GND NTCLK RANEZ LCNA LPWRDN VCC GND DVSS C/LKON LPS CNA TESTM1 TESTM2 /RESET /ISO AVCC PWRDN PLLFLT PLLVDD PLLGND PLLGND XI XO
LD3 LD2 LD1 LD0 LCTL1 LCTL0 LSYSCLK VCC GND DGND DVCC PC0 PC1 PC2 LREQ CTL0 CTL1 D0 D1 SYSCLK DVCC DGND AGND AGND TPBIAS AGND AGND AVCC AVCC CPS R1 R0 TPBTPB+ TPATPA+
127 136 104 117 128 137 92 105 118 129 138 93 106 119 130 139 131 140 120 107 94 141 132 121 108 95 142 133 122 109 143 134 123 144 135 124
Fig. 3-14-1 Digital IF (IC8001) pin assignment
3-39
3.14.2 Digital IF (IC8001) pin functions-1/4

Pin No. 20 19 35 34 33 32 49 48 47 46 45 62 61 60 59 58 69 68 70 71 72 78 79 80 81 82 88 89 90 91 101 102 103 114 115 116 Label GND N.C. N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. VCC /RST FRP VFRP TEST0 GND TEST1 TEST2/SI SO SCK VCC /SEN TMS TCK /TRST GND TDI TDO /LISO LLREQ VCC In/Out In In Out In In In Out In In In In In In Out In Out Description GND Not used Power supply Not used GND Not used Power supply Reset input Frame pulse input Frame pulse output (when DV input) Not used GND Not used Power supply Not used For boundaly scan GND For boundaly scan H:fixed Request signal output to PHY Power supply
Table 3-14-1 Digital IF (IC8001) pin functions-1/4
3-40
Digital IF (IC8001) pin functions-2/4

Pin No. 127 136 104 117 128 137 92 105 118 129 138 93 106 119 130 139 131 140 120 107 94 141 132 121 108 95 142 133 122 109 143 134 123 144 135 124 Label LD3 LD2 LD1 LD0 LCTL1 LCTL0 LSYSCLK VCC GND DGND DVCC PC0 PC1 PC2 LREQ CTL0 CTL1 D0 D1 SYSCLK DVCC DGND AGND AGND TPBIAS AGND AGND AVCC AVCC CPS R1 R0 TPBTPB+ TPATPA+ In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In In In In In/Out In/Out In/Out In/Out Out Out In In/Out In/Out In/Out In/Out Description Not used Data in/out betweem LINK and PHY Control signal in/out between LINK and PHY System clock input from PHY (49.152MHz) Power supply GND GND Power supply Not used Not used Request signal input from LINK Control signal in/out between LINK and PHY Data in/out betweem LINK and PHY System clock output to LINK (49.152MHz) Power supply GND GND Bias supply for DV terminal GND Power supply Not used For bias voltage
DV terminal (twisted pair cable)
3-41

Pin No. 125 126 110 111 112 113 96 97 98 99 100 83 84 85 86 87 76 77 75 74 73 67 66 65 64 63 57 56 55 54 44 43 42 31 30 12 Label XO XI PLLGND PLLGND PLLVDD PLLFLT PWRDN AVCC /ISO /RESET TESTM2 TESTM1 CNA LPS C/LKON DVSS GND VCC LPWRDN LCNA RANEZ NTCLK GND NTOUT NTZIHZ CYCLEIN /INTP VCC VCCA(2/3) AD15 AD14 AD13 AD12 GND AD11 AD10 In/Out In In In In In In Out In In/Out Out In In In Out In In Out In/Out In/Out In/Out In/Out In/Out In/Out Description Clock (24.576MHz) Not used GND Power supply For PLL filter PHY power down mode Power supply Not used PHY reset Not used 1394 connection detect (connected :L) Not used Not used GND GND Power supply Power down mode output to PHY 1394 connection detect input from PHY (connected :L) Not used GND Not used Not used DIF interrupt to MSD IC Power supply Power supply Data/address from/to Host (MSD IC) GND Data/address from/to Host (MSD IC)
3-42

Pin No. 18 9 41 28 17 8 53 40 27 16 7 52 39 26 15 6 14 5 25 38 51 4 13 24 37 50 3 12 23 36 2 11 22 1 10 21 Label AD9 AD8 VCCA(2/3) AD7 AD6 AD5 AD4 GND AD3 AD2 AD1 AD0 GND /LCNTD N.C. ALE /DC BCLK VCCB(2/3) VCC VCCB(2/3) BD0 BD1 BD2 BD3 SMP GND N.C. N.C. N.C. N.C. N.C. VCCB(2/3) CLK18 VCC SSP In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In In Out In In/Out In/Out In/Out In/Out In/Out In In Description Data/address from/to Host (MSD IC) Power supply Data/address from/to Host (MSD IC) GND Data/address from/to Host (MSD IC) GND Not used Not used Address lutch enable Access completion signal to Host (MSD IC) System clock from MSD IC Power supply Power supply Power supply DV-BUS data DV-BUS start mark pulse GND
Not used
Power supply System clock input 18MHz Power supply DV-BUS sector start pulse
3-43
3.15 MONITOR FUNCTION

R G B
IC7403
CS CLK DI DO EA0 ECL B-Y IN R-Y IN
IC7201
BLKLIM
RGB OUT to VF&MONI
IC7203 SUB TG MONI VF
EPROM EVR
ADJ
SYNC Y IN
VF:H /MONI:L
RPD
Y IN
CKI
RPD
VF ON:L
MONI ON:L
VCO
IC7411 D7401,L7401 11.06MHZ (*10.97MHz)
VCO
IC7410 D7201,L7201 16.52MHZ (*16.41MHz)
PLL ADJ
Fig. 3-15-1 LCD driver block diagram The LCD DRIVER IC7201 is a one chip IC mounting the RGB recorder, driver functions, and the timing generator for panel driving. The video signal inputs that can be used include the composite input, Y/C input, and Y/color difference input. In this unit, the Y/color difference input is used. The input method is selected by the Pin 8 MODE2. NTSC/PAL is switched by the Pin 7 MODE1.
MODE1 H M L MODE2 H Composite input M Y/Chroma input L Y/C input
NTSC D-PAL SPAL
IC7201 drives both the VF and monitor, but the monitor drive pulse is converted to the drive pulse for the high picture quality LCD panel adopted in this unit by the sub timing generator IC7203. To obtain accurate timings, a phase comparator and frequency counter are incorporated. By connecting an external VCO, PLL operations can be performed. The VCO center frequency differs between the VF and monitor and so the two VCOs are used alternately (for VF: variable cap D7401, L7401, and IC7411/ for MONITOR: variable cap D7201, L7201, and IC7410). The internal timing generator is switched for VF or monitor by selecting the Pin 19 SLCK input. During the L/R reversal of the monitor, the HST1, HCK1, and HCK2 timings and internal sampling hold pulse timings are switched by the selection of the Pin 34 RGT.
SLCK: Driving LCD select L MONITOR H VF VF: VCO center frequency NTSC 11.06MHz PAL 10.97MHz M O N I T O R : V C O center frequency NTSC 16.52MHz PAL 16.41MHz
RGT: Horizontal scanning direction H Normal scanning L Reverse scanning
3-44
The 3-state detection circuit (IC7401/IC7402) converts the H/M/L tertiary information sent from the SYSCON CPU into two H/L binary information.
IC7401 VF : L MONI : L MONI+BL : H IC7402 UP/DOWN + L/R: H UP/DOWN : L NOMAL : L
BackLight ON/OFF Control
L/R Control
IC7406 VF ON/OFF Control VF ON : L UP/DOWN Control
VF : H MONI : L MONI+BL : L L : VF ON M : MONI H : MONI+BL
UP/DOWN + L/R : L UP/DOWN : L NOMAL : H
L : UP/DOWN + L/R PLAY Mode E-E Mode (Mirror Mode) M : UP/DOWN H : NOMAL
Fig. 3-15-2 3-state detection circuit The RGB signal output is reversed every 1H as shown in the following diagram by the internal POL SW. It is then feed back so that the center voltage of the output signal matches the reference voltage Vcc2 /2. The white level output is clipped at the Vsig center voltage level, while the black level output is adjusted by the Pin 46 BLKLIM, and clipped at the limiter operating point.
Video IN
FRP Black Level Limit
RGB OUT
Vsig Center Voltage
Black Level Limit
Fig. 3-15-3 RGB output waveform The adjustment values are output from IC7403. IC7403 is an IC which is incorporated with both the EEPROM and EVR. The EEPROM is memorized with both the VF adjustment data and monitor adjustment data. The adjustment data is selected by Pin 21 EA0 (VF: H/ MONI: L). The Pin 16 ECL is input with one pulse each time the VF and monitor are switched. And each time, the adjustment value of the VF or monitor is output according to this pulse.
3-45
3.15.1 LCD driver (IC7201) pin assignment

BLKLIM G_OUT R_OUT
B_OUT
FB_G
GND2
VCC1
VCC2
FB_R
FB_B
REG
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
B-YIN R-YIN COUT RST/TINT COLOR XVXO R_BRT B_BRT RGBGAIN GAMMA2 GAMMA1 BRIGHT CONT C_IN R_GAIN B_GAIN
VDD
33
RGT
NC
NC
NC
49 50 51 52 53 54 55 56 57 58 CLAMP
1/2 Vcc2
32 31
NC VD HD HCK1 HCK2 HST1 HST2 CLR EN VCK1 VCK2 VST1 NC SLCK TEST0 TEST1
B-Y R-Y Y MATRIX SUB BRIGHT RGB CONT RGB GAIN POL SW H-CTL H-POS TIMING PLS GEN
30 29 28 27 26 GAMMA FIELD& LINE CTL ELIM/ MODE 25 24 V-CTL V-POS TIMING PLS GEN VSYNC SEP 23 22 21 20 PLL COUNT 19 18 MODE SELECT PLL PC M CK SUB CK 9 10 11 12 13 14 15 16 17
SUB CONT
BRIGHT
S/H 59 60 61 62 63 64 AGC CLAMP EXT SW
PIC CONT SYNC SEP HSYNC DET
AGCADJ
EXT_R
EXT_B
Y_IN
GND1
RPD
VSS
EXT_G
CKI
SYNC
MODE1
MODE2
AGCTC
CKO
Fig. 3-15-4 LCD driver (IC7201) pin assignment
3-46
TEST2
PICT
3.15.2 LCD driver (IC7201) pin functions-1/2

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Y IN AGCADJ AGCTC PICT GND1 MODE1 MODE2 EXT-R EXT-G EXT-B RPD VSS CKI CKO TEST2 TEST1 TEST0 SLCK NC VST1 VCK2 VCK1 EN CLR HST2 HST1 HCK2 HCK1 HD VD NC Label SYNC In/Out In In In In In In In In In Out In In Out Out Out Out Out Out Out Out Out Out LCD panel select (H:VF /L:MONI) Not used Vertical start pulse output Vertical clock pulse 2 output Vertical clock pulse 1 output Gate select pulse enable Uniformity pulse output Not used Horizontal start pulse output Horizontal clock pulse 2 output Horizontal clock pulse 1 output HD pulse output VD pulse output Not used Not used PLL phase comparison GND Clock input (VF:11.06MHz /MONI:16.52MHz) Not used On-screen input Y signal input for sync Y signal input AGC level adjustment AGC time constant Picture control (sharpness) GND Mode select (H:NTSC /M:DPAL /L:SPAL) Mode select (H:composite /M:Y,Chroma /L:Y,C) Description
Table 3-15-1 LCD driver (IC7201) pin functions-1/2
3-47
LCD driver (IC7201) pin functions-2/2

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VDD RGT NC NC NC GND2 R OUT FBR G OUT FBG B OUT FBB VCC2 BLKLIM VCC1 REG B-Y IN R-Y IN C OUT RST/TINT COLOR XVXO R-BRT B-BRT RGB GAIN GAMMA2 GAMMA1 BRIGHT CONT C IN R GAIN B GAIN Label In/Out In Out In Out In Out In In In In In In In In In In In In In GND R output R DC voltage feed back G output G DC voltage feed back B output B DC voltage feed back Power supply analog 10V Black peak limit level adjustment Power supply analog 3.5V Capacitor for regulator B-Y input R-Y input Not used Not used Not used Not used R brightness adjustment B brightness adjustment RGB gain adjustment Gamma 2 adjustment Gamma 1 adjustment Brightness adjustment Contrast adjustment Not used R gain adjustment B gain adjustment Not used Power supply digital 3.5V H:normal scan /L:reverse scan control Description
Table 3-15-1 LCD driver (IC7201) pin functions-2/2
3-48
3.15.3 LCD SUBTG (IC7203) PIN ASSIGNMENT
NTPAL VDI HDI ENI CLRI HCK1I VSTI HSTI XCLR VSS
1 2 3 4 5 6 7 8 9 10
PAL PULSE ELIMNATOR FIELD & LINE CONTROLLER DECODER & V-TIMING PULSE GENERATOR DECODER & H-TIMING PULSE GENERATOR V-POSITION COUNTER H-POSITION COUNTER
20 19 18 17 16 15 14 13 12 11
VDD XHST XVST EN XEN PCG XPCG HFRP LFRP FRPI
Fig. 3-15-5 LCD SUBTG (IC7203) pin assignment 3.15.4 LCD SUBTG (IC7203) pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Label NTPAL VDI HDI ENI CLRI HCK1I VSTI HSTI XCLR VSS FRPI LFRP HFRP XPCG PCG XEN EN XVST XHST VDD In/Out In In In In In In In In In In Out Out Out Out Out Out Out Out Description NTSC:H /PAL:L select VD pulse input HD pulse input Gate select pulse enable Uniformity pulse input H clock pulse 1 input V start pulse input H start pulse input System clear (L:clear) GND Pulse input for alternating current drive Not used Pulse output for alternating current drive Uniformity pulse output (inverted PCG) Uniformity pulse output Gate select pulse enable output (inverted EN) Gate select pulse enable output V start pulse output (inverted VST) H start pulse output (inverted HST) Power supply
Table 3-15-2 LCD SUBTG (IC7203) pin functions
3-49
3.16 MIC CIRCUIT

FRONT F PS R-ch
L-ch
R-ch
C PS
R F L-ch
C
R2612 4.7k Q2601 10k Q2602 R2611
R
R2613 4.7k
C2610 0.047 or OPEN R2614 4.7k
Fig. 3-16-1 Triangle microphone As the previous pocket type movie's microphone was attached to the top of the unit, directivity was difficult to grasp from the front. In this unit, three microphones are arranged triangularly, and the front directivity has been improved sharply by vector calculation. As shown in the figure, the microphones are located at the front F, rear R, and center C and the phase of the difference in the time to reach the microphone from the L and R is shifted and added to create the L-ch and R-ch audio signal. Phase shift (PS) is performed by the capacitor C2610 in the microphone input circuit as shown in the figure. At phase shifted line, 0.047 mF is input to C2610 while those which are not, the status is OPEN.
3-50
3.17 SYSCON CPU

3.17.1 SYSCON CPU (IC1001) pin functions-1/4
Pin No. 15 29 2 42 16 56 3 43 4 57 5 31 18 44 6 58 19 45 33 46 20 7 59 8 34 21 47 22 48 10 35 23 9 30 32 51 Label S_OPEN S_CLOSE AD0 AD1 AD2 AD3 VDD VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 PWR_CTL M16_RDY AD11 AD12 AD13 AD14 AD15 MODE0 MODE1 MODE2 M16_CS CLK_4MHz F/Z_CS VDD OSCI OSCO VSS VSS VSS VSS VSS In/Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Address/data MPX BUS 16bits from/to YMCA IC4301 In/Out In/Out In/Out Out In In/Out In/Out In/Out Address/data MPX BUS 16bits from/to YMCA IC4301 In/Out In/Out In In In Out Out Out In Out GND GND AL3V MSD IC1401 chip select Not used F/Z DRIVER IC4851 chip select Power supply System clock (16MHz) System clock (16MHz) GND GND GND GND GND Power control to REG section MSD IC1401 READY Power supply GND Address/data MPX BUS 16bits from/to YMCA IC4301 Description Lens cover open control forward Lens cover close control reverse
Table 3-17-1 SYSCON CPU (IC1001) pin functions-1/4
3-51

Pin No. 142 37 36 38 49 50 60 63 62 64 73 77 75 76 74 90 86 89 88 101 100 102 99 103 114 116 113 115 128 127 129 140 141 165 159 117 VSS FLDFMC BATT_DOWN RST PIT V_MUTE JLIP_INT VD OMT EXTINDET MENU_P_A FRP RTC_INT TNW AH_CTL1 AH_CTL2 OSD_CS EEPROM_CS VDD TIMER_OUT TALLY CHG_CTL P_DET REMOTE S_DT_IN S_DT_OUT S_CLK VF_CTL OSD_DATA OSD_CLK RXD TXD AUDIO_CS AVDD AVDD VDD Label In/Out In In In In Out In In In In In In In In Out Out Out Out Out Out Out In In In Out Out Out Out Out In Out Out GND Field distinction Battery down detect Reset Docking station detect Video mute JLIP interrupt Verticl drive pulse EIS data read timing EXT_DC detect Menu dial pulse A Frame reference pulse Clock 1 second interrupt FMC busy Jack select Jack select OSD IC1002 chip select EEPROM IC1003 chip select Power supply Not used Tally LED on/off control Charge control Plug detect Remote input Serial data input from MSD, EEPROM, RTC Serial data output to MSD TG CDS/AGC EEPROM DAC RTC Serial clock VF back light OSD data OSD clock RS232C data input RS232C data output AUDIO IC2201 chip select Power supply Power supply Power supply Description
3-52

Pin No. 87 61 136 125 153 139 166 126 152 112 151 138 164 111 163 137 150 124 162 110 149 123 135 122 148 109 161 160 134 147 121 146 133 158 132 145 VDD VDD AVSS AVSS RESERVE4 AFZ_DATA AFZ_CLK VDD VSS AVSS VRefL BATT_CHK KEY_A KEY_B ZOOM_SW IR_DA HALL_AD Z_PTR_AD F_PTR_AD TG_CS CDS/AGC_CS AVH_DET BATT_SW RESERVE2 MONI_RVS VRefH AVDD WB_IR_DET M16_RST BUZZER MENU_SET_SW RTC_CS DAC_CS LWE HWE RE Label In/Out Out Out In In In In In In In In Out Out In In In In Out Out In Out Out Out Out In Power supply Power supply GND GND Not used Serial data output to AUDIO FZ_MDA Serial data clock AUDIO FZ_MDA Power supply GND GND ADCGND Battery DC input Deck operation switch input Camera operation switch input Zoom switch input AWB IR sensor AD input Iris motor hole generator AD input ZOOM position sensor AD input FOCUS position sensor AD input TG IC5002 chip select CDS/AGC IC5601 select Plug detect input AV:H HP:L Battery detect Not used LCD monitor reverse switch ADC Power supply Flicker detect Reset for MSD IC1401 Buzzer signal output Menu set switch RTC IC1004 chip select EVR/DAC IC3503 chip select Write enable Write enable Read enable REG3V Description
3-53

Pin No. 107 54 39 119 131 120 130 108 118 106 105 95 104 93 91 94 92 82 78 81 79 68 67 69 66 80 65 55 52 40 53 41 26 28 27 17 Label VDD(VPP) VDD(VPP) VDD ALE VDD VSS DIAL_5S DIAL_ST DIAL_MANU DIAL_AUTO DIAL_OFF DIAL_PLAY EJECT_SW CAS_SW MONITOR_SW VF_SW MENU_P_B RESERVE3 SHUT_RST 74_RST F/Z_RST M_U/D_LR1 M_U/D_LR2 BK_L_CTL1 BK_L_CTL2 VDD(VPP) IRIS_O/C Z_LED F_LED SMUTE S_SPK_ON RESERVE1 FADE_H AFADER A_MUTE VDD In/Out Out In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Power supply Power supply Power supply Address latch enable Power supply GND Dial switch 5S position Dial switch ST position Dial switch MANU position Dial switch AUTO position Dial switch OFF position Dial switch PLAY position Eject switch Cassette switch LCD monitor switch VF switch Menu dial pulse B Not used Reset for YMCA IC4301(shutter sound section) Reset for YMCA IC4301 Reset for F/Z DRIVER IC4851 LCD monitor control (up/down,L/R) 3-state output H:NORMAL M:PLAY MODE(U/D) L:EE MODE(U/D+L/R) Back light contrlo 3-state output H:monitor+backlight M:monitor L:VF on Power supply Zoom wide end sensor LED control Focus infinity sensor LED control Shutter sound mute Speaker on/off control Not used Pulse at fader end During fader:H output Audio mute Power supply Description
In/Out IRIS open/close
3-54
3.18 MSD CPU

3.18.1 MSD CPU (IC1401) pin functions-1/4
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Label VSS HLDA HOLD RESET MOD0 MOD1 VCC VSS VPP ADC_DEM0 ADC_DEM1 ADC_PWD0 ADC_PWD1 DIC_STP1 DIC_STP2 TRIG_OUT P97 VSS OSCVCC XIN XOUT OSCVSS VSS VCC P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 In/Out In Out Out Out Out Out In/Out Out In Out Description GND Not used H:fixed Reset input from SYSCON CPU L:fixed H:fixed Power supply GND Power supply REG 5V Sampling frequency select to AUDIO AD/DA IC2101 ADC_DEM0/ADC_DEM1:frequency (L/L:44.1k, L/H:48k, H/L:OFF, H/H:32k) D/A power control power down:L to AUDIO AD/DA IC2101 A/D power control power down:L to AUDIO AD/DA IC2101 Serial communication enable to DVIO IC3202 Communication start/stop signal to/from CAS IC3001 Remote signal output Not used GND Power supply X'tal 27MHz X'tal 27MHz GND GND Power supply
Not used
Table 3-18-1 MSD CPU (IC1401) pin functions-1/4
3-55
MSD CPU (IC1401) pin functions-2/4

Pin No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Label P117 VCC VSS VCC CAM0 CAM1 CAM2 REC_SAFE REEL_LED RF_TRICK RF_FAST RF_STAB VCC VSS DRUM_FG CAP_FG TSR HID SPA T_REEL S_REEL SSP FRP MCVS PWMO VSS VCC DIC_RST LD_ON CAP_BRK TXD RXD MDA_CS MDA_CLK MDA_IN MDA_OUT DIF_RST DIC_CLK DIC_IN In/Out In In In In Out Out Out Out In In In In In In In In In In In Out Out Out Out Out Out In Out Out Out Description Not used Power supply GND Power supply Mechanism position detect from rotary encoder Rec safety switch Reel sensor LED control Slow/still:H (for EQ PLL gain adjust ) PB EQ Search:H (for EQ PLL gain adjust ) PB EQ Safety tab (REC prohibition) to PRE/REC IC3502 Power supply GND Drum FG Capstan FG HID reference (drum 150Hz) Head switch pulse ATF sample pulse TU reel pulse SUP reel pulse DVC bus sector start signal from CAS IC3001 Frame reference pulse from DVIO IC3202 1394 frame reference pulse from DVIO IC3202 PWM output for audio PLL GND Power supply Reset output to CAS, EDA, DVIO Loading motor ON/OFF control Capstan motor brake control Not used MDA IC1601 chip select Serial clock to MDA IC1601 Serial data output to MDA IC1601 Serial data input from MDA IC1601 Reset to DIF IC8001 Serial clock to CAS IC3001, DVIO IC3202 Serial data output to CAS IC3001, DVIO IC3202
3-56

Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Label DIC_OUT MREADY SYS_CLK SYS_IN SYS_OUT VCC VSS DIF_INT P55/INT3 P56/INT2 P57/INT1 MSELECT NMI DRUM_REF CAP_REF V_PLL A_PLL MIC_CTL MIC_SDA MIC_SCK FRP TAPE_LED VSS VCC P72/TA2 P73/TB2 P74/TA3 P75/TB3 P76/TA4 P77/TB4 P84/TA5 P85/TB5 P86/TC5 P87/ADTRG AVSS AN12 AN11 AN10 BCID3 In/Out In Out In Out In In In In Out Out Out Out Out Out Out In Out In Description Serial data input from CAS IC3001, DVIO IC3202 Serial bus ready to SYSCON CPU IC1001 Serial clock to SYSCON CPU IC1001 Serial data output to SYSCON CPU IC1001 Serial data input from SYSCON CPU IC1001 Power supply GND DIF interrupt from DIF IC8001 Not used MSD chip select input from SYSCON CPU IC1001 H:fixed Drum offset voltage output to MDA IC1601 Capstan offset voltage output to MDA IC1601 PLL output to PLL IC3201(18MHz when 1394 input) Audio PLL output (PWM) to PLL IC3201 For memory in cassette only information of recorded or brand-new tape Frame reference pulse from DVIO IC3202 Tape LED control GND Power supply
Not used
GND Not used Cassette tape ID board information
3-57

Pin No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Label BCID2 BCID1 AN06 AN05 AN04 AN03 DEW_SENS E_SENS S_SENS AVREF AVCC VCC2 VSS AGC_RST BCLK DC R/W ALE RD BLW BHW D00 D01/A16 D02/A17 D03/A18 D04/A19 D05/A20 D06/A21 D07/A22 D08/A23 D09/A24 D10/A25 D11/A26 D12/A27 D13/A28 D14/A29 D15/A30 VSS VCC2 In/Out In In In In In Out Out In Out Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Description Cassette tape ID board information
Not used Dew sensor detect End sensor detect Start sensor detect Reference Voltage 1/2VCC Power supply Power supply REG 2.2V GND Reset to VIDEO OUTPUT DRIVER IC3701 System clock 13.5MHz to DIF IC8001 Access comletion signal from DIF IC8001 Not used Address latch enable Read strobe to EDA IC3003 Write strobe to EDA IC3003 Not used
Data (16 bits) /address (15 bits) from/to EDA,DIF
GND Power supply REG 2.2V
3-58
3.19 MDA FUNCTION

3.19.1 MDA (IC1601) pin assignment
DRUM_PWR VCC UNREG DCC1 DCC2 DCC3 DCC
D.VM D.UH D.U
UPPER/LOWER DIVISION
D.UIN
DRIVE SIGNAL LOGIC
D.VH D.V
D.VIN
D.WH D.W
D.WIN D.COM
IC1602
D.OSC
OSC
START TIMING
D.GND
DRUM.M
D . F G-
D. BRK D.EC D.ECR TORQUE CTL
BRAKE
D.PG-
DRUM_REF REG_5V
D . F G P G+ CURRENT FEED BACK D.PG.SM UNREG L.REF
DRUM_FG DRUM_PG
D.FGSOUT D.PGSOUT
L.FWD MDA_CS MDA_CLK MDA_IN MDA_OUT CS CLK DIN DOUT
SHIFT REGISTER & LATCH
C.FR C.MODE C.TL D.PG.SM D. BR K L.FIN L.RIN PW_SAVE
POWER SAVE
CTL LOGIC
L.REV L . GN D
LOAD.M
PW_SAVE
L.FIN
L.RIN
D . F GD . F G+
REG_5V DRUM_FG
C.FR
DIRECTION UPPER/LOWER DIVISION
C.VM C.UH C.U
CAP_PWR
HALL
C. HU+ C.HU-
DRIVE SIGNAL LOGIC
C.VH C.V
HALL
C. HV+ C.HV-
C.WH C.W
HALL
C.HW+ C.HW-
IC1603 CAP.M
C.RCC
RIPPLE CANCEL
C.EC C.VS C.MODE C.VM C.MODE
C.GND
CAP.M
CAP_REF REG_5V
C.EC C.ECR TORQUE CTL
CAP_ERR
DC/DC
C.TL C. BRK
CURRENT LIMIT BRAKE
CAP_BRK
Fig. 3-19-1 MDA (IC1601) pin assignment

3-59
3.19.2 MDA (IC1601) pin functions-1/2

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Label GND1 D.U D.VM D.V D.RNF L.REF D.W L.FWD GND2 L.GND NC UNREG L.REV C.U NC C.RNF C.V C.VM C.W C.CH C.VH C.WH C.HWC.HW+ C.HVC.HV+ C.HUC.HU+ C.FGSOUT C.FGOUT C.FGC.FG+ VCC C.VS C.PCV C.PCI C.ECR C.EC C.RCC C.BRK In/Out Out In Out In Out Out Out Out Out In Out Out Out Out In In In In In In Out Out In In In In In In In In In Description GND Drum motor output Drum power Drum motor output Drum GND (current detect resistor) Loading motor output reference voltage Drum motor output Loading motor output GND Loading motor GND Not used Power for load motor driver, drum BEMF comparater (REG 5V) Loading motor output Capstan motor output Not used Capstan GND (current detect resistor) Capstan motor output Drum power Capstan motor output Capstan motor output (pre-drive)
Capstan motor holl signal input
Capstan FG output Capstan FG amp. Output Capstan FG input Power supply Capstan motor power control Terminal for prevent saturation Terminal for prevent saturation Capstan torque reference Capstan torque control Capstan ripple cancel Capstan brake :H
Table 3-19-1 MDA (IC1601) pin functions-1/2
3-60
MDA (IC1601) pin functions-2/2

Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Label NC CLK CS DIN DOUT D0 D1 D2 D3 D4 GND2 NC D.EC D.ECR D.PCI D.PCV D.OSC START DETECT TEST1 TEST2 D.PGSOUT D.PGOUT D.PGD.FGPG+ D.FGD.FGOUT D.FGSOUT GND1 D.UIN D.VIN D.WIN D.COM DCC3 DCC2 DCC1 DCC D.UH D.VH D.WH In/Out In In In Out In In In In In In In Out Out In In In Out Out In In In In Out Out Out Description Not used Clock input Chip select input Serial data input Serial data output
Not used
GND Not used Drum torque control Drum torque reference Terminal for prevent saturation Terminal for prevent saturation Drum osc Drum start mode time setting Drum detect mode time setting Not used Drum PG output Drum PG amp output Drum PG input Drum FG/PG common input Drum FG input Drum FG amp output Drum FG output GND Drum BEMF comparater input Drum motor common Drum slope shape Drum current control Drum motor output (pre-drive)
Table 3-19-1 MDA (IC1601) pin functions-2/2
3-61
SECTION 4 ERROR RATE ADJUSTMENT

PB EQ (Error Rate) Adjustment Error rates can be checked on the screen of service support software beginning with the GR-DVM5. (However while the Error Rate is displayed, the time code of the monitor onscreen will stop at the value just before and operations will stop.) Adjustment procedures and contents are the same as before. But when PB EQ (error rate) adjustment is selected, the following Error Rate screen appears. The following describes the displays.
The error rate is displayed in this box which is the total number of both channel, and next boxes are separate numbers of CH1 and CH2. These numbers will be updated every second. The A V means audio and video, usually the error rate represents the total number of audio and video sections, same number as using the error rate JIG. When the viterbi is switched on or off, " Error " is appeared in the box momentarily, that is normal.
These six items are new function. The error rate of audio and video part can be shown individually. It is easy to understand what proportion of audio and video in the total error rate, therefore it will be able to use for judgment of tape pass problem.
fig.1
This bar display is imaged the pattern of tape, that is useful for judgment of tape problem such as block noise. Sync block numbers of each area will be shown in percentage and color. Ordinarily, it will become O K and B L U E that sync block will be detected perfectly (100%). If they become other than B L U E as fig.2, that may be caused by tape pass, tape damage or off adjustment of PB EQ seriously. It is necessary to check them if there is not B L U E area, even if the error rate values are less than the specified value.
fig.2
4-1
VITERBI ON/OFF Even during PB EQ (error rate) adjustment, viterbi ON/OFF instructions will be given, the GR-DVM5 automatically turns On the viterbi when playback starts (from the stop state) for both SP/LP. When stopping, viterbi goes off. In other words, even if viterbi is turned off using the Fig. 3 menu during playback, it will turn on in playback after. This will require the viterbi to be turned off again.
When the unit is going to playback from stop mode, the VITERBI mode will be switched to ON automatically, even if display remains O F F here. Therefore, in order to make VITERBI off mode, it is necessary to select again after playback.
fig.3
ATF ON/OFF In the ATF OFF state, the 0.13 mm tracking can be shifted for every 01h using the editor shown in Fig. 5. Previously, 80h was the center position and the shift was greatest at 00h and FFh. But with GR-DVM5, the center has been changed to 00h and FFh. In this case, the shift is the greatest at 80H.
After select ATF OFF, the Editing window will appear as fig.5.
fig.4
The center position is 00h or FFh. The default value is 00h.
fig.5
4-2
VICTOR COMPANY OF JAPAN, LIMITED
Printed in Japan 9903 (TM1)

JVC Gr-dvm5 Technical Guide

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VIDEO TECHNICAL GUIDE

DIGITAL VIDEO MOVIE

COPYRIGHT 1999 VICTOR COMPANY OF JAPAN, LTD.

SECTION 1 OUTLINE OF THE PRODUCT

Continuous shooting time: 40 min. (When LCD is used)

(When VF is used) Continuous shooting time: 80 min. (When LCD is used)

Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-1/4

Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-2/4

No (With lens protection glass)

1/4" 460k (540k) pixels Effective aria 290k (350k) pixels

Progressive scanning Electric Image Stabilizer Sensitivity

No Excess pixel method 7 lux (Shutter 1/30 seconds) F1.6 f=4.5 to 45 mm

Lens specification Zoom Ratio

Optical zoom: 10x Electronic zoom: 2x/10x Total zoom: 100x

Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-2/4

Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-3/4

Snapshot in Playback Zoom in Playback Auto flash LP mode

Yes (Excluding negative-positive) (Maximum 10 times) No

By main unit/remote control unit No No

No Docking station is not required

Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-3/4

Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-4/4

Software JLIP ID number Remote control sensor

Power ON/OFF button in Remote control unit

System backup button battery

Table 1-1-1 Table list differing points between models (GR-DV1/GR-DVM1/GR-DVX/GR-DVL9000/GR-DVM5/DV3)-4/4

SECTION 2 OPERATION OF MECHANISM

MOTOR BRACKET ASSY (MODE CONTROL MOTOR)

MAIN DECK (RELAY GEAR)

MAIN CAM [Refer to 2.1.2]

SLIDE LEVER ASSY

SLIDE GUIDE PLATE

PAD ARM ASSY

LOADING BRAKE ASSY

SLIDE DECK ASSY

BRAKE CONTROL ASSY

CHARGE ARM ASSY

CONTROL PLATE ASSY GUIDE ARM ASSY

CATCHER (T) ASSY

PINCH ROLLER ARM ASSY [Refer to 2.1.5]

CASSETTE HOUSING ASSY (RELEASE LEVER)

CATCHER (T) ASSY

SLANT POLE ARM ASSY

SUB BRAKE ASSY

CLEANER ARM ASSY

Fig. 2-1-1 Loading operation chart

To control the TC lever assembly [M3-433]

To control the Slide lever assembly [M3-426]

Fig. 2-1-3 Sub cam

2.2 OPERATION OF MECHANISM

Mechanism mode timing chart

Main Cam Sub Cam Encoder Cam SW1

Slide Lever Assy

Loading Brake Assy

Sub Brake Assy (TU Brake)

Pinch Roller Arm Assy

Pad Arm Assy (SUP Brake)

Main Cam Sub Cam Encoder

Fig. 2-2-1 Mechanism mode timing chart

SECTION 3 CIRCUIT DESCRIPTION

Fig. 3-1-1 Optical black diagram

3.1.1 CCD pin assignment

Fig. 3-1-2 CCD pin location 3.1.2 CCD pin functions