Daisuke Miyazaki, Masanori Furuta and Shoji Kawahito,

Research Institute of Electronics, Shizuoka University, 3-5- 1,Johoh, Hamamatsu, Japan. Tel:+S 1-53-478- 1342 FAX:+S 1-412-5481 (dmiya,mfuruta,kawahito}@idl.rie.shizuoka.ac.jp Abstract: This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADCs. Capacitor mismatch, gain and offset errors are measured by a technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3 pm 2-poly 3-metal CMOS technology. The lObit 120M Samplels ADC achieves 0.14LSB of DNL and 0.SLSB of INL with very lowpower dissipation of 75mW at 2V.

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Fig. 1 4-parallel pipeline ADC.

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1. Introduction
System LSIs for visual applications and communications require high-speed low-power highresolution analog-to-digital converters(ADCs) in CMOS technology. Parallel or time-interleaved pipeline architecture is an effective way to achieve high-speed ADCs with low-power consumption[l][4]. However, offset and gain mismatches between the individual ADC channels and capacitor mismatches in each ADC channel degrade the SNDR of the ADC. The effort to achieve high precision in the analog ADC design leads to the increase of power dissipation. This paper presents a 4-channel lOhit parallel pipeline ADC based on a totally low-power design. In the pipeline ADC core, a pseudo-differentiai pipeline ADC architecture[Z] is used for low-power high-speed operations. A new digital calibration technique[3] without any additional analog circuits on the ADC chip is applied to correct offset and gain errors between channels, as well as capacitor mismatches. Previous digital calibration approaches[5][6][7] require the additional on-chip analog circuits for the measuement of the mismatch errors. The digital calibration is effective for reducing the power dissipation because the requirement of analog precision is relaxed. Though, a sophisticated digital calibration technique for the interleaved pipeline ADC is reported[7], it is not intended for low-power design. The implemented ADC demonstrates that the thorough use of digital error corrections is effective for the low power design of highspeed ADCs.

Fig.2 Block diagram of the pseudo differential ADC. 2. Architecture and Digital calibration method 2.1 Low-power pseudo-differential pipeline ADC Figures 1 and 2 show the block diagram of the designed 4-channel parallel pipeline ADC. Each chamel consists of 11 1.5hit pipeline stages and has a 12bit equivalent digital code. The additional 2bits are used for digital calibration. Each stage consists of a 1.5b subADC, a 1.5h D/A converter P A C ) , and multiply-by-two amplifiers. The pseudo differential architecture is effective for reducing the DC bias current of amplifiers while maintaining a high switching speed by using a wide-hand single-ended amplifier. The operation of the pseudo-differential multiply-by-two stage is almost same as that of a differential scheme, except that a pseudo differential stage amplifies common-mode input variations. To avoid this problem, fully differential amplifiers are used for the 3rd and the 7th multiply-bytwo stages as shown in Fig. 2. The pseudo-differential ADC is modified from reference [2] to achieve better input common-mode rejection by using the fully-differential input sampleand-hold(S/H) circuit. Figures 3 and 4 show the

719

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simplified scheme of skew insensitive interleaved S/H circuits and its sampling timing diagram, respectively. Bootstrapped switches are employed for the input. Clock pulses connected to gates of all the other switches are boosted twice the supply voltage. A global sampling clock(CKgs) is used for the skew insensitive sampling. The clocks CKI and CK2 are generated from a clock generator and may have a large skew. In the proposed bootstrapped clock generator, the fall timing of C h i for the transistor MI of all the ADC channels is determined by the global sampling clock CKgs. Though the threshold voltage deviations(d Vlh) of MI and M4 may cause a small skew of few picc-second, the proposed sampling network has much less sensitively to the clock skew than the conventional sampling circuits without the global sampling clock.

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Figure 5 shows a simplified block diagram of an error analysis model of each N-bit pipeline ADC. The coefficients a, and b. are the gain errors and the offset errors, respectively, in the S/H circuits and the MBT's. The digital correction is performed by subtracting the in digital digital approximated coefficients domain[3][5][6]. The digitized error in the i-th stage E, is approximately expressed given by

E, = AiX i - DiAi + 2Bi

(1)

where Ai and B j are digitized values of a; and b , respectively and Xi is a digitized value of x;. The error is measured using an INL plot for a ramp signal. There is no need for on-chip error measurement circuits. Each error in digital domain,(A,BJ, i=l,....M is determined using a cost function calculated from the mean square of the INL plot. The ML plot is obtained by giving a ramp signal to the ADC input using a highresolution DAC in a signal generator (SG). The cost function is given by

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Fig.3 Simplified skew insensitive SiH circuit

where 1NL; is the integral nonlinearity of the i-th digital code. For the determination of the gain error of the k-rh stage, Ah is considered here as an example. In the measurement of lNL by using the ramp signal, the offset error is cancelled. Therefore, the equation (1) is rewritien as Ei=AX,-D& In this case 7 as a function of Ah is calculated using continuous integral as

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Fig.4 Timing diagram of skew insensitive S/H circuit. if other error are negligible, where r=y-'and

2.2 Digital correction and Error measurement method for digital calibration

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If the ADC to be calibrated has the gain error of A, , and

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Fig.5 Block diagram of 1.5bit /stage algorithmic ADC(C: Comparator, MBT: multiply-by-two amplifier).

where akis a factor due to other errors. Because the cost function has a parabolic relation, it is easy to fmd out the gain error using three points of A f ' . For example, if the estimation points are chosen at A, A and 2A, the gain error is calculated by[3]

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3AX(V(A)-V(-A)) , 2(377(e)(A)-q7(C)(-A)-?77(C) (2A))

(5)

Similarly, the other errors can be obtained using this procedure.

3. Experimental Result A prototype chip is implemented in a 0 . 3 p 2-poly 3metal CMOS technology. The chip photograph is shown in Fig. 7. The ADC core area including digital correction logic is 5.0 mm x 6.0 mm. The power dissipation of the analog core is measured to be 6oinW at a supply voltage of 2V and a sampling frequency of 120MHz. All digital logics without PAD drivers consume about 14.5mW. The total is about 75mW.

Figure 9 shows the DNL and INL plot of the implemented 4-channel pipeline ADC at l20M Sample/s for DC inputs after digital calibrations. The offset and gain between the channels and capacitor mismatch errors in each channel are corrected. The DNL and INL are less than O.2LSB and 0.6LSB, respectively. Figures 10 and 11 show the 4096 point FFT spectrum of the 4-channel pipeline ADC at lOOM Sampleh for 2MHz inputs with and without calibration, respectively.

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Fig. 6 chip photograph. The measurement and estimation of the error coefficients are performed using the proposed technique. Figure 8(a) shows the INL plot without error correction for single-channel operation of the implemented ADC. The relationship between p and the gain error coefficients of the 1st stage is obtained from the measurement results as shown in Fig. 7. The horizontal axis is expressed by a unit of LSB in 12bits. Because the cost function has a parabolic relation, using three points of A/'. the 1st stage error coefficient value A,=6[LSB12] can be estimated. Similarly, A2 and A3 are also estimated using the same procedure. The error coefficients after the 4-fh stage are not necessary because the coefficient of A is to be less than lLSB at 12bit accuracy. Fig. 8(b) shows the INL plot with the error correction.
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Fig. 9 DNL and INL plot of the ADC for DC input.

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Fig. 12 SNDR and SNR versus the sampling frequency.

TABLE 1 MEASUREMENT SUMMARY Technology I 0.3pm 2-P 3-M CMOS I Supply Voltage [ 2v

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. . . . . . . .' . . . L * e t o o ~ & mhmami

Sampling rate Full scale DNL INL

12UMHz 1.6V (p-p) +O. 14b0.16 LSB +0.8/-0.6 LSB

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FrequencylHz] Fig. IO 4096 point FFT spectrum of 2MHz input without calibration.

4. Conclusion This paper describes the design and the implementation of a high-speed IObit time-interleaved pipeline ADC. The ADC has very low-power consumption and sufficient SNR using the digital calibration technique and the pseudo-differential pipeline architecture.
Acknowledgements This work is supported by Semiconductor Technology Academic Research Center (STARC). References

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[I] D.Miyazaki, S.Kawahito, "Low-Power Area-Efficient

Design of Embedded High-speed AiD Converters," IEICE Trans. Electronics, vol.EB3-Cpo.1 l,pp.17241732,2000, [2] D.Miyazaki, M.Furuta, S.Kawahito, "A 16mW 30MSamplesls lob Pipelined A/D Converter Using a Pseudo-Differential Architecture," Dig. of Tech. papers, Int. Solid-state Circuits Conf.,no.l0.5,pp.l74-175,Feb. 2002. [3] M.Furuta, SKawahito, D.Miyazaki, "A Digital Calibration Technique for Capacitor Mismatch for Pipelined Analog-to-Digital Converters,", IEICE Trans. on Electronics, Vol.ES5-C, No.8,pp. 15621568, Aug. 2002. [4] Lauri Sumanen, Mikko Waltari and Kari A.LHalonen, "A IO-bit 200-MSk CMOS Parallel Pipelined N D Converter", IEEE JSSC, pp1048-1055, Vo1.36, No.7, July.2001. [SI Yuh-Min Lin, Beomsup Kim, Paul R.Gray, "A 13-b 2.5-MHz Self-calibrated Pipelied A/D Converter in 3u-m CMOS", IEEE JSSC, pp628-636, Vo1.26, No.4, Mar. 1991. [6] Hae-Seung Lee, "A 12-b 600ks/s Digitally Self Calibrated Pipelined Algorithmic ADC", IEEE JSSC, pp509-515, Vo1.29, No.4, Apr.1994. [7] S. M. Jamal, D. Fu, P. J. Hunt, S. H. Lewis, "A lobit 12OMSample/s Time-Interleaved Analog-toDigital Converter with Digital Background Calibration," Dig. of Tech. papers, Int. Solid-state Circuits Conf.,no. 1 0 . 4 , ~ ~ . 174,Feb. 2002. 173-

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