Analog Integrated Circuits and Signal Processing, 25, 245251, 2000

Differential Analog Data Path DC Offset Calibration Methods

TAKEO YASUDA1 (MEMBER) AND HAJIME ANDOH2 (NONMEMBER)
1

IBM Japan, Shiga-ken, 5202392 Japan; Graduate School of Informatics, Kyoto University Kyoto-shi, 6068501 Japan
2

TI Japan, Yokohama-shi, 2400005 Japan

Received June 22, 1998

Abstract. DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-"m four-layer metal CMOS process. The measured data show this method works effectively in this system. Key Words: DC offset cancel, analog differential path, HDD channel, offset calibration

1.

Introduction

As the information industry grows, signal processing technology becomes more and more important. There are many types of media for storing huge amounts of data with a high data ratio. Hard disk drives (HDDs) still occupy the top position in capacity and in speed, with several key technologies such as the MR head and the PRML channel [13]. The read channel in the HDD extracts ``1'' or ``0'' data from a noisy readback analog waveform. Analog circuit components are located at the front end of the read channel. The offset in these circuits has undesirable effects on the circuit, such as phase locked loops or analog-todigital converter (ADC). These lead to a considerable degradation of the error rate of the HDD les. Highspeed analog circuits normally use a differential path to reject common-mode noise. However, the circuits have problems when the DC offset values in the two lines are too large to be ignored. Thus the offset should be removed actively. The DC offset calibration method is introduced and is compared with the prior art. This new method relaxes the tolerance for the DC offset for each analog component by changing the control target from the

ADC to the input buffer and separating the calibration process into three steps. In the rst two steps, the levels of the positive and negative lines are adjusted to the target level (the DC center of the ADC) independently, and then in the nal step the total DC offset is canceled. As the offset requirements for the front-end analog blocks are relaxed, this method does not require a post-production trimming circuit with fuses and their blowing process. Time-sharing use of the component and improvement of the algorithm remove the need for additional hardware and speed up the operation. The circuit reduces the simulation and execution times. It is implemented in a small silicon space in a high-speed (240 Mb/s) channel (HSC). 2. Problems in Prior Art

It is common to use a differential signal line for analog circuits in a read channel, to implement a robust system for common-mode noise. Even if such a line is adopted, however, DC offset cancellation in the analog path is required to convert differential signal into single-end correctly [4]. Fig. 1 shows the offset calibration circuit in the HDD channel of a

Copyright, 1999, IEICE, reprinted with permission from IEICE Transaction.

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Fig. 1. Offset calibration circuit of prior art.

prior art. For high-speed performance, the signal amplitude is small in variable gain amplier (VGA) and low-pass lter (LPF). In contrast the ADC requires a certain input range (amplitude and level) in order to output expected levels for the peak and center of a preamble study pattern in the disk. The ADCs input buffer amplies and shifts the smallamplitude signal from the LPF so that its output signal can lie within the ADCs target input range and drive-power can be improved. In this circuit, the offset is canceled as follows: at the beginning of the calibration, the VGAs inputs are shorted in order to force the AC input to zero. The offset calibration logic controls the current owing through the resistance ladder in the ash ADCs. The calibration logic changes its output by monitoring the ADCs sign bit (or most signicant bit (MSB)) output. Thus this method requires ADCs correct function from the beginning. This method, however, has some drawbacks. First, the initial offset should be within a few least signicant bits (LSBs) at the ADC's input. Fig. 2 shows the denition of the differential and common-

mode offsets in the differential system. The differential system is robust against the common-mode offset but too much offset still causes some undesirable effects on differential to single-end conversion. Fig. 3 shows the effect of the offset on the comparator's operation in the 3-bit differential ash ADC [5]. From these gures, the initial commonmode offset Vcom off must be less than 1.5 LSBs of the ADC because an offset of more than that may cause the differential ADC to malfunction. Similarly the differential offset Vdif off should be less than 2 LSBs. These restrictions make the tolerance of the initial total offset of the input signal, the VGA, the LPF, and the buffer rather strict (less than about 2.4 mV for Vcom off and less than 3.2 mV for Vdif off at the buffer's input, respectively assuming the buffer's gain is 10 and the ADC's LSB is 16 mV). Supplemental circuits such as that for fuse-trimming are required inside the VGA, the LPF and the buffers to reduce the internal circuit offsets caused by these blocks and the signal offset coming from the outside through the data input. This leads to overheads of time and cost, because it requires larger chip area, additional manufacturing processes, fuse testing, and its blowing. Second, the calibration time is rather long. The calibration bits in the ADC resistance ladder are very sensitive to its output. Whenever the calibration bits are changed, it takes a long time (more than 10 ms) for ADC to settle. Thus a long time counter is required for the logic, to make the waiting-timer strobe. That is why execution and simulation of this circuit take a long time.

Fig. 2. Offset denition in the differential system.

Fig. 3. Offset effect on the differential ADC.

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3.

Basic Idea and Circuit Implementation

Fig. 4 shows the new offset calibration circuit. Two identical buffers are used for the positive and negative signal lines. The calibration bits control the two buffers' DC levels through variable current sources independently. The calibration process has three steps. In the rst step (STEP1), after the VGA's inputs are shorted, the positive line's buffer is adjusted so that its output equals a certain DC value Vts1 . In the next step (STEP2), similarly, the negative line's buffer's output is adjusted to a DC value Vts2 . In fact Vts1 and Vts2 are equal to the center level of the 6-bit ash ADC's ladder. After these steps, the DC level difference of the ADC's two inputs is less than a few LSBs (ideally, it is zero). In the nal step (STEP3) the system offset is surely canceled by monitoring the ADC's MSB output. In this step, the calibration bits of either positive or negative lines of buffers are controlled. A single comparator shared by STEP1 and STEP2 is used, and is turned off after calibration to save power and circuit area. At the comparator's input, two switches select the target line and detach the comparator input capacitance from data lines after calibration. The merits of this idea are claried in detail with equations and real values. First, the offset tolerance at the buffers' input, which is the most important point of this idea, is discussed. Fig. 5 shows a positive-line buffer and its surrounding devices (the circuit for the negative line has exactly the same devices). The relations between

Fig. 5. Calibration buffer.

+ the buffer' inputs Vi+ and outputs Vo are described in the following equation [6]:   Rf Rs + Rf + + Vi Ical Rf Vref 1 Vo Rs Rs + where Ical are the total output currents of the positive and negative lines' calibration DACs, and Rf and Rs are resistance values. After STEP1 (or STEP2), Vo (or Vo ) is equal to the target voltage Vts1 (or Vts2 ). Vi (or Vi ) is then expressed by the following equation: 2 3 Rf Rs + + Vts1 or Vts2 Ical Rf Vref 2 Vi Rf Rs Rs

From (2) and the relation Vts1 Vts2 , the offsets at the buffers' input are calculated with the following equations: Vdif Vcom
off :Vi off :

Vi

Rf Rs I Ical Rf Rs cal

3 4

Rf Rs Ical Ical Vi Vi Vic 2 R f Rs 2

where Vic is the buffers' input level which gives the center level of the ADC ladder at their output. With the number of the DAC bits n 6, Rf 900 O, Rs 100 O, and jIcal j, jIcal j2n1 169 mA, the amount of maximum offsets which can be canceled are given as follows: max jVdif
Fig. 4. Offset calibration circuit.
off j^50 off j^25

mV mV

5 6

max jVcom

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From (5) and (6), this circuit is able to treat up to about 50-mV differential and 25-mV common-mode offsets at the buffers' input. Considering the input signal specication, the VGA, and the LPF performance, these value are large enough to cancel a typical total maximum Vdif off of 2030 mV and Vcom off of + 1015 mV. As for the resolution, DVo (the minimum + step of Vo ) is given by (1) as follows:
+ + DVo LSB of Ical Rf

+ + Substituting 9(mA) for the (LSB of Ical ), DVo equal 8.1 mV. This value is almost half of the ADC's LSB of about 16 mV, and is small enough for the minimum offset calibration step. In order to increase the signal-to-noise ratio (SNR) for the ADC, the buffer amplies the small signal output of the LPF. In the prior art, since the gain of the present buffer circuit is about 10, the initial differential and common-mode offset at the buffers' inputs must be less than 1/10 of 2 and 1.5 LSBs of the ADC, respectively. (This restriction comes from the initial offset tolerance at the ADC's input to ensure that the ADC functions correctly.) Therefore, the initial offsets at the buffer's input are less than 3.2( 16 6 2/10) mV and 2.4( 16 6 1.5/10) mV for the differential and commom-mode offset, respectively. These values are less than 1/10 of the values for the new method shown in (5) and (6). Thus this circuit relaxes the tolerance of the initial offset by more than 10 times. Second, the calibration time is analyzed. Fig. 6 shows its timing. The calibration bits are incremented or decremented at a waiting-time interval with a up counter and a down counter. According to the simulation, the buffers need less than 1 (ms) to settle after changing the calibration bits. Thus the waiting-time is slightly more than 1 (ms). STEP1 and STEP2 stop when each counters' outputs (calibration bits) reach the target. The average number of waitingcycles in each step are 2n1 (n is the calibration-bit width) for STEP1 and STEP2 and k ( 5 about 6) for STEP3. The total execution time is less than 2n k61 ms. In the conventional circuit, the calibration bits change at intervals of more than 10 ms, because it takes so much for the ADC to settle. Strobe is generated 2n 1 times on the average. Thus the total execution time is 2n 1610 ms. In the case of n 6, the calibration times for the new and prior art are about 70 and

Fig. 6. Calibration timing.

630 (ms), respectively. This means that the new method gives the execution time an improvement of almost 9 times. 4. Performance Evaluation

The performance is evaluated with the circuits implemented in the CMOS HDD channel HSC. Fig. 7 shows the DC levels of the two buffers' output vs. calibration bits. Both buffers' DC levels cover a range of more than 350 mV at their outputs. This ensures that the tolerance of the offset requirement is at least 35 mV at the buffer's input. Table 1

Fig. 7. Calibration buffer DC level. This data is collected by forcing the positive and negative calibration bits externally. The center of DC level is about 0.95 V. The DC level changes almost linearly except at the middle point. (This non-linearity is correct, because the calibration bit is expressed with the offset binary code, to preserve the symmetry of the code.)

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Table 1. Offset calibration results. Calibration Positive line DC level (mV) Negative line DC level (mV) Before After Before After Chip A 979 947 806 935 Chip B 741 1060 810 1070

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Fig. 9. System input and ADC output. Sine wave is given to the system input. From the second signal from the top to bottom one show the ADC's output. The bottom signal corresponds to the MSB while upper ones correspond to the other bits.

(a) Before offset calibration

shows the DC levels of the two lines before and after the offset calibration. Chip A has a 173-mV DC level difference before calibration, while Chip B has a 69mV difference. These difference are more than four LSBs (16 mV 6 4 64 mV). After the calibration, the differences are 12 and 10 mV for Chips A and B, respectively. These values correspond to the system's offset. Fig. 8 (a) and (b) show the signal levels for Chip A before and after calibration, respectively. After the calibration, the two lines' DC levels come close, and the ADC's MSB ips. These gures show the calibration process completed correctly. Fig. 9 shows the system input and ADC output after the offset calibration. The input sine waveform and the MSB output of the ADC, which is located at the

(b) After offset calibration Fig. 8. DC level before and after calibration. Before calibration, in (a), the top signal is the negative buffer's output and the middle one is the positive buffer's output. The bottom signal is the ADC's MSB output. After calibration, in (b), the positive and negative buffer's output come close together, and the ADC's MSB output ips.

Fig. 10. Calibration buffer layout.

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Table 2. Calibration circuit features. Area (mm2) Buffer (X2) Logic 580 6 360 500 6 450 # of Tr. (k) 0.1 2.4 Pow. Dissip. (mW) 5 60 (3.3 V) 5 10 (2.5 V)

bottom of the gure, show that the analog data path DC offset is canceled correctly. Slight timing delay between the center of the input sine-wave and the MSB's ipping point corresponds to the analog path delay. Even for the same chips, the offset may change with different register values. It may also change after powering on, reset, or long run. It is recommended that offset calibration be performed periodically. Table 2 shows the values of the size and the power dissipation of the additional circuit components to implement this method. The calibration logic occupies no more space than that of prior art and it consumes less than 10 mW at 40 MHz clock speed. The buffer's bandwidth is more than 160 MHz with maximum capacitance load of 1.5 pF. Their group delays spread less than 0.1 ns throughout the target signal range of from 1 to 150 MHz. The input and output ranges of these buffers are 0.2 and 2.0 V peak-to-peak, respectively. They are adjusted to the output range of the LPF and the input range of the ADC, respectively. The circuits are implemented in

0.25 mm Leff 0X12 mm four-layer metal CMOS process. Fig. 10 shows the buffers' layout with the shared comparator and the current DACs for calibration. The calibration DAC and the comparator together occupy about 15% of the total buffer area. The circuit is implemented in a high-speed channel on a 3.41 mm 6 3.67 mm die area and realizes excellent performance in data read operation. A microphotograph of the total chip is shown in Fig. 11. It shows the die areas occupied by the offset calibration circuits and the related analog blocks. 5. Conclusion

A differential analog data path offset calibration method has been introduced. Before calibrating the total system offset by monitoring the ADC's MSB output, the method adjusts the DC level of the ADC's input to within a few LSBs. This ensures the ADC's correct performance in the nal step in which the total offset is canceled by using the ADC's MSB output. It relaxes the offset tolerance for the analog circuit by almost 10 times, and eliminates a postmanufacturing ne-trimming circuit with such as the fuses. It also reduces the execution and simulation times down to almost 1/9 of those of the conventional method without any additional silicon space. This calibration has only to be invoked from outside just after powering on, reset or once in a long run. This method and circuit can be widely utilized in any other analog signal processing systems with a differential analog data path. Acknowledgments The authors would like to thank Rick Malm, Fang-shi Lai, Denny D. Tang, Martin Chen, Toshio Sunaga, or their useful advices through this study. The authors are also grateful to Tetsuo Hattori, Kohji Ishii, and Izumi Tsutamoto for their kind assistance for this study. References
1. R. A. Richetta, C. J. Goetschel, R. A. Greene, R. A. Kertis, R. A. Philpott, T. J. Schmerbeck, D. J. Schulte, and D. P. Swart, ``A 16 MB/s PRML read/write data channel.'' ISSCC Digest of Technical Papers, pp. 7879, February 1995.

Fig. 11. Microphotograph of the total chip.

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2. G. T. Tuttle, G. D. Vishakhadatta, M. Goldenberg, D. Kuai, I. Mehr, A. Singh, R. P. Trujillo, D. R. Welland, R. Gomez, F. Aram, J. P. Hein, D. Reed, J. Mitchem, W. G. Bliss, A. J. Armstrong, R. T. Behrens, T. O. Dudley, C. J. Duey, J. Meadows, W. R. Foland Jr., R. W. Hull, and D. P. Turner, ``130 Mb/s PRML read/write channel with digital-servo detection.'' ISSCC Digest of Technical Papers, pp. 6465, February 1996. 3. R. Alini, G. Betti, R. Castello, F. Heydari, G. Maguire, L. Fredrickson, L. Volz, and D. Stone, ``A 200 M Sample/s trelliscoded PRML read/write channel with digital servo.'' ISSCC Digest of Technical Papers, pp. 318319, February 1997. 4. T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, and K. Okada, ``A 10-b, 50 MS/s 500-mW A/D converter using a differential-voltage subconverter.'' IEEE J. Solid-State Circuits, 29(4), pp. 516522, April 1994. 5. M. Ito, T. Miki, S. Hosotani, T. Kumamoto, Y. Yamashita, M. Kijima, T. Okuda, and K. Okada, ``A 10 bit, 20 MS/s 3 V supply CMOS A/D converter.'' IEEE J. Solid-State Circuits, 29(12), pp. 15311536, December 1994. 6. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. 2nd edn., Wiley, New York, Chapters 39 and 12, 1984.

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engineering from Kyoto University, Kyoto, Japan, in 1988 and 1990, respectively. He has been doing research on magnetic recording systems with IBM Japan since 1990. Currently he is a student of the doctor course of Graduate School of Informatics, Kyoto University, too. His research interest includes analog and digital signal processing circuits for high performance magnetic recording system. He is now a member of IEEE Magnetic Society and Solid-State Circuits Society.

Takeo Yasuda was born in Osaka, Japan, in 1965. He received B.E. and M.E. degrees in electronic

Hajime Andoh was born in Taka-yama Gifu, Japan, in 1950. He received B.E. and M.E. degrees in electronic engineering from Nagoya Institute of Technology and University of Vermont in 1973 and 1986, respectively. He worked for OKI as analog circuit designer from 1973 to 1980 and for IBM Japan as analog circuit designer from 1980 to 1997. Currently, he is a manager of read channel development in TI Japan. His research interest is in analog circuits and architectures of signal processing in magnetic recording. He is a member of IEEE.