TDA7442 TDA7442D

TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR

4 STEREO INPUTS INPUT ATTENUATION CONTROL IN 0.5dB STEP TREBLE AND BASS CONTROL TWO SURROUND MODE AVAILABLE WITH 4 SELECTABLE RESPONSES: - MUSIC - SIMULATED STEREO TWO SPEAKER ATTENUATORS: - 2 INDEPENDENT SPEAKER CONTROLS IN 1dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS 2 MONITOR OUTPUT (ONLY FOR TDA7442) DESCRIPTION The TDA7442/42D is volume tone (bass and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. It reproduces surround sound by using a proPIN CONNECTIONS

SO28

SDIP32

ORDERING NUMBER: TDA7442D (SO28) TDA7442 (SDIP32)

grammable phase shifter. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the BIPOLAR/CMOS Technology used, Low Distortion, Low Noise and DC stepping are obtained.

R-IN2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D01AU1247

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

R-IN3 R-IN4 L-OUT R-OUT AGND VS CREF SDA SCL DIGGND TREBLE-R N.C. TREBLE-L PS1 LP BOUT(L)

R_IN3 R_IN2 R_IN1 L_IN1 L_IN2 L_IN3 L_IN4 MUXOUTL IN(L) MUXOUT(R) IN(R) BIN(R) BOUT(R) BIN(L)

1 2 3 4 5 6 7 8 9 10 11 12 13 14
D98AU948

28 27 26 25 24 23 22 21 20 19 18 17 16 15

R_IN4 LOUT ROUT AGND VS CREF SDA SCL DIG-GND TREBLE(R) TREBLE(L) PS1 LP BOUT(L)

R-IN1 MONITOR(L) MONITOR(R) L-IN1 L-IN2 L-IN3 L-IN4 MUXOUT(L) IN(L) MUXOUT(R) N.C. IN(R) BIN(R) BOUT(R) BIN(L)

SO28

SDIP32 1/16

January 2001

TDA7442 - TDA7442D

BLOCK DIAGRAM (TDA7442)

100nF 2.2F 5.6nF 5.6K 100nF 100nF

IN(L)

MONITOR(L) 0.47F L-IN1 50K 0.47F L-IN2 50K 0.47F L-IN3 0.47F L-IN4 50K 7 50K 8 6 5 3

MUXOUT(L) 31.5dB control 9

PS1 19 RPS1

TREBLE-L 20 16

BIN(L) BOUT(L) 17 RB

10

FIX

30K PS1 90Hz OFF 79dB CONTROL VAR SPKR ATT MUTE + FIX MIXING AMP TREBLE BASS 24 25 I2C BUS DECODER + LATCHES 23 TREBLE BASS FIX SURR VAR + 50K 30K OFF MUTE 79dB CONTROL 50K 31.5dB control 4 MONITOR(R) 11 MUXOUT(R) 13 18 27 VS 1.2nF 28 Vref RB 22 CREF TREBLE-R 14 BIN(R) 13 BOUT(R) SPKR ATT + + 50K 30K OFF MUTE 79dB CONTROL 50K 31.5dB control 10 MUXOUT(R) 11 16 24 VS 1.2nF 25 Vref RB 19 CREF TREBLE-R 12 BIN(R) 13 BOUT(R) -

+ + L+R

SYMULATED

MUSIC/ SYMULATED MUSIC

SURR

30

LOUT

+ 0.47F R-IN1 50K 0.47F R-IN2 50K 0.47F R-IN3 0.47F R-IN4 32 1

L-R

OFF

SCL SDA DIG GND

LPF 9KHz

EFFECT CONTROL

MIXING AMP

29

ROUT

31

SUPPLY

26

AGND

IN(R)

LP

D98AU947B

2.2F

22F 5.6nF 100nF 5.6K 100nF

BLOCK DIAGRAM (TDA7442D)

5.6nF 5.6K 100nF 100nF

100nF 2.2F

IN(L)

MUXOUT(L) 0.47F L-IN1 50K 0.47F L-IN2 50K 0.47F L-IN3 50K 0.47F L-IN4 50K 7 + + 6 5 4 31.5dB control 8

PS1 17 RPS1

TREBLE-L 18 14

BIN(L) 15 RB

BOUT(L)

FIX

30K PS1 90Hz OFF 79dB CONTROL VAR SPKR ATT MUTE

SYMULATED L+R MUSIC + L-R OFF

MUSIC/ SYMULATED MIXING AMP

SURR

27

LOUT

FIX TREBLE BASS

21 22 I2C BUS DECODER + LATCHES 20

SCL SDA DIG GND

0.47F R-IN1

3 50K

0.47F R-IN2

2 50K

LPF 9KHz

EFFECT CONTROL

MIXING AMP SURR

TREBLE

BASS FIX VAR SPKR ATT

0.47F R-IN3 0.47F R-IN4

26

ROUT

28

SUPPLY

23

AGND

IN(R)

LP

D01AU1248

2.2F

22F 5.6nF 100nF 5.6K 100nF

2/16

TDA7442 - TDA7442D
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio V out = 1Vrms (mode = OFF) Channel Separation f = 1KHz Treble Control (2db step) -14 -14 -79 100 Bass Control (2dB step) Balance Control 1dB step (LCH, RCH) Mute Attenuation Parameter Min. 7 2 0.01 106 90 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB

THERMAL DATA
Symbol Rth j-pins Thermal Resistance Junction-pins Description Max. Value 85 Unit C/W

ABSOLUTE MAXIMUM RATINGS

Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 11 -10 to 85 -55 to +150 Unit V C C

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TDA7442 - TDA7442D
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, RL = 10K, Vin = 1Vrms; RG = 600, all controls flat (G = 0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection LCH / RCH out, Mode = OFF 7 10 60 9 18 80 10.2 26 V mA dB

INPUT STAGE
RIN VCL CRANGE AVMIN AVMAX ASTEP Input Resistance Clipping Level Control Range Min. Attenuation Max. Attenuation Step Resolution -1 31 THD = 0.3% 35 2 50 2.5 31.5 0 31.5 0.5 1 32 1 65 K Vrms dB dB dB dB

BASS CONTROL
Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +11.5 1 32 +14.0 2 44 +16.0 3 56 dB dB K

TREBLE CONTROL
Gt TSTEP Control Range Step Resolution Max. Boost/cut +13.0 1 +14.0 2 +15.0 3 dB dB

EFFECT CONTROL
CRANGE SSTEP Control Range Step Resolution - 21 0.5 1 -6 1.5 dB dB

SURROUND SOUND MATRIX PHASE

RPS10 RPS11 RPS12 RPS13 Phase Shifter 1: D1 = 0, D0 = 0 Phase Shifter 1: D1 = 0, D0 = 1 Phase Shifter 1: D1 = 1, D0 = 0 Phase Shifter 1: D1 = 1, D0 = 1 8.3 10 12.6 26.4 11.8 14.1 17.9 37.3 15.2 18.3 23.3 48.85 K K K K

SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
Symbol GOFF Parameter In-phase Gain (OFF) Test Condition Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin Rout Lin Lout Mode OFF, Input signal of 1kHz, 1.4 Vp-p Rin Rout, Lin Lout Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout), (Lin Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin Rout) - (Lin Lout) Min. -1 Typ. 0 Max. 1 Unit dB

DGOFF

LR In-phase Gain Difference (OFF) In-phase Gain (Music)

-1

dB

GMUS

dB

DGMUS

LR In-phase Gain Difference (Music)

dB

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TDA7442 - TDA7442D
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit

SPEAKER ATTENUATORS
Crange SSTEP EA VDC AMUTE RVEA Control Range Step Resolution Attenuation set error DC Steps Output Mute Condition Input Impedance Av = 0 to -20dB Av = -20 to -79dB adjacent att. steps -0.5 -1.5 -3 -3 +70 21 79 1 0 0 0 100 30 39 1.5 1.5 2 3 dB dB dB dB mV dB K Vrms Vrms mVrms mVrms 0.1 % dB Vrms 50 V

AUDIO OUTPUTS
NO(OFF) NO(MUS) NO(PSEUDO) d SC VOCL ROUT VOUT Output Noise (OFF) Output Noise (Music) Output Noise (Pseudo Stereo) Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level d = 0.3% Output Mute, Flat BW = 20Hz to 20KHz Mode = Music , BW = 20Hz to 20KHz, Mode = Pseudo Stereo BW = 20Hz to 20KHz, Av = 0 ; Vin = 1Vrms 70 2 10 4 5 30 30 0.01 90 2.5 30 3.8

MONITOR OUTPUTS
d SC VOCL ROUT VOUT Distorsion Channel Separation Clipping Level Output Resistance DC Voltage Level Av = 0 ; Vin = 1Vrms d = 0.3% 70 2 20 0.01 90 2.5 50 4.5 70 0.1 % dB Vrms V

BUS INPUTS
VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 1 +5 0.4 V V A V

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TDA7442 - TDA7442D
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7442D and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS knowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking.

SDA

SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED

D99AU1031

Figure 4: Timing Diagram of I2CBUS

SCL I2CBUS SDA

D99AU1032

START

STOP

Figure 5: Acknowledge on the I2CBUS

SCL

SDA MSB START

D99AU1033

ACKNOWLEDGMENT FROM RECEIVER

6/16

TDA7442 - TDA7442D
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7442D address A subaddress bytes A sequence of data (N byte + achnowledge) A stop condition (P)

CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB B

SUBADDRESS LSB DATA ACK MSB

DATA 1 to DATA n LSB DATA ACK P

D95AU226A

ACK = Achnowledge S = Start P = Stop A = Address B = Auto Increment

EXAMPLES No Incremental Bus The TDA7442D receives a start condition, the

correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.

CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 0 X

SUBADDRESS LSB X X D3 D2 D1 D0 ACK MSB

DATA LSB DATA ACK P

D95AU306

Incremental Bus The TDA7442D receive s a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas

SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored. The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.

CHIP ADDRESS MSB S 1 0 0 0 0 0 A LSB 0 ACK MSB 1 X

SUBADDRESS LSB X X D3 D2 D1 D0 ACK MSB

DATA 1 to DATA n LSB DATA ACK P

D95AU307

7/16

TDA7442 - TDA7442D
DATA BYTES Address = 80(HEX) FUNCTION SELECTION: The first byte (subaddress)
MSB D7 B B B B B B B B B B D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 0 1 SUBADDRESS INPUT ATTENUATION SURROUND & OUT & EFFECT CONTROL PHASE RESISTOR BASS TREBLE SPEAKER ATTENUATION "L" SPEAKER ATTENUATION "R" NOT ALLOWED NOT ALLOWED INPUT MULTIPLEXER

B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 INPUT ATTENUATION SELECTION
MSB D7 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 INPUT ATTENUATION 0.5 dB STEPS 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 4 dB STEPS 0 -4 -8 -12 -16 -20 -24 -28

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

INPUT ATTENUATION = 0 -31.5dB

8/16

TDA7442 - TDA7442D
SURROUND SELECTION
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 LSB D0 0 1 0 SURROUND MODE SIMULATED STEREO MUSIC OFF OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 SURROUND PHASE RESISTOR PHASE SHIFT 1 (K) 12 14 18 37

0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

PHASE RESISTOR SELECTION

MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 LSB D0 0 1 0 1

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TDA7442 - TDA7442D
BASS SELECTION
MSB D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14

SPEAKER SELECTION
MSB D7 X X X X X X X X X X X X X X X X X X X X D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER/ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE

0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 1

0 0 1 1 0 0 1 1 0 0 1 X

0 1 0 1 0 1 0 1 0 1 X X

X = INDIFFERENT 0,1 SPEAKER ATTENUATION = 0dB -79dB

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TDA7442 - TDA7442D
TREBLE SELECTION
MSB D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D5 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 D4 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 D3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LSB D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TREBLE 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14

INPUT SELECTION
MSB D7 X X X X D6 D5 D4 D3 D2 0 0 1 1 D1 0 1 0 1 LSB D0 0 0 0 0 INPUT MULTIPLEXER IN2 IN3 IN4 IN1

POWER ON RESET
BASS TREBLE SURROUND & OUT CONTROL+ EFFECT CONTROL SPEAKER ATTENUATION L &R INPUT ATTENUATION INPUT 2dB 0dB OFF + FIX + MAX ATTENUATION MUTE MAX ATTENUATION IN1

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TDA7442 - TDA7442D
PIN: TREBLE-L, TREBLE-R
VS 20A

PIN: VOUT REF

VS 20A

25K

GND
GND
D95AU233A

10K
D95AU309

GND

PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4,

PIN: CREF

VS
VS

20K
20A

20A

42K

50K GND

20K
D94AU200

VREF

D95AU336

GND

PIN: SCL, SDA

PIN: LP

VS

20A

20A

GND

D94AU205

GND
D95AU308

12/16

TDA7442 - TDA7442D
PIN: L-OUT, R-OUT PIN: BASS-LI, BASS-RI

VS 20A

VS 20A

GND BASS-LO

45K : Bass

GND
D95AU230

BASS-RO

D98AU949

PIN: BASS-LO, BASS-RO

VS 20A

45K GND BASS-LI,BASS-RI

D98AU950

13/16

TDA7442 - TDA7442D
mm MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013

DIM.

OUTLINE AND MECHANICAL DATA

SO28

8 (max.)

14/16

TDA7442 - TDA7442D
mm DIM. MIN. A A1 A2 B B1 C D E E1 e eA eB L 2.540 3.048 3.556 0.508 3.048 0.356 0.762 0.203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 3.810 0.1 0.12 4.572 0.584 1.397 0.356 28.45 11.05 9.398 TYP. 3.759 MAX. 5.080 MIN. 0.14 0.020 0.12 0.014 0.03 0.008 1.08 0.39 0.3 0.14 0.018 0.04 0.01 1.1 0.409 0.35 0.070 0.400 0.500 0.15 0.18 0.023 0.055 0.014 1.12 0.433 0.37 TYP. 0.147 MAX. 0.2 inch

OUTLINE AND MECHANICAL DATA

SDIP32 (Shrink Plastic Dip 32L)

E E1

A2

A1 L

B1

eA eB

D C

32

17

16
SDIP32M

0123183

15/16

TDA7442 - TDA7442D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com

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