TDA8754

TDA8754
Triple 8-bit video ADC up to 270 Msample/s

Rev. 07 3 May 2007 Product data sheet
1. General description
The TDA8754 is a complete triple 8-bit Analog-to-Digital Converter (ADC) with an integrated Phase-Locked Loop (PLL) running up to 270 Msample/s and analog preprocessing functions (clamp and programmable gain amplier) optimized for capturing RGB/YUV graphic signals. The PLL generates a pixel clock from inputs HSYNC and COAST. The TDA8754 offers full sync processing for Sync-On-Green (SOG) applications. A clamp signal may be generated internally or provided externally. The clamp levels, gains and other settings are controlled via the I2C-bus interface. This IC supports display resolutions up to QXGA (2048 1536) at 85 Hz.
2. Features
I 3.3 V power supply I Temperature range from 10 C to +70 C I Triple 8-bit ADC: N 0.25 LSB Differential Non-Linearity (DNL) N 0.6 LSB Integral Non-Linearity (INL) I Analog sampling rate from 12 Msample/s up to 270 Msample/s I Maximum data rate: N Single port mode: 140 MHz N Dual port mode: 270 MHz N 3.3 V LV-TTL outputs I PLL control via I2C-bus: N 390 ps PLL jitter peak to peak at 270 MHz N Low PLL drift with temperature (2 phase steps maximum) N PLL generates the ADC sampling clock which can be locked on the line frequency from 15 kHz to 150 kHz N Integrated PLL divider N Programmable phase clock adjustment cells I Three clamp circuits for programming a clamp code from 24 to +136 by steps of 1 LSB (mid-scale clamping for YUV signal) I Internal generation of clamp signal I Three independent blanking functions I Input: N 700 MHz analog bandwidth
NXP Semiconductors
TDA8754
I I I
N Two independent analog inputs selectable via I2C-bus N Analog input from 0.5 V to 1 V (p-p) to produce a full-scale ADC input of 1 V (p-p) N Three controllable ampliers: gain control via I2C-bus to produce full-scale peak-to-peak output with a half LSB resolution Synchronization: N Frame and eld detection for interlaced video signal N Parasite synchronization pulse detection and suppression N Sync processing for composite sync, 3-level sync and sync-on-green signals N Polarity and activity detection IC control via I2C-bus serial interface Power-down mode LQFP144 and LBGA208 package: N LBGA208 package pin-to-pin compatible with TDA8756
3. Applications
I I I I LCD panels drive RGB/YUV high-speed digitizing LCD projection system New TV concept
4. Quick reference data

Table 1. Symbol VCCA VCCD VCCO fPLL ENOB INL DNL Ptot Quick reference data Parameter analog supply voltage digital supply voltage output supply voltage output clock frequency effective number of bits integral non-linearity differential non-linearity total power dissipation fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz Conditions Min 3.0 3.0 3.0 10 Typ 3.3 3.3 3.3 7.6 0.6 0.25 1.0 Max 3.6 3.6 3.6 270 1.3 0.6 1.3 Unit V V V MHz bit bit bit W
TDA8754_7
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5. Ordering information
Table 2. Ordering information Maximum sampling frequency 110 MHz 140 MHz 170 MHz 210 MHz 270 MHz 110 MHz 140 MHz 170 MHz 210 MHz 270 MHz LBGA208[1] plastic low prole ball grid array package; 208 balls; body 17 17 1.05 mm SOT774-1 Package Name LQFP144 Description plastic low prole quad at package; 144 leads; body 20 20 1.4 mm Version SOT486-1 Type number
TDA8754HL/11/C1 TDA8754HL/14/C1 TDA8754HL/17/C1 TDA8754HL/21/C1 TDA8754HL/27/C1 TDA8754EL/11/C1 TDA8754EL/14/C1 TDA8754EL/17/C1 TDA8754EL/21/C1 TDA8754EL/27/C1
[1]
Values are not yet guaranteed.
6. Block diagram
3 RGB1 input RGB2 input 3 CLAMP AGC 3 ADC DMX LV-TTL BUFFERS RGB output B ACTIVITY DETECTION HPDO LV-TTL BUFFERS RGB output A
TDA8754
SOGIN1 SOGIN2 HSYNC1 CHSYNC1 HSYNC2 CHSYNC2 COAST PLL VSYNC1 VSYNC2 I 2C-BUS SLAVE POWER MANAGEMENT SYNC SEPARATOR CLKDMX HCOUNTER
CKDATA
DEO
mgu895
VSYNCO
HSYNCO
CKEXT CKREFO SDA SCL
A0
FIELDO
Fig 1. Block diagram

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7. Pinning information
7.1 Pinning
144 109 108
TDA8754HL
36 37 72 4 3 5 6 7 8 9 10 11
73
001aac980
Fig 2. Pin conguration LQFP144 package
ball A1 index area 1 A B C D E F G H J K L M N P R T
12 13
14 15
16
TDA8754EL
001aac981
Transparent top view
Fig 3. Pin conguration LBGA208 package
7.2 Pin description

Table 3. Symbol GNDD(TTL) VCCD(TTL) HSYNC2 CHSYNC2 VCCA(PLL) HSYNC1 CHSYNC1
TDA8754_7
Pin description for LQFP144 package Pin 1 2 3 4 5 6 7 Description TTL input digital ground TTL input digital supply voltage horizontal synchronization pulse input 2 composite horizontal synchronization pulse input 2 PLL analog supply voltage horizontal synchronization pulse input 1 composite horizontal synchronization pulse input 1
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Pin description for LQFP144 package continued Pin 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description PLL analog ground PLL lter input CPO analog ground PLL lter input phase measurement output (test) SUB analog ground decoupling SOG input 1 decoupling SOG output decoupling SOG input 2 SOG analog ground sync-on-green input 1 SOG analog supply voltage sync-on-green input 2 red channel analog supply voltage red channel analog input 1 red channel 1 analog ground red channel analog input 2 red channel 2 analog ground main regulator decoupling input red channel ladder decoupling input red channel clamp capacitor input green channel analog supply voltage green channel analog input 1 green channel 1 analog ground green channel analog input 2 green channel 2 analog ground green channel ladder decoupling input green channel clamp capacitor input blue channel analog supply voltage blue channel analog input 1 blue channel 1 analog ground blue channel analog input 2 blue channel 2 analog ground blue channel ladder decoupling input blue channel clamp capacitor input Automatic Gain Control (AGC) output ADC digital ground ADC digital supply voltage SUB digital ground power-down control input test input; must be connected to ground
Table 3. Symbol
GNDA(PLL) CZ GNDA(CPO) CP PMO GNDA(SUB) CAPSOGIN1 CAPSOGO CAPSOGIN2 GNDA(SOG) SOGIN1 VCCA(SOG) SOGIN2 VCCA(R) RIN1 GNDA(R1) RIN2 GNDA(R2) DEC RBOT RCLPC VCCA(G) GIN1 GNDA(G1) GIN2 GNDA(G2) GBOT GCLPC VCCA(B) BIN1 GNDA(B1) BIN2 GNDA(B2) BBOT BCLPC AGCO GNDD(ADC) VCCD(ADC) GNDD(SUB) PWD TEST
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Pin description for LQFP144 package continued Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Description blue channel ADC output B bit 0 blue channel ADC output B bit 1 blue channel ADC output B bit 2 blue channel ADC output B bit 3 blue channel ADC output B bit 4 blue channel ADC output B bit 5 blue channel ADC output B bit 6 blue channel ADC output B bit 7 blue channel B output supply voltage blue channel B output ground blue channel ADC output bit out of range blue channel ADC output A bit 0 blue channel ADC output A bit 1 blue channel ADC output A bit 2 blue channel ADC output A bit 3 blue channel ADC output A bit 4 blue channel ADC output A bit 5 blue channel ADC output A bit 6 blue channel ADC output A bit 7 blue channel A output supply voltage blue channel A output ground green channel ADC output B bit 0 green channel ADC output B bit 1 green channel ADC output B bit 2 green channel ADC output B bit 3 green channel ADC output B bit 4 green channel ADC output B bit 5 green channel ADC output B bit 6 green channel ADC output B bit 7 green channel B output supply voltage green channel B output ground green channel ADC output bit out of range green channel ADC output A bit 0 green channel ADC output A bit 1 green channel ADC output A bit 2 green channel ADC output A bit 3 green channel ADC output A bit 4 green channel ADC output A bit 5 green channel ADC output A bit 6 green channel ADC output A bit 7 green channel A output supply voltage
Table 3. Symbol BB0 BB1 BB2 BB3 BB4 BB5 BB6 BB7 VCCO(BB) GNDO(BB) BOR BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 VCCO(BA) GNDO(BA) GB0 GB1 GB2 GB3 GB4 GB5 GB6 GB7 VCCO(GB) GNDO(GB) GOR GA0 GA1 GA2 GA3 GA4 GA5 GA6 GA7 VCCO(GA)
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Pin description for LQFP144 package continued Pin 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Description green channel A output ground red channel ADC output B bit 0 red channel ADC output B bit 1 red channel ADC output B bit 2 red channel ADC output B bit 3 red channel ADC output B bit 4 red channel ADC output B bit 5 red channel ADC output B bit 6 red channel ADC output B bit 7 red channel B output supply voltage red channel B output ground red channel ADC output bit out of range red channel ADC output A bit 0 red channel ADC output A bit 1 red channel ADC output A bit 2 red channel ADC output A bit 3 red channel ADC output A bit 4 red channel ADC output A bit 5 red channel ADC output A bit 6 red channel ADC output A bit 7 red channel A output supply voltage red channel A output ground clock output digital supply voltage data clock output clock output digital ground I2C-bus lines digital ground I2C-bus lines digital supply voltage I2C-bus address control input I2C-bus serial data input and output I2C-bus serial clock input I2C-bus disable control input scan test output scan test mode input; must be connected to ground clamp pulse input DVI standby output MCF digital ground MCF digital supply voltage horizontal synchronization pulse output data enable output hot plug detector output TTL output digital ground
Table 3. Symbol GNDO(GA) RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 VCCO(RB) GNDO(RB) ROR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 VCCO(RA) GNDO(RA) VCCO(CLK) CKDATA
GNDO(CLK) GNDD(I2C) VCCD(I2C) A0 SDA SCL DIS TDO TCK CLP STBDVI GNDD(MCF) VCCD(MCF) HSYNCO DEO HPDO GNDO(TTL)
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Pin description for LQFP144 package continued Pin 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Description TTL output digital supply voltage vertical synchronization pulse output eld information output clamp output reference output clock; re-synchronized horizontal negative pulse composite synchronization output test pin; should be connected to ground test pin; should be connected to ground SLC digital ground SLC output digital supply voltage external clock input PLL coast control input vertical synchronization pulse input 2 vertical synchronization pulse input 1
Table 3. Symbol VCCO(TTL) VSYNCO FIELDO CLPO CKREFO CSYNCO ACRX2 ACRX1
GNDD(SLC) VCCD(SLC) CKEXT COAST VSYNC2 VSYNC1 Table 4. Symbol SOGIN1 GNDA(PLL) SOGIN2 GNDA(PLL) HSYNC2 CHSYNC2 COAST CSYNCO FIELDO HSYNCO SCL n.c. n.c. DIS A0 CKDATA GNDA(PLL) PMO GNDA(PLL) GNDA(PLL) VCCA(PLL) CLP CKEXT CKREFO
TDA8754_7
Pin description for LBGA208 package Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 Description sync-on-green input 1 PLL analog ground sync-on-green input 2 PLL analog ground horizontal synchronization pulse input 2 composite horizontal synchronization pulse input 2 PLL coast control input composite synchronization output eld information output horizontal synchronization pulse output I2C-bus serial clock input not connected not connected I2C-bus disable control input I2C-bus address control input data clock output PLL analog ground phase measurement output (test) PLL analog ground PLL analog ground PLL analog supply voltage clamp pulse input external clock input reference output clock; re-synchronized horizontal negative pulse
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Pin description for LBGA208 package continued Ball B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 Description vertical synchronization pulse output data enable output I2C-bus serial data input and output not connected not connected not connected clock output digital ground clock output digital supply voltage red channel analog input 1 analog ground decoupling SOG input 1 decoupling SOG input 2 decoupling SOG output horizontal synchronization pulse input 1 vertical synchronization pulse input 1 clamp output not connected not connected scan test mode input scan test output I2C-bus lines digital supply voltage not connected not connected not connected analog ground analog ground PLL lter input PLL lter input CPO analog ground composite horizontal synchronization pulse input 1 vertical synchronization pulse input 2 hot plug detector output not connected not connected TTL output digital supply voltage TTL output digital ground I2C-bus lines digital ground not connected not connected not connected red channel analog input 2
Table 4. Symbol VSYNCO DEO SDA n.c. n.c. n.c.
GNDO(CLK) VCCO(CLK) RIN1 GNDA CAPSOGIN1 CAPSOGIN2 CAPSOGO HSYNC1 VSYNC1 CLPO n.c. n.c. TCK TDO VCCD(I2C) n.c. n.c. n.c. GNDA GNDA CZ CP GNDA(CPO) CHSYNC1 VSYNC2 HPDO n.c. n.c. VCCO(TTL) GNDO(TTL) GNDD(I2C) n.c. n.c. n.c. RIN2
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Pin description for LBGA208 package continued Ball E2 E3 E4 E7 E8 E9 E10 E13 E14 E15 E16 F1 F2 F3 F4 F13 F14 F15 F16 G1 G2 G3 G4 G5 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H12 H13 H14 H15 H16 J1 J2 Description analog ground analog ground analog ground TTL input digital ground TTL input digital supply voltage SLC digital ground SLC output digital supply voltage not connected not connected not connected not connected analog ground analog ground red channel ladder decoupling input analog ground not connected not connected not connected not connected green channel analog input 1 analog ground main regulator decoupling input analog supply voltage analog supply voltage not connected not connected not connected not connected not connected analog ground analog ground analog ground red channel clamp capacitor input analog supply voltage not connected not connected not connected not connected not connected green channel analog input 2 analog ground
Table 4. Symbol GNDA GNDA GNDA
GNDD(TTL) VCCD(TTL) GNDD(SLC) VCCD(SLC) n.c. n.c. n.c. n.c. GNDA GNDA RBOT GNDA n.c. n.c. n.c. n.c. GIN1 GNDA DEC VCCA VCCA n.c. n.c. n.c. n.c. n.c. GNDA GNDA GNDA RCLPC VCCA n.c. n.c. n.c. n.c. n.c. GIN2 GNDA
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Pin description for LBGA208 package continued Ball J3 J4 J5 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K12 K13 K14 K15 K16 L1 L2 L3 L4 L13 L14 L15 L16 M1 M2 M3 M4 M7 M8 M9 M10 M13 M14 M15 M16 N1 N2 N3 Description green channel ladder decoupling input analog ground green channel clamp capacitor input not connected not connected not connected not connected not connected analog ground analog ground analog ground blue channel clamp capacitor input analog supply voltage not connected not connected not connected not connected not connected blue channel analog input 1 analog ground blue channel ladder decoupling input analog supply voltage not connected not connected not connected not connected analog ground analog ground AGC output test input data output digital supply voltage data output digital supply voltage data output digital ground data output digital ground not connected not connected not connected not connected blue channel analog input 2 analog ground ADC digital ground
Table 4. Symbol GBOT GNDA GCLPC n.c. n.c. n.c. n.c. n.c. GNDA GNDA GNDA BCLPC VCCA n.c. n.c. n.c. n.c. n.c. BIN1 GNDA BBOT VCCA n.c. n.c. n.c. n.c. GNDA GNDA AGCO TEST VCCO VCCO GNDO GNDO n.c. n.c. n.c. n.c. BIN2 GNDA
GNDD(ADC)
TDA8754_7
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Pin description for LBGA208 package continued Ball N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Description ADC digital ground blue channel ADC output A bit 2 data output digital supply voltage green channel ADC output B bit 4 green channel ADC output B bit 0 green channel ADC output A bit 4 green channel ADC output A bit 0 data output digital ground power-down control input not connected not connected not connected not connected ADC digital supply voltage ADC digital supply voltage blue channel ADC output B bit 1 blue channel ADC output A bit 6 blue channel ADC output A bit 3 blue channel ADC output bit out of range green channel ADC output B bit 5 green channel ADC output B bit 1 green channel ADC output A bit 5 green channel ADC output A bit 1 red channel ADC output B bit 6 red channel ADC output B bit 3 red channel ADC output B bit 0 red channel ADC output A bit 5 red channel ADC output A bit 2 red channel ADC output bit out of range blue channel ADC output B bit 6 blue channel ADC output B bit 4 blue channel ADC output B bit 2 blue channel ADC output A bit 7 blue channel ADC output A bit 4 blue channel ADC output A bit 0 green channel ADC output B bit 6 green channel ADC output B bit 2 green channel ADC output A bit 6 green channel ADC output A bit 2 red channel ADC output B bit 7 red channel ADC output B bit 4
Table 4. Symbol
GNDD(ADC) BA2 VCCO GB4 GB0 GA4 GA0 GNDO PWD n.c. n.c. n.c. n.c. VCCD(ADC) VCCD(ADC) BB1 BA6 BA3 BOR GB5 GB1 GA5 GA1 RB6 RB3 RB0 RA5 RA2 ROR BB6 BB4 BB2 BA7 BA4 BA0 GB6 GB2 GA6 GA2 RB7 RB4
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Pin description for LBGA208 package continued Ball R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Description red channel ADC output B bit 1 red channel ADC output A bit 6 red channel ADC output A bit 3 red channel ADC output A bit 0 blue channel ADC output B bit 7 blue channel ADC output B bit 5 blue channel ADC output B bit 3 blue channel ADC output B bit 0 blue channel ADC output A bit 5 blue channel ADC output A bit 1 green channel ADC output B bit 7 green channel ADC output B bit 3 green channel ADC output A bit 7 green channel ADC output A bit 3 green channel ADC output bit out of range red channel ADC output B bit 5 red channel ADC output B bit 2 red channel ADC output A bit 7 red channel ADC output A bit 4 red channel ADC output A bit 1
Table 4. Symbol RB1 RA6 RA3 RA0 BB7 BB5 BB3 BB0 BA5 BA1 GB7 GB3 GA7 GA3 GOR RB5 RB2 RA7 RA4 RA1
8. Functional description
8.1 Functional description
This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals coming from an analog source into digital data used by a LCD driver (pixel clock up to 270 MHz with analog source) or projections systems.
8.1.1 Power management

It is possible to put the TDA8754 in Standby mode by setting bit STBY = 1 or to put the whole device in Power-down mode by setting pin PWD to HIGH level. 8.1.1.1 Standby mode In Standby mode, the status of the blocks is as follows:
Activity detection, I2C-bus slave, sync separator and SOG are still active Pixel counter, ADCs, demultiplexers, AGC and clamp cells are inactive Output buffers to the RGB block (RGB 0 to 7, CKDATA, DEO, HSYNCO and
VSYNCO) are in high-impedance state
Output HPDO is still active Output buffers (ROR, BOR, GOR, CKREFO, CSYNCO, CLPO and FIELDO) are in a
LOW-level state.
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8.1.1.2
Power-down mode In Power-down mode the status of the blocks is as follows:
All digital inputs and outputs are in high-impedance state All blocks are inactive (I2C-bus, activity detection, ADCs, etc.) Analog output is left uncontrolled I2C-bus is left in high-impedance state.
8.2 Analog video input

The RGB/YUV video inputs are externally AC coupled and are internally DC polarized. The synchronization signals are also used by the device as input for the internal PLL and the automatic clamp.
8.2.1 Analog multiplexers

The TDA8754 has two analog inputs (RGB input 1 and RGB input 2) selectable via the I2C-bus. The sync management can be achieved in several ways:
Choice between two analog inputs HSYNC and two analog inputs VSYNC Choice between two analog inputs CHSYNC Choice between two analog inputs SOG.
8.2.2 Activity detection
When a signal is connected or disconnected on pins HSYNC1(2), CHSYNC1(2), VSYNC1(2) and SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is set to HIGH to advise the user of a change. Bit HPDO is set to logic 0 and pin HPDO is set to LOW when register ACTIVITY2 has been read. When the synchronization pulse on pin SOG is 3-level, the system will automatically be able to detect that a 3-level sync is present and will force bit 3LEVEL to logic 1. It is possible to disable this function with bit FTRILEVEL. When an interlaced signal is detected, bit ACFIELD is set to logic 1. When the signal detected is progressive, this bit is set to logic 0. Any change in this bit results into setting bit HPDO = 1 and pin HPDO = HIGH. A eld detection unit is available on pin FIELDO which output is given by the sync separator. The eld identity is given by pin FIELDO. This pin gives the eld of interlaced signal input. An automatic polarity detection is also available on pins HSYNC1(2), VSYNC1(2) and CHSYNC1(2). The output on pin HPDO is not affected by the change of polarity of these inputs.
8.2.3 ADC
The three ADCs are designed to convert R, G and B (or Y, U and V) signals at a maximum frequency of 270 Msample/s. The ADC input range is 1 V (p-p) full-scale and the pipeline delay is 2 ADC clock cycles from the input sampling to the data output.
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The reference ladders regulators are integrated.
8.2.4 Clamp
Three independent parallel clamping circuits are used to clamp the video input signals on programmable black levels. The clamp levels may be set from 24 to +136 LSBs in steps of 1 LSB. They are controlled by three 9-bit I2C-bus registers (OFFSETR, OFFSETG and OFFSETB). The clamp pulse can be generated internally (based on the PLL clock reference) or can be externally applied on pin CLP. Remark: To prevent clamp noise when using internal clamp generated by the pixel counter (bit CLPSEL2 = 0), it is advised to delay the clamp pulse by 16 pixels using the HSYNCL register. By setting correctly the I2C-bus bits, it is possible to inhibit the clamp request with the Vsync signal. This inhibition will be effected by forcing logic 0 on the clamp request output. It should be noted that the clamp period can start on the falling edge of the clamp request and that the high level of the clamp request sets the ADC outputs in the blanking mode. This means that by forcing the clamp signal request to logic 0 by using Vsync, a falling edge may happen on the clamp request if this signal was at logic 1 before enforcing the inhibition. To avoid this, the user has to guarantee that the Vsync signal used for the clamp inhibition will not be set during a high level of the clamp request signal. Remark: If signal Vsync is coming from the external pin VSYNC, this signal may be used to coast the PLL. In order to properly do the coast, the edge of signal Vsync (COAST) must not appear at the same time as the edge of signal Hsync. This condition is similar to the pin CLP inhibition condition.
8.2.5 AGC
Three independent variable gain ampliers are used to provide, for each channel, a full-scale input signal to the 8-bit ADC. The gain adjustment range is designed in such a way that for an input range varying from 0.5 to 1 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p).
8.3 HSOSEL, DEO and SCHCKREFO

Bit HSOSEL allows to have a full correlation phase behavior between outputs CKDATA and HSYNCO when bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and bits PA4 to PA0 of register PHASE are changed to chose the best sampling time, the phase relationship between outputs CKDATA and HSYNCO will stay unchanged. After the video standard is determined, bit HSOSEL must be set to a logic 0 for normal operation mode. To use the Hsync from the counter the registers HSYNCL, HBACKL, HDISPLMSB and HDISPLLSB should be set properly in order to create the correct HSYNCO and DEO output signals (see Figure 5 and Figure 6), which is depending on video standard. Output signal DEO should be used to determine the rst active pixel. The demultiplexed mode should be used (bit DMXRGB = 1) and the output ow is alternated between port A and port B in case the sampling frequency is over 140 Msample/s (clock frequency). It is necessary, in order to warrant that the outputs HSYNCO and DEO are always changing on CKDATA output rising edge (see Figure 7),
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that the values HSYNCL, HBACKL and HDISPL (see Figure 5) are even value. If an odd value is entered the outputs HSYNCO and DEO can change state during falling edge, which is not compliant with the th(o) and td(o) specied output timing. Bit SCHCKREFO is used if in demultiplexed mode one pixel shift is needed in the DEO signal (to move the screen one vertical line). By setting bit SCHCKREFO from a logic 0 to a logic 1 a left move is obtained, also the timing relationship between HSYNCO, DEO and CKDATA stays unchanged. An even number of pixel moves is done by changing the value of HBACKL and HSYNCL. The correct combination of bits HBACKL, HSYNCL and SCHCKREFO places the rst active pixel at the beginning of the screen with always the correct phase relationship between outputs DEO, HSYNCO and CKDATA. Bit HSOSEL should be set to a logic 0 only after the PLL is stable, so only after the video standard has been found and correct PLL parameters have been set in the TDA8754. Bit HSOSEL should be set to a logic 1 to have a stable HSYNCO signal during the video recognition. The video standard can be recognized by using the signals FIELDO, VSYNCO and HSYNCO. The phase relation between CKDATA and HSYNCO (or DEO) is undened if bit HSOSEL = 1.
8.4 PLL
The ADCs are clocked by either the internal PLL locked to the reference clock (Hsync from input or Hsync from sync separator) or to an external clock connected to pin CKEXT. This selection is performed via the I2C-bus by setting bit CKEXT. To use the external clock, bit CKEXT must be reset to logic 1. The PLL phase frequency detector can be disconnected during the frame yback (vertical blanking) or the unavailability of the Ckref signal by using the coast function. The coast signal can be derived from the VSYNC1(2) input, from the Vsync extracted by the sync separator or from the coast input. The coast function can be disabled with bit COE. The coast signal may be active either HIGH or LOW by setting bit COS. It is possible to control the phase of the ADC clock via the I2C-bus with the included digital phase-shift controller. The phase register (5 bits) enables to shift the phase by steps of 11.25 deg. The PLL also provides a CKDATA clock. This clock is synchronized with the data outputs whatever the output mode is. It is possible to delay the CKDATA clock with a constant delay (t = 2 ns compared to the outputs) by setting bit DLYCLKRGB = 1. Moreover, it is possible to invert this output by setting bit CKDATINV = 1. When the PLL reference signal comes from the separator, the PLL rising edge must be preferably used in order to not use the PLL coast mode. It should be noted that the HSYNCO output of the sync separator is always a mostly LOW signal, whatever is the polarity of the composite sync input. The VSYNCO output signal of the sync separator is also mostly LOW signal. It is at a high state during the vertical blanking.
8.5 Sync-on-green
When the SOG input is selected (bit SOGSEL = 1), the SOG charge pump current bits SOGI[1:0] should be programmed in function of the input signal; see Table 5.
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A hum remover is implemented in the SOG. It removes completely the hum perturbation on the rst or second edge of the horizontal sync pulse for digital video input like VESA, and on the second edge only for analog video input signal like TV or HDTV. The maximum hum perturbation is 250 mV (p-p) at 60 Hz to have a correct SOG functionality.
Table 5. Charge pump current programming[1] Maximum value Tvideo / Tline 00 01 10 11
[1]
BITS SOGI[1:0]
Standard Tsync / Tline 14.8 % 12.6 % 8.6 % TV standards and non-VESA standards all TV, HDTV and VESA standards HDTV standards or non-VESA standards
83.5 % 86.0 % 90.5 % test mode
Denitions: Tvideo Total time in 2 frames when video signal is strictly superior to black level. Tline Total time of 2 frames. Tsync Total time in 2 frames when the video signal is strictly inferior to black level.
8.6 Programmable coast

When the values of PRECOAST[2:0] = 0 and POSTCOAST[4:0] = 0, the coast pulse equals the Vsync input. When an interlaced signal is used, the regenerated coast pulse width may vary from one frame to another of one Hsync pulse. In that case, the programmed value of PRECOAST[2:0] needs to be increased by one compared to the expected minimum number of Hsync coast pulses before the vertical sync signal.
8.7 Data enable

This signal qualies the active data period on the horizontal line. Pin DEO = HIGH during the active display time and LOW during the blank time. The start of this signal can be adjusted with bits HSYNCL[9:0] and HBACKL[9:0]. The length of this signal can be adjusted with bits HDISPL[11:0].
8.8 Sync separator

The sync separator is compatible with TV, HDTV and VESA standards. If the green video signal has composite sync on it (sync-on-green), the SOG function allows to separate the Chsync and the active video part. The Chsync signal coming from this SOG function is accessible through pin CSYNCO. It is possible to extract the Hsync and the Vsync signals by using the sync separator from this (C)Hsync signal coming from SOG or coming from the (C)Hsync input. This function is able to get rid of the additional synchronization pulses in vertical blanking like equalization or serration pulses.
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8.9 3-level
When the synchronization pulse of the input of the SOG is 3-level, the system will be able to detect that a 3-level sync is present and will advise the customer if a change is observed by setting bit HPDO = 1 and pin HPDO = HIGH. It is possible to disable this function with bit FTRILEVEL. When this automatic function is disabled, the manual mode will only inuence the separator circuitry.
9. I2C-bus register description

9.1 I2C-bus formats
9.1.1 Write 1 register
Each register is programmed independently by giving its subaddress and its data content.
Table 6. S Byte 1 A Byte 2 A Byte 3 A P Table 7. Bits Byte 1 A6 1 Byte 2 X Byte 3 D7 D6 D5 D4 A5 0 programming mode X MODE 0 SA4 data 1 D3 D2 D1 D0 A4 0 I2C-bus sequence for writing 1 register master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and register subaddress to write to slave generates an acknowledge master transmits data 1 slave generates an acknowledge master generates a stop condition Byte format for writing 1 register 7 6 5 4 device address A3 1 A2 1 SA3 A1 0 register subaddress SA2 SA1 SA0 A0 X 3 2 1 0 R/W 0
SDA line Description
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Write format bit description Symbol A[6:0] R/W MODE SA[4:0] Description Device address; the TDA8754 address is 1001 10X; bit A0 relates with the voltage level on pin A0 Write command bit; if R/W = 0, then write action not used Mode selection bit; if MODE = 0, then each register can be written independently Register subaddress; subaddress of the selected register (from 0 0000 to 1 1111) Data 1; this value is written in the selected register
Table 8. Bit Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte 3 7 to 0
D[7:0]
9.1.2 Write all registers

All registers are programmed one after the other, by giving this initial condition (XX11 1111) as the subaddress state; thus, the registers are charged following the predened sequence of 32 bytes (from subaddress 0 0000 to 1 1111).
Table 9. S Byte 1 A Byte 2 A Byte 3 A : Byte 34 A P Table 10. Bits Byte 1 A6 1 Byte 2 X Byte (2 + n) D7 D6 D5 D4 A5 0 programming mode X MODE 0 SA4 1 data n D3 D2 D1 D0 1 A4 0 I2C-bus sequence for writing all registers master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and register subaddress to write to slave generates an acknowledge master transmits data 1 slave generates an acknowledge : master transmits data 32 slave generates an acknowledge master generates a stop condition Byte format for writing all registers 7 6 5 4 device address A3 1 A2 1 SA3 A1 0 SA2 1 A0 X SA1 1 3 2 1 0 R/W 0 SA0 1
register subaddress
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Write format bit description Symbol A[6:0] R/W MODE SA[4:0] D[7:0] Description Device address; the TDA8754 address is 1001 10X; bit A0 relates with the voltage level on pin A0 Write command bit; if R/W = 0, then write action not used Mode selection bit; if MODE = 1, then all registers can be written one after the other Register subaddress; initial condition is XX11 to 1111 Data n; this value is written in register 00h + n
Table 11. Bit Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 7 to 0
Byte (2 + n)
9.1.2.1
Read register
Table 12. S Byte 1 A Byte 2 A Byte 3 A Byte 4 A Byte 5 A P Table 13. Bits Byte 1 A6 1 Byte 2 X Byte 3 0 0 0 A5 0 programming mode X MODE 0 SA4 1 0 1 0 A4 0 I2C-bus sequence for reading one register master starts with a start condition master transmits device address (7 bits) plus write command bit (R/W = 0) slave generates an acknowledge master transmits programming mode and register subaddress to read from slave generates an acknowledge master transmits read register subaddress slave generates an acknowledge master transmits device address (7 bits) plus read command bit (R/W = 1) slave generates an acknowledge slave transmits data to master master generates an not-acknowledge after reading the data byte master generates a stop condition Byte format for reading register 7 6 5 4 device address A3 1 A2 1 SA3 A1 0 register subaddress SA2 1 0 SA1 1 RA1 SA0 1 RA0 A0 X 3 2 1 0 R/W 0
read subaddress
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Byte format for reading register continued 7 A6 1 6 A5 0 D6 5 A4 0 D5 4 device address A3 1 data 1 D7 D4 D3 D2 D1 D0 A2 1 A1 0 A0 X 3 2 1 0 R/W 1
Table 13. Bits Byte 4
Byte 5
Table 14. Bit Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte 3 7 to 0 Byte 4 7 to 1 0 Byte 5 7 to 0
Read format bit description Symbol A[6:0] R/W MODE SA[4:0] RA[1:0] A[6:0] R/W D[7:0] Description Device address; the TDA8754 address is 1001 10X; bit A0 relates to the voltage level on pin A0 Write command bit; if R/W = 0, then write action not used Mode selection bit; if MODE = 0, then each register can be written independently Register subaddress; subaddress of the read register (1 1111) Read address; this is the value of the read register to be selected Device address; the TDA8754 address is 1001 10X. Bit A0 relates with the voltage level on pin A0 Read command bit; if R/W = 1, then read action Data 1; the value from read register is sent from the slave to the master
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9.2 I2C-bus registers overview

Bit MSB 7 6 OR6 CR6 OG6 CG6 OB6 CB6 UP IP0 PA3 SCH CKREFO DI6 HSYNCL8 HSYNCL0 HBACKL2 HDISPL6 OR5 CR5 OG5 CG5 OB5 CB5 5
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Table 15.
I2C-bus analog write registers Reset value LSB 4 OR4 CR4 OG4 CG4 OB4 CB4 STRILEVEL Z1 PA1 EPSI0 DI4 HSYNCL6 HBACKL8 HBACKL0 HDISPL4 OR3 CR3 OG3 CG3 OB3 CB3 CKREFS Z0 PA0 DI11 DI3 HSYNCL5 HBACKL7 HDISPL11 HDISPL3 POST COAST3 TESTCNT COE CLPH BLKEN AOENRGB HPDOEN 3 OR2 CR2 FR2 OG2 CG2 FG2 OB2 CB2 FB2 SOGSEL DR2 VCO2 DI10 DI2 HSYNCL4 HBACKL6 HDISPL10 HDISPL2 POST COAST2 BYSEPA VSS CLPENL DMXRGB OROEN VSOENRGB 2 OR1 CR1 FR1 OG1 CG1 FG1 OB1 CB1 FB1 SOGI1 DR1 VCO1 DI9 DI1 HSYNCL3 HBACKL5 HDISPL9 HDISPL1 POST COAST1 HSSEL COSSEL2 ICLP ODDARGB TOUTERGB CLPOEN 1 OR0 CR0 FR0 OG0 CG0 FG0 OB0 CB0 FB0 SOGI0 DR0 VCO0 DI8 DI0 HSYNCL2 HBACKL4 HDISPL8 HDISPL0 POST COAST0 HSS COSSEL1 CLPT SHIFTRGB TOUTSRGB FIELDOEN 0 0000 0000 0100 0110 XXXX X000 0000 0000 0100 0110 XXXX X000 0000 0000 0100 0110 XXXX X000 0000 0001 0101 1100 0000 0101 0000 0110 1001 1000 0010 0100 0000 1111 1000 0101 0000 0000 0000 0000 XXXX 0100 XXX0 0000 X010 0000 X000 0000 0000 0000 XXX1 1100 1111 1111
Addr Name
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h
OFFSETR COARSER FINER OFFSETG COARSEG FINEG OFFSETB COARSEB FINEB SOG PLLCTRL PHASE DIVMSB DIVLSB HSYNCL HBACKL HDISPLMSB HDISPLLSB COAST HSYNCSEL VSYNCSEL CLAMP INVERTER OUTPUT OUTPUTEN1 OUTPUTEN2
OR7 OR8 OG7 OG8 OB7 OB8 DO IP1 PA4 CKEXT DI7 HSYNCL9 HSYNCL1 HBACKL3 HDISPL7
FTRILEVEL Z2 PA2 EPSI1 DI5 HSYNCL7 HBACKL9 HBACKL1 HDISPL5
PRECOAST2 PRECOAST1 PRECOAST0 POST COAST4 RGBSEL CKROEN HSOSEL COS TEN CSOEN CLPSEL2 CLPS AGCSEL1 DEOENRGB TSTCOAST CLPSEL1 CKREFOINV AGCSEL0 BOENRGB HSOENRGB
TDA8754
DEOINVRGB HSOINVRGB VSOINVRGB FIELDOINV
Table 15. I2C-bus analog write registers continued Bit MSB 7 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh CLKOUTPUT INTOSC reserved reserved PWRMGT READADDR SHCKDMX SHCKADC STBY ADDR1 DVIRGB ADDR0 XXXX 0000 XXXX XX00 6 5 4 CKSELRGB 3 2 1 OUTOSCILL DLYCLKRGB CKDATINV LSB 0 CKOENRGB XXX0 0001 XXXX XX00 Reset value
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Addr Name
SWITCHOSC INTOSCOFF
Table 16. Addr
I2C-bus analog read registers[1] Name Bit MSB 7 6 ACVS1 ASD POLVS2 ACSOG2 3LEVEL 5 POLVS1 ACSOG1 ACFIELD 4 VER3 POLCHS2 ACCHS2 HPDO 3 VER2 POLCHS1 ACCHS1 ACVSSEP 2 VER1 POLHS2 ACHS2 ACRXC1 1 VER0 POLHS1 ACHS1 ACRXC0 LSB 0 XXXX 0000 XX00 0000 0000 0000 X000 0000 Reset value
ADDR[0:0] ADDR[0:1] ADDR[1:0] ADDR[1:1]

[1]
VERSION SIGN ACTIVITY1 ACTIVITY2
ACVS2 -
The read register address is specied with bits ADDR1 and ADDR0 of register READADDR.
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9.3 Offset registers (R, G and B)

The offset registers contain a 9-bit value which controls the clamp level for the RGB channels. The 8 LSBs are in the offset registers and the 1 MSB is in the coarse gain control register. The relationship between the programming code and the level of the clamp code is given in Table 19. The reset value is: clamp code = 0 and ADC output = 0.
Table 17. Register OFFSETR (00h) OFFSETG (03h) OFFSETB (06h) Reset Table 18. Bit 7 to 0 Offset registers (00h, 03h, 06h) bit allocation 7 OR7 OG7 OB7 0 6 OR6 OG6 OB6 0 5 OR5 OG5 OB5 0 4 OR4 OG4 OB4 0 3 OR3 OG3 OB3 0 2 OR2 OG2 OB2 0 1 OR1 OG1 OB1 0 0 OR0 OG0 OB0 0
Offset registers (00h, 03h, 06h) bit description Symbol OR[7:0] Description offset R channel; LSB in this register and MSB bit OR8 in register COARSER offset G channel; LSB in this register and MSB bit OG8 in register COARSEG offset B channel; LSB in this register and MSB bit OB8 in register COARSEB
OFFSETR (address: 00h)
OFFSETG (address: 03h) 7 to 0 OG[7:0]
OFFSETB (address: 06h) 7 to 0 OB[7:0]
Table 19. Value
Coding for clamp level and ADC output ADC output (code transition)
OR8 OR7 OR6 OR5 OR5 OR3 OR2 OR1 OR0 Clamp OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0 code (decimal) OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 1 0 0 1 0 24 23 : 1 0 +1 : 63 64 : 120 121 : 128
1E9h 1EAh : 1FFh 000h 001h : 03Fh 040h : 078h 079h : 080h
24/23 23/22 : 1/0 0/1 1/2 : 63/64 64/65 : 120/121 121/122 : 128/129
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Coding for clamp level and ADC output continued ADC output (code transition)
Table 19. Value
OR8 OR7 OR6 OR5 OR5 OR3 OR2 OR1 OR0 Clamp OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0 code (decimal) OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0 : 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 134 135
: 086h 087h
: 134/135 135/136
9.4 Coarse registers (R, G and B)

The coarse gain of the AGC is controlled with 7 bits. The code gain can vary from 32 to 95; see Table 22.
Table 20. Register COARSER (01h) COARSEG (04h) COARSEB (07h) Reset Table 21. Bit 7 6 to 0 7 6 to 0 7 6 to 0 Table 22. Value Coarse gain registers (01h, 04h, 07h) bit allocation with reset 7 OR8 OG8 OB8 0 6 CR6 CG6 CB6 1 5 CR5 CG5 CB5 0 4 CR4 CG4 CB4 0 3 CR3 CG3 CB3 0 2 CR2 CG2 CB2 1 1 CR1 CG1 CB1 1 0 CR0 CG0 CB0 0
Coarse gain registers (01h, 04h, 07h) bit description Symbol OR8 CR[6:0] OG8 CG[6:0] OB8 CB[6:0] Description offset R channel; MSB bit of offset value coarse gain of the AGC for R channel offset G channel; MSB bit of offset value coarse gain of the AGC for G channel offset B channel; MSB bit of offset value coarse gain of the AGC for B channel
COARSER (address: 01h)
COARSEG (address: 04h)
COARSEB (address: 07h)
Coarse register CR6 CR5 CR4 CR3 CR2 CR1 CR0 Vi (full-scale) CG6 CG5 CG4 CG3 CG2 CG1 CG0 CB6 CB5 CB4 CB3 CB2 CB1 CB0 Gain ADC
32 33 : 63 64 65 : 69
0 0 0 1 1 1
1 1 1 0 0 0
0 0 1 0 0 0
0 0 1 0 0 0
0 0 1 0 0 1
0 0 1 0 0 0
0 1 1 0 1 1
1.000 0.992 : 0.753 0.746 0.738 : 0.706
1.000 1.008 : 1.328 1.340 1.355 : 1.416
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Coarse register continued CR6 CR5 CR4 CR3 CR2 CR1 CR0 Vi (full-scale) CG6 CG5 CG4 CG3 CG2 CG1 CG0 CB6 CB5 CB4 CB3 CB2 CB1 CB0 Gain ADC
Table 22. Value
70 : 95
1 1
0 0
0 1
0 1
1 1
1 1
0 1
0.698 : 0.500
1.432 : 2.000
9.5 Fine registers (R, G and B)

Fine gain control is done with 3 bits allowing 8 intermediate values between two values of consecutive coarse gain.
Table 23. Register FINER (02h) FINEG (05h) FINEB (08h) Reset Table 24. Bit 7 to 3 2 to 0 7 to 3 2 to 0 7 to 3 2 to 0 Table 25. Value Fine gain registers (02h, 05h, 08h) bit allocation with reset 7 X 6 X 5 X 4 X 3 X 2 FR2 FG2 FB2 0 1 FR1 FG1 FB1 0 0 FR0 FG0 FB0 0
Fine gain registers (02h, 05h, 08h) bit description Symbol FR[2:0] FG[2:0] FB[2:0] Description not used ne gain of the AGC for R channel not used ne gain of the AGC for G channel not used ne gain of the AGC for B channel
FINER (address: 02h)
FINEG (address: 05h)
FINEB (address: 08h)
Fine gain control bits (example for coarse register value 32) FR2 FG2 FB2 FR1 FG1 FB1 0 0 1 1 0 0 1 1 FR0 FG0 FB0 0 1 0 1 0 1 0 1 1.000 1.001 1.002 1.003 1.004 1.005 1.006 1.007 Fine steps of gain ADC
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 1
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9.6 Sync-on-green register

Table 26. Bit Symbol Reset Access Table 27. Bit 7 SOG - sync-on-green register (address 09h) bit allocation 7 DO 0 W 6 UP 0 W 5 0 W 4 0 W 3 CKREFS 0 W 2 SOGSEL 0 W 1 SOGI1 0 W 0 SOGI0 1 W FTRILEVEL STRILEVEL
SOG - sync-on-green register (address 09h) bit description Symbol DO Description test bit for forcing charge pump current down 0 = reset value 1 = forcing down
UP
test bit for forcing charge pump current up 0 = reset value 1 = forcing up
FTRILEVEL
denes the 3-level function mode 0 = automatic 3-level 1 = level selection with bit STRILEVEL
STRILEVEL
forces the state of 3-level function 0 = not 3-level mode 1 = 3-level mode
CKREFS
enables the PLL Ckref signal to be selected 0 = same as input 1 = input inverted
SOGSEL
enables the reference PLL between HSYNC input and SOG input to be selected 0 = HSYNC input 1 = SOG input
1 to 0
SOGI[1:0]
denes the SOG charge pump current; values are given in % of sync pulse/line length 00 = 14.8 % maximum (TV standards) and non-VESA standards 01 = 12.6 % maximum (all standards) 10 = 8.6 % maximum (HDTV standards) and non-VESA standards 11 = 0 test mode
9.7 PLL control register

Table 28. Bit Symbol Reset Access PLLCTRL- PLL control register (address 0Ah) bit allocation 7 IP1 0 W 6 IP0 1 W 5 Z2 0 W 4 Z1 1 W 3 Z0 1 W 2 DR2 1 W 1 DR1 0 W 0 DR0 0 W
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Table 29. Bit 7 to 6
PLLCTRL - PLL control register (address 0Ah) bit description Symbol IP[1:0] Description charge pump current value to increase the bandwidth of the PLL 00 = 800 A 01 = 1200 A 10 = 1600 A 11 = 2000 A
5 to 3
Z[2:0]
internal resistance value for the Voltage Controlled Oscillator (VCO) lter to be selected 000 = not used 001 = 1.56 k 010 = 1.25 k 011 = 1.00 k 100 = 0.80 k 101 = 0.64 k 110 = 0.51 k 111 = 0.41 k
3 to 0
DR[2:0]
PLL temperature phase drift to be compensated. The optimized value of this register is 001. These bits add a delay on the clock reference input of the PLL as a function of the temperature of the die. 000 = +1.75 step phase 001 = 0.3 step phase 010 = 4.3 step phase 011 = 6.2 step phase 100 = 2.2 step phase
9.8 Phase register

Table 30. Bit Symbol Reset Access Table 31. Bit 7 to 4 3 to 0 PHASE - phase register (address 0Bh) bit allocation 7 PA4 0 W 6 PA3 0 W 5 PA2 0 W 4 PA1 0 W 3 PA0 0 W 2 VCO2 1 W 1 VCO1 0 W 0 VCO0 1 W
PHASE - phase register (address 0Bh) bit description Symbol PA[4:0] VCO[2:0] Description phase shift value for the clock pixel; see Table 32 VCO gain control; see Table 33
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Table 32. PA4 0 0 : 1 1 Table 33. VCO2 0 0 0 0 1 1 1 1
Phase registers bits PA3 0 0 : 1 1 VCO gain control VCO1 0 0 1 1 0 0 1 1 VCO0 0 1 0 1 0 1 0 1 VCO gain (MHz/V) 13 30 60 60 105 105 135 no oscillation Pixel clock frequency (MHz) 12 to 22 22 to 45 45 to 62 62 to 85 85 to 120 120 to 176 176 to 270 PA2 0 0 : 1 1 PA1 0 0 : 1 1 PA0 0 1 : 0 1 Phase shift (deg) 0 11.25 : 337.50 348.75
9.9 PLL divider registers

Table 34. Bit Symbol Reset Access Table 35. Bit 7 DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit allocation 7 CKEXT 0 W 6 SCHCKREFO 0 W 5 EPSI1 0 W 4 EPSI0 0 W 3 DI11 0 W 2 DI10 1 W 1 DI9 1 W 0 DI8 0 W
DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit description Symbol CKEXT Description external clock selection 0 = internal PLL 1 = external clock
SCH CKREFO
shift of pixel counter reference (Ckref) with one clock pixel period 0 = not active 1 = active enables the resynchronization edge of CKREFO to be selected; they are test bits 00 = reset value for proper operation PLL divider ratio; these are the 4 MSBs of the 12-bit value; see Table 38
5 to 4 3 to 0
EPSI[1:0] DI[11:8]
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Table 36. Bit Symbol Reset Access Table 37. Bit 7 to 0 Table 38. DI11 0 : 1 0 : 1
DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit allocation 7 DI7 1 W 6 DI6 0 W 5 DI5 0 W 4 DI4 1 W 3 DI3 1 W 2 DI2 0 W 1 DI1 0 W 0 DI0 0 W
DIVLSB - PLL divider ratio (LSB) register (address 0Dh) bit description Symbol DI[7:0] Description PLL divider ratio; these are the 8 LSBs of the 12-bit value; see Table 38
PLL divider ratio VDI9 0 : 1 VDI8 0 : 1 VDI7 0 : 1 VDI6 1 : 1 VDI5 1 : 1 VDI4 0 : 1 DI3 0 : 1 DI2 1 : 1 DI1 0 : 1 DI0 0 : 1 4095 PLL divider ratio 100
VDI10
9.10 Horizontal sync registers

Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be smaller than the PLL divider.
Table 39. 7 HSYNCL9 0 HSYNCL1 0 HBACKL3 1 HDISPL7 0 Table 40. Bit 9 to 0 9 to 0 HSYNCL, HBACKL and HDISPL (address 0Eh, 0Fh, 10h, 11h) bit allocation 6 HSYNCL8 0 HSYNCL0 0 HBACKL2 0 HDISPL6 0 5 HSYNCL7 1 HBACKL9 0 HBACKL1 0 HDISPL5 0 4 HSYNCL6 0 HBACKL8 0 HBACKL0 0 HDISPL4 0 3 HSYNCL5 0 HBACKL7 1 HDISPL11 0 HDISPL3 0 2 HSYNCL4 1 HBACKL6 1 HDISPL10 1 HDISPL2 0 1 HSYNCL3 0 HBACKL5 1 HDISPL9 0 HDISPL1 0 0 HSYNCL2 0 HBACKL4 1 HDISPL8 1 HDISPL0 0 Register address 0Eh
Register address 0Fh
Register address 10h
Register address 11h
Sync registers (0Eh to 11h) bit description Description
Symbol
HSYNCL[9:0] length of the Hsync signal; in number of pixel clock cycles; minimum value is 16 HBACKL[9:0] interval between the Hsync active edge and the rst active pixel; in number of pixels; minimum value is 16
11 to 0 HDISPL[11:0] number of active pixels for one line; length of the data enable signal; minimum value is 16
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9.11 Coast register

Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals the VSYNC input.
Table 41. Bit Symbol Reset Access Table 42. Bit COAST - coast register (address 12h) bit allocation 7 PRE COAST2 0 W 6 PRE COAST1 0 W 5 PRE COAST0 0 W 4 POST COAST4 0 W 3 POST COAST3 0 W 2 POST COAST2 0 W 1 POST COAST1 0 W 0 POST COAST0 0 W
COAST - coast register (address 12h) bit description Description programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the vertical sync signal
Symbol
7 to 5 PRECOAST[2:0]
4 to 0 POSTCOAST[4:0] programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the vertical sync signal
9.12 Horizontal sync selection register

Table 43. Bit Symbol Reset Access Table 44. Bit 7 to 4 3 HSYNCSEL - horizontal sync selection register (address 13h) bit allocation 7 X W 6 X W 5 X W 4 X W 3 TESTCNT 0 W 2 BYSEPA 1 W 1 HSSEL 0 W 0 HSS 0 W
HSYNCSEL - horizontal sync selection register (address 13h) bit description Symbol TESTCNT Description not used this bit is used to test the pixel counter 0 = normal mode 1 = test mode
BYSEPA
enables the sync separator for the PLL reference to be bypassed 0 = Hsync from the separator 1 = bypass of the sync separator
HSSEL
enables either the HSYNC or CHSYNC input signal to be selected 0 = HSYNC input 1 = CHSYNC input
HSS
enables either the HSYNC or CHSYNC input signal to be inverted 0 = non-inverted 1 = inverted
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9.13 Vertical sync selection register

Table 45. Bit Symbol Reset Access Table 46. Bit 7 to 5 4 VSYNCSEL - vertical sync selection register (address 14h) bit allocation 7 X W 6 X W 5 X W 4 TSTCOAST 0 W 3 COE 0 W 2 VSS 0 W 1 COSSEL2 0 W 0 COSSEL1 0 W
VSYNCSEL - vertical sync selection register (address 14h) bit description Symbol TSTCOAST Description not used switches a multiplexer to select the output signal on pin VSYNCO 0 = output of the separator function 1 = output of the coast function
COE
enables coast mode 0 = coast mode 1 = no coast mode
VSS
enables VSYNC input signal to be inverted 0 = non-inverted 1 = inverted
COSSEL2
selects signal for coast PLL mode 0 = signal selected with bit COSSEL1 1 = pin coast
COSSEL1
can be used for the coast PLL mode; see bit COSSEL2 0 = VSYNC input 1 = VSYNC from the sync separator
9.14 Clamp register

Table 47. Bit Symbol Reset Access Table 48. Bit 7 6 CLAMP - clamp register (address 15h) bit allocation 7 X W 6 HSOSEL 0 W 5 CLPSEL2 1 W 4 CLPSEL1 0 W 3 CLPH 0 W 2 CLPENL 0 W 1 ICLP 0 W 0 CLPT 0 W
CLAMP - clamp register (address 15h) bit description Symbol HSOSEL Description not used denes the signal on the output HSYNCO; see Section 8.3 0 = Hsync from the Hcounter 1 = Ckref is reference of the PLL
CLPSEL2
can be used to select the clamp signal 0 = Hsync signal generated by the pixel counter 1 = signal selected with bit CLPSEL1
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Table 48. Bit 4
CLAMP - clamp register (address 15h) bit description continued Symbol CLPSEL1 Description can be used to select the clamp signal; see bit CLPSEL2 0 = PLL reference signal 1 = clamp input
CLPH
inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 46) 0 = clamp inhibited during Vsynco 1 = clamp active during Vsynco
CLPENL
denes if clamp input works on edge or on level 0 = on edge; for all frequencies (must be preferably chosen) 1 = on level; only for frequencies below 45 MHz to have proper clamp function
1 0
ICLP CLPT
dedicated for test mode; should be forced to logic 0 denes if the test mode of the clamp is active 0 = not active 1 = active
9.15 Inverter register

Table 49. Bit Symbol Reset Access Table 50. Bit 7 6 INVERTER - inverter register (address 16h) bit allocation 7 X W 6 COS 0 W 5 CLPS 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W CKREFOINV DEOINVRGB HSOINVRGB VSOINVRGB FIELDOINV
INVERTER - inverter register (address 16h) bit description Symbol COS Description not used enables the COAST input signal to be inverted 0 = non-inverted 1 = inverted
CLPS
enables the CLAMP input signal to be inverted 0 = non-inverted 1 = inverted
CKREFOINV
enables the output CKREFO to be inverted 0 = non-inverted 1 = inverted
DEOINVRGB
enables the output DEO to be inverted 0 = non-inverted 1 = inverted
HSOINVRGB
enables the output HSYNCO to be inverted 0 = non-inverted 1 = inverted
TDA8754_7
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NXP Semiconductors
TDA8754
Table 50. Bit 1
INVERTER - inverter register (address 16h) bit description continued Symbol VSOINVRGB Description enables the output VSYNCO to be inverted 0 = non-inverted 1 = inverted
FIELDOINV
enables the output FIELDO to be inverted 0 = non-inverted 1 = inverted
9.16 Output register

Table 51. Bit Symbol Reset Access Table 52. Bit 7 OUTPUT - output register (address 17h) bit allocation 7 RGBSEL 0 W 6 TEN 0 W 5 AGCSEL1 0 W 4 AGCSEL0 0 W 3 BLKEN 0 W 2 DMXRGB 0 W 1 ODDARGB 0 W 0 SHIFTRGB 0 W
OUTPUT- output register (address 17h) bit description Symbol RGBSEL Description denes which RGB input will be used 0 = input 1 1 = input 2
TEN
enables the track and hold operating mode to be selected 0 = mode enable; must be set to logic 0 for proper operation 1 = mode disable
5 to 4
AGCSEL[1:0]
dene the output on pin AGCO 00 = RAGC 01 = GAGC 10 = BAGC 11 = not used
BLKEN
inhibits the blanking mode during clamp 0 = blanking active; during the blanking period, the RGB outputs of the ADC are xed at the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater or equal to 0, or forced to 0 if these values are negative. 1 = blanking not active
DMXRGB
determines whether all pixels go to port A or if pixels go alternately to port A and B. The maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode. 0 = port A 1 = port A and B
ODDARGB
denes the parity of the pixels 0 = even pixel on port A 1 = odd pixel on port A
SHIFTRGB
denes output on port A and B 0 = synchronous 1 = interleaved
TDA8754_7
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NXP Semiconductors
TDA8754
9.17 Output enable register 1

Table 53. Bit Symbol Reset Access Table 54. Bit 7 to 5 4 OUTPUTEN1 - output enable 1 register (address 18h) bit allocation 7 X W 6 X W 5 X W 4 BOENRGB 1 W 3 AOENRGB 1 W 2 OROEN 1 W 1 0 W 0 0 W TOUTERGB TOUTSRGB
OUTPUTEN1 - output enable 1 register (address 18h) bit description Symbol BOENRGB Description not used enables output port B to be set to high-impedance 0 = active signal 1 = high-impedance
AOENRGB
enables output port A to be set to high-impedance 0 = active signal 1 = high-impedance
OROEN
enables outputs Out Of Range to be set to high-impedance 0 = active signal 1 = high-impedance
TOUTERGB
denes if the test mode of the output buffer is active or not 0 = mode normal 1 = mode test
TOUTSRGB
denes the state of the output in test mode 0 = forces output to LOW 1 = forces output to HIGH
9.18 Output enable register 2

Table 55. Bit Symbol Reset Access Table 56. Bit 7 OUTPUTEN2 - output enable 2 register (address 19h) bit allocation 7 CKROEN 1 W 6 CSOEN 1 W 5 1 W 4 1 W 3 HPDOEN 1 W 2 VSOENRGB 1 W 1 CLPOEN 1 W 0 FIELDOEN 1 W DEOENRGB HSOENRGB
OUTPUTEN2 - output enable 2 register (address 19h) bit description Symbol CKROEN Description enables the output CKREFO to be set to high-impedance 0 = active signal 1 = high-impedance
CSOEN
enables the output CSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance
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NXP Semiconductors
TDA8754
Table 56. Bit 5
OUTPUTEN2 - output enable 2 register (address 19h) bit description continued Symbol DEOENRGB Description enables the output DEO to be set to high-impedance 0 = active signal 1 = high-impedance
HSOENRGB
enables the output HSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance
HPDOEN
enables the output HPDO to be set to high-impedance 0 = active signal 1 = high-impedance
VSOENRGB
enables the output VSYNCO to be set to high-impedance 0 = active signal 1 = high-impedance
CLPOEN
enables the output CLPO to be set to high-impedance 0 = active signal 1 = high-impedance
FIELDOEN
enables the output FIELDO to be set to high-impedance 0 = active signal 1 = high-impedance
9.19 Clock output register

Table 57. Bit Symbol Reset Access Table 58. Bit 7 to 5 4 CLKOUTPUT - clock output register (address 1Ah) bit allocation 7 X E 6 X W 5 X W 4 0 W 3 0 W 2 CKDATINV 0 W 1 0 W 0 1 W CKSELRGB DLYCLKRGB OUTOSCILL CKOENRGB
CLKOUTPUT - clock output register (address 1Ah) bit description Symbol CKSELRGB Description not used enables the selection of the signal on the pin CKDATA 0 = clock of output buffers; signal Ckdata 1 = pixel clock of the converter; signal Ckadco
DLYCLKRGB
enables a delay of 2 ns to be added to the clock Ckdata 0 = no delay 1 = 2 ns delay
CKDATINV
enables the polarity of the output CKDATA to be inverted 0 = non-inverted 1 = inverted
TDA8754_7
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NXP Semiconductors
TDA8754
Table 58. Bit 1
CLKOUTPUT - clock output register (address 1Ah) bit description continued Symbol OUTOSCILL Description enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the internal oscillator on the output 0 = Ckdata 1 = for test
CKOENRGB
enables the output CKDATA to be set to high-impedance 0 = active signal 1 = high-impedance
9.20 Internal oscillator register

Table 59. Bit Symbol Reset Access Table 60. Bit 7 to 2 1 INTOSC - internal oscillator register (address 1Bh) bit allocation 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 0 W 0 0 W SWITCHOSC INTOSCOFF
INTOSC - internal oscillator register (address 1Bh) bit description Symbol SWITCHOSC Description not used enables a multiplexer to be switched; signal insertion on the input of the separator and coast block, between the internal oscillator and pin CKEXT 0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = test mode
INTOSCOFF
disables the internal oscillator for the separator function, the coast gate and activity detection 0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast, activity detection and sync separator is done 1 = disabled
9.21 Power management register

Table 61. Bit Symbol Reset Access Table 62. Bit 7 to 4 3 2 PWRMGT - power management register (address 1Eh) bit allocation 7 X W 6 X W 5 X W 4 X W 3 SHCKDMX 0 W 2 SHCKADC 0 W 1 STBY 0 W 0 DVIRGB 0 W
PWRMGT - power management register (address 1Eh) bit description Symbol SHCKDMX SHCKADC Description not used test bits; should be set to logic 0 for proper operation test bits; should be set to logic 1 for better performances
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NXP Semiconductors
TDA8754
Table 62. Bit 1
PWRMGT - power management register (address 1Eh) bit description continued Symbol STBY Description enables the RGB block to be forced into the Standby mode, except activity detection, I2C-bus registers. In the Standby mode, all outputs are in high-impedance state, except pin HPDO which is still active. If the IC is in the Power-down mode, this bit has no effect 0 = IC active 1 = Standby mode
DVIRGB
this bit must be set to logic 0 for proper operation
9.22 Read register

Table 63. Bit Symbol Reset Access Table 64. Bit 7 to 2 1 to 0 READADDR - read register (address 1Fh) bit allocation 7 X W 6 X W 5 X W 4 X W 3 X W 2 X W 1 ADDR1 0 W 0 ADDR0 0 W
READADDR - read register (address 1Fh) bit description Symbol ADDR[1:0] Description not used register address to be read 00 = read register 0 01 = read register 1 10 = read register 2 11 = read register 3
9.23 Version register

Table 65. Bit Symbol Reset Access Table 66. Bit 7 to 4 3 to 0 VERSION - version register (read register 0) bit allocation 7 X R 6 X R 5 X R 4 X R 3 VER3 0 R 2 VER2 0 R 1 VER1 0 R 0 VER0 0 R
VERSION - version register (read register 0) bit description Symbol VER[3:0] Description not used version of the IC
9.24 Sign detection register

The sign bits are set at logic 0 when the input is a mostly LOW input signal.
TDA8754_7
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NXP Semiconductors
TDA8754
Table 67. Bit Symbol Reset Access Table 68. Bit 7 to 6 5
SIGN - sign register (read register 1) bit allocation 7 X R 6 X R 5 POLVS2 0 R 4 POLVS1 0 R 3 POLCHS2 0 R 2 POLCHS1 0 R 1 POLHS2 0 R 0 POLHS1 0 R
SIGN - sign register (read register 1) bit description Symbol POLVS2 Description not used sign of VSYNC2 input 0 = non inverted 1 = inverted
POLVS1
sign of VSYNC1 input 0 = non inverted 1 = inverted
POLCHS2
sign of CHSYNC2 input 0 = non inverted 1 = inverted
POLCHS1
sign of CHSYNC1 input 0 = non inverted 1 = inverted
POLHS2
sign of HSYNC2 input 0 = non inverted 1 = inverted
POLHS1
sign of HSYNC1 input 0 = non inverted 1 = inverted
9.25 Activity detection 1 register

Table 69. Bit Symbol Reset Access ACTIVITY1 - activity detection 1 register (read register 2) bit allocation 7 ACVS2 0 R 6 ACVS1 0 R 5 ACSOG2 0 R 4 ACSOG1 0 R 3 ACCHS2 0 R 2 ACCHS1 0 R 1 ACHS2 0 R 0 ACHS1 0 R
TDA8754_7
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NXP Semiconductors
TDA8754
Table 70. Bit 7
ACTIVITY1 - activity detection 1 register (read register 2) bit description Symbol ACVS2 Description activity of VSYNC2 input 0 = not active 1 = active
ACVS1
activity of VSYNC1 input 0 = not active 1 = active
ACSOG2
activity of SOGIN2 input 0 = not active 1 = active
ACSOG1
activity of SOGIN1 input 0 = not active 1 = active
ACCHS2
activity of CHSYNC2 input 0 = not active 1 = active
ACCHS1
activity of CHSYNC1 input 0 = not active 1 = active
ACHS2
activity of HSYNC2 input 0 = not active 1 = active
ACHS1
activity of HSYNC2 input 0 = not active 1 = active
9.26 Activity detection register 2

Remark: It should be noted that activity, sign and polarity detection will be correctly set after a maximum delay of: 6 frame periods + 50 ms.
Table 71. Bit Symbol Reset Access ACTIVITY2 - activity detection 2 register (read register 3) bit allocation 7 X R 6 ASD 0 R 5 3LEVEL 0 R 4 ACFIELD 0 R 3 HPDO 0 R 2 ACVSSEP 0 R 1 ACRXC1 0 R 0 ACRXC0 0 R
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TDA8754
Table 72. Bit 7 6
ACTIVITY2 - activity detection 2 register (read register 3) bit description Symbol ASD Description not used indicates if parasite sync pulses have been detected 0 = not detected 1 = detected
3LEVEL
state of the sync separator input 0 = Hsync 1 = 3-level Hsync
ACFIELD
activity of the sync separator FIELDO output 0 = not active 1 = active
HPDO
copy of the HPDO output state 0 = stable state on input 1 = new input
ACVSSEP
activity of the sync separator (Vsync output) 0 = not active 1 = active
1 0
ACRXC1 ACRXC0
test bit test bit
10. Limiting values

Table 73. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VCC Vi Vi(SCL) Vi(SDA) Io Tstg Tamb Tj Vesd Parameter supply voltage supply voltage differences input voltage I2C-bus clock input voltage I2C-bus data input voltage output current storage temperature ambient temperature junction temperature electrostatic discharge voltage human body model, LQFP144 package referred to GNDA referred to GNDD referred to GNDD Conditions Min 0.5 0.5 0.5 0.5 0.5 55 10 3000 Max +5 +0.5 +4.5 +6.5 +6.5 50 +150 +70 150 +3000 Unit V V V V V mA C C C V
TDA8754_7
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TDA8754
11. Thermal characteristics

Table 74. Symbol Rth(j-a) Thermal Characteristics Parameter thermal resistance from junction to ambient Conditions in free air; JEDEC4L LQFP144 package LBGA208 package Rth(j-c) thermal resistance from junction to case LQFP144 package 35 30 8.1 8.5 K/W K/W K/W Min Typ Max Unit
12. Characteristics
Table 75. Characteristics Tamb = 25 C unless otherwise specied. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO VCC analog supply voltage digital supply voltage output stage supply voltage analog supply current digital supply current output stage supply current supply voltage difference VCCA to VCCD VCCO to VCCD VCCA to VCCO Ptot P total power dissipation power dissipation Power-down mode Standby mode R, G and B ampliers RGB inputs: pins RIN1, GIN1, BIN1, RIN2, GIN2 and BIN2 Vi(p-p) Ii Ci Ri Ampliers B Gc bandwidth coarse gain 3 dB; Tamb = 25 C minimum coarse gain; code = 32 maximum coarse gain; code = 95 G/T amplier gain stability variation minimum coarse gain; with temperature code = 32 700 0 6 2 MHz dB dB % input voltage range (peak-to-peak value) input current input capacitance input resistance 0.5 40 50 3 1.0 +40 V A pF k 100 165 165 1.0 10 120 +100 +165 +165 1.3 mV mV mV W mW mW 3.0 3.0 3.0 3.3 3.3 3.3 180 125 1 3.6 3.6 3.6 V V V mA mA mA Parameter Conditions Min Typ[1] Max Unit
TDA8754_7
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TDA8754
Table 75. Characteristics continued Tamb = 25 C unless otherwise specied. Symbol GE(rms) Parameter full-scale channel-to-channel matching (RMS value) clamp level accuracy Conditions minimum coarse gain; code = 32 fCLK = 25 MHz; clamp code = 20 fclk = 270 MHz; DR = 2160 Min Typ[1] Max 2.5 Unit %
R, G and B clamp Nclamp 1 bit
Phase-Locked Loop (PLL); see Table 76 JPLL(p-p) DR fPLL fref step step fs(max) INL DNL ENOB ct S/N SFDR THD td(o) th(o) tsu(o) long term PLL phase jitter (peak-to-peak value) divider ratio output clock frequency reference clock frequency number of phase shift steps from drift phase shift step maximum sampling frequency integral non-linearity differential non-linearity effective number of bits crosstalk signal-to-noise ratio spurious free dynamic range total harmonic distortion output delay output hold time output setup time fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz fclk = 270 MHz; fi = 10 MHz 100 10 15 270 48 1.9 390 11.25 0.6 0.25 7.6 48 55 55 4 480 4095 270 150 2 1.3 0.6 45 48 5.2 6 deg MHz bit bit bit dB dB dB dB ns ns ns MHz kHz ps
Analog-to-Digital Converters (ADCs); minimum coarse gain
Data timing; 10 pF load; see Figure 4
LV-TTL digital inputs and outputs Input pins CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK and CLP VIL VIH LOW-level input voltage HIGH-level input voltage 0 2.0 0.8 V VCCD(TTL) V
Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO, HSYNCO, VSYNCO, FIELDO, CLPO, CKREFO and CSYNCO VOL VOH LOW-level output voltage HIGH-level output voltage IOH = 1 mA IOL = 1 mA 2.4 0.4 V V
Data clock output Output pin CKDATA fCKDATA(max) Data outputs Output pins RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO and CSYNCO fdata(max)
TDA8754_7
maximum buffer frequency
140
MHz
maximum buffer frequency
70
MHz
Product data sheet
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NXP Semiconductors
TDA8754
Table 75. Characteristics continued Tamb = 25 C unless otherwise specied. Symbol Parameter Conditions Min Typ[1] Max Unit Hsync inputs Input pins HSYNC1, HSYNC2, CHSYNC1 and CHSYNC2 tW(Hsync)(min) minimum pulse width tW(Hsync)(max) maximum pulse width SOG inputs Input pins SOGIN1 and SOGIN2 Vsync(G) Vsync(G) sync-on-green pulse amplitude high/low differential amplitude of 3-level pulse 150 20 mV % in % of total horizontal line 250 20 ns %
I2C-bus (fast mode; 5 V tolerant) Pins SCL and SDA fSCL VIL VIH Cb
[1]
clock frequency LOW-level input voltage HIGH-level input voltage capacitive load
0 2.0 -
400 0.8 5.5 400
kHz V V pF
Typical values are measured at VCCA = VCCA(SOG) to GNDA(SOG) or VCCA(R) to GNDA(R) or VCCA(G) to GNDA(G) or VCCA(B) to GNDA(B) = 3.3 V; VCCD = VCCD(TTL) to GNDD(TTL) or VCCD(ADC) to GNDD(ADC) or VCCD(I2C) to GNDD(I2C) or VCCD(MCF) to GNDD(MCF) or VCCD(TTL) to GNDD(TTL) or VCCD(SLC) to GNDD(SLC) = 3.3 V; VCCO = VCCO(BB) to GNDO(BB) or VCCO(BA) to GNDO(BA) or VCCO(GB) to GNDO(GB) or VCCO(GA) to GNDO(GA) or VCCO(RB) to GNDO(RB) or VCCO(RA) to GNDO(RA) or VCCO(CLK) to GNDO(CLK) = 3.3 V.
Table 76. Examples of PLL settings and performance VCCA = VCCD = VCCO = 3.3 V; Tamb = 25 C[1]. Video standard fref (kHz) fclk (MHz) DR Ko Cz (nF) (MHz/V) CP (pF) IP (A) Z () Long-term time jitter RMS (ps) VGA 60 Hz; VESA: 640 480 31.469 25.175 50 78.75 108 135 162 202.5 229.5 800 1040 1312 1688 1688 2160 2160 2160 30 60 60 105 105 105 135 135 220 220 220 220 220 220 220 220 680 680 680 680 680 680 680 680 1200 1200 1600 1600 1600 2000 1600 2000 510 510 640 510 640 640 800 640 500 370 220 185 145 135 95 85 p-p (ps) 3000 1980 1320 1110 870 810 570 510
SVGA 72 Hz; VESA: 48.08 800 600 XGA 75 Hz; VESA: 1024 768 60.02
SXGA 60 Hz; VESA: 63.98 1280 1024 SXGA 75 Hz; VESA: 80.00 1280 1024 UXGA 60 Hz; VESA: 75.00 1600 1200 UXGA 75 Hz; VESA: 93.75 1600 1200 UXGA 85 Hz; VESA: 106.25 1600 1200
[1]
PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
TDA8754_7
Product data sheet
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NXP Semiconductors
TDA8754
13. Timing
VOH CKDATA sample N + 1 sample N + 2 50 % VOL sample N
RGB input th(o) RGB outputs A7 to A0, B7 to B0, DEO, HSYNCO, CKREFO td(o) VOH DATA N2 DATA N1 tsu(o) DATA N DATA N+1 50 % VOL
mce410
Fig 4. Data timing diagram
TDA8754_7
Product data sheet
Rev. 07 3 May 2007
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Product data sheet Rev. 07 3 May 2007
NXP B.V. 2007. All rights reserved. TDA8754_7
NXP Semiconductors
R, G, B in
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CS
ckdivo ckphi
ckrefin
possibility to add a clock period with bit SCHCKREFO HSYNCL HBACKL

1 hb hb1 1 hd
HDISPL
hd1 hd2
hcount
hs
hs1 hs2
hsyncin
dein
ckadco
ADC out
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
mdb107
TDA8754
HSYNCL, HBACKL and HDISPL must be long 16 (minimum value in number of pixel clock cycles).
46 of 57
Fig 5. Timing diagram
NXP Semiconductors
TDA8754
ckrefin
HSYNCO
CKREFO
DEO
CKDATA
RGB outputs A7 to A0
10
11
12
13
14
15
16
17
18
19
20
mdb201
HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckren. CKREFO is LOW during 8 clock pulses.
Fig 6. Output format port A
ckrefin
HSYNCO
CKREFO
DEO
CKDATA bit SHIFTRGB = 0 RGB outputs A7 to A0 RGB outputs B7 to B0 RGB outputs A7 to A0 RGB outputs B7 to B0 28 2 4 6 8 10 12 14 16 18
27
11
13
15
17
bit SHIFTRGB = 1 28 2 4 6 8 10 12 14 16 18
27
11
13
15
17
19
mdb108
Fig 7. Output formats ports A and B; even pixels port A and odd pixels port B
TDA8754_7
Product data sheet
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NXP Semiconductors
TDA8754
ckrefin
HSYNCO
CKREFO
DEO
CKDATA bit SHIFTRGB = 0 RGB outputs A7 to A0 RGB outputs B7 to B0 27 1 3 5 7 9 11 13 15 17
28
10
12
14
16
18
mdb200
Fig 8. Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 0
ckrefin
HSYNCO
CKREFO
DEO
CKDATA bit SHIFTRGB = 1 RGB outputs A7 to A0 RGB outputs B7 to B0 27 1 3 5 7 9 11 13 15 17
28
10
12
14
16
18
mce411
Fig 9. Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 1
TDA8754_7
Product data sheet
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48 of 57
NXP Semiconductors
TDA8754
14. Application information

VCCD SCL SDA VCCD
R21 4.7 k R20 4.7 k
VCCD GNDD(SLC)
VCCO GNDO(TTL)
VCCD GNDD(MCF)
VCCD GNDO(CLK) GNDD(I2C)
VCCO VCCO
GNDO(RA)
VCCD(MCF)
CKDATA VCCO(CLK)
CKEXT VCCD(SLC)
VSYNCO VCCO(TTL)
A0 VCCD(I2C)
CKREFO
VCCO(RA) 110
CSYNCO
HSYNCO
VSYNC1
VSYNC2
STBDVI
FIELDO
COAST
ACRX1
ACRX2
HPDO DEO
CPLO
TDO
SDA
TCK
SCL
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
VCCD
GNDD(TTL) VCCD(TTL) HSYNC2 CHSYNC2 VCCA(PLL) HSYNC1 CHSYNC1 GNDA(PLL)

C1 220 nF C2 680 pF C3 1 F C4 1 F C5
109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ROR GNDO(RB) VCCO(RB) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 GNDO(GA) VCCO(GA) GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 GOR GNDO(GB) VCCO(GB) GB7 GB6 GB5 GB4 GB3 out green B VCCO out green A VCCO out red B VCCO out red A 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GB2
001aac978
CLP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 GB1
VCCA
CZ GNDA(CPO) CP PMO GNDA(SUB) CAPSOGIN1 CAPSOGO CAPSOGIN2 GNDA(SOG) SOGIN1 VCCA(SOG) SOGIN2 VCCA(R) RIN1 GNDA(R1) RIN2 GNDA(R2) DEC RBOT RCLPC VCCA(G) GIN1 GNDA(G1) GIN2 GNDA(G2) GBOT GCLPC VCCA(B)
SOGIN1 SOGIN2 VCCA RIN1 RIN2

330 pF C6 330 pF C7 1 F C8 1 F C9 C10 C11 100 nF 100 nF 4.7 nF
TDA8754HL
VCCA GIN1
C12 1 F C13
GIN2
1 F C14 C15 100 nF 4.7 nF
VCCA
DIS
GNDD(SUB)
PWD
TEST
BB0
BB1
BB2
BB3
BB4
BB5
BB6
GNDD(ADC)
BB7
GNDO(BB)
BOR
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
GNDO(BA)
GNDA(B1)
GNDA(B2)
BCLPC
AGCO
BBOT
BIN1
BIN2
VCCD(ADC)
VCCO(BB)
out blue B
out blue A
C16 1 F
C17 1 F C18 100 nF
C19 4.7 nF
VCCD
VCCO
VCCO
BIN1
BIN2
Fig 10. Application diagram
TDA8754_7
VCCO(BA)
GB0
Product data sheet
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72
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15. Package outline

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
c
y X
A 108 109 73 72 ZE
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B v M B 36 bp v M A 37
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7 o 0
o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Fig 11. Package outline SOT486-1 (LQFP144)

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LBGA208: plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm
SOT774-1
ball A1 index area
A2 A1 detail X
e1 e
1/2 e
C b
v M C A B w M C
y1 C
T R P N M L K J H G F E D C B A 1/2 e
e2
ball A1 index area
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.65 A1 0.45 0.35 A2 1.20 0.95 b 0.55 0.45 D 17.2 16.8 E 17.2 16.8 e 1 e1 15 e2 15 v 0.25 w 0.1 y 0.12 y1 0.35
OUTLINE VERSION SOT774-1
REFERENCES IEC --JEDEC MO-192 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 02-05-14
Fig 12. Package outline SOT774-1 (LBGA208)

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16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 Surface mount reow soldering description.
16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ne pitch SMDs. Reow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature prole. Leaded packages, packages with solder balls, and leadless packages are all reow solderable. Key characteristics in both wave and reow soldering are:
Board specications, including the board nish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering

Key characteristics in wave soldering are:
Process issues, such as application of adhesive and ux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath specications, including temperature and impurities

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16.4 Reow soldering

Key characteristics in reow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reow temperature prole; this prole includes preheat, reow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classied in accordance with Table 77 and 78
Table 77. SnPb eutectic process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 78. 235 220 Lead-free process (from J-STD-020C) Package reow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reow soldering, see Figure 13.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature proles for large and small components
For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description.
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17. Revision history

Table 79. Revision history Release date 20070503 Data sheet status Product data sheet Change notice Supersedes TDA8754_6 Document ID TDA8754_7 Modications:
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 8.2.4: added remark on clamp noise Product data sheet Product specication Preliminary specication Objective specication Objective specication Objective specication TDA8754_5 TDA8754_4 TDA8754_3 TDA8754_2 TDA8754_1 -
TDA8754_6 (9397 750 14984) TDA8754_5 (9397 750 13199) TDA8754_4 (9397 750 12016) TDA8754_3 (9397 750 11551) TDA8754_2 (9397 750 10598) TDA8754_1 (9397 750 04134)
20050616 20040518 20030930 20030716 20030417 19980930
TDA8754_7
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18. Legal information

18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualication Production
Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.
Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus logo is a trademark of NXP B.V.
19. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com
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20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.1.1 8.1.1.2 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.1.1 9.1.2 9.1.2.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . 13 Functional description. . . . . . . . . . . . . . . . . . . 13 Power management . . . . . . . . . . . . . . . . . . . . 13 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down mode . . . . . . . . . . . . . . . . . . . . . 14 Analog video input . . . . . . . . . . . . . . . . . . . . . 14 Analog multiplexers. . . . . . . . . . . . . . . . . . . . . 14 Activity detection. . . . . . . . . . . . . . . . . . . . . . . 14 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 HSOSEL, DEO and SCHCKREFO. . . . . . . . . 15 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sync-on-green . . . . . . . . . . . . . . . . . . . . . . . . 16 Programmable coast. . . . . . . . . . . . . . . . . . . . 17 Data enable . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sync separator . . . . . . . . . . . . . . . . . . . . . . . . 17 3-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C-bus register description . . . . . . . . . . . . . . 18 I2C-bus formats. . . . . . . . . . . . . . . . . . . . . . . . 18 Write 1 register . . . . . . . . . . . . . . . . . . . . . . . . 18 Write all registers . . . . . . . . . . . . . . . . . . . . . . 19 Read register . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus registers overview . . . . . . . . . . . . . . . 22 Offset registers (R, G and B) . . . . . . . . . . . . . 24 Coarse registers (R, G and B) . . . . . . . . . . . . 25 Fine registers (R, G and B). . . . . . . . . . . . . . . 26 Sync-on-green register . . . . . . . . . . . . . . . . . . 27 PLL control register. . . . . . . . . . . . . . . . . . . . . 27 Phase register. . . . . . . . . . . . . . . . . . . . . . . . . 28 PLL divider registers . . . . . . . . . . . . . . . . . . . . 29 Horizontal sync registers . . . . . . . . . . . . . . . . 30 Coast register . . . . . . . . . . . . . . . . . . . . . . . . . 31 Horizontal sync selection register . . . . . . . . . . 31 Vertical sync selection register . . . . . . . . . . . . 32 Clamp register . . . . . . . . . . . . . . . . . . . . . . . . 32 Inverter register. . . . . . . . . . . . . . . . . . . . . . . . 33 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 18.1 18.2 18.3 18.4 19 20 Output register . . . . . . . . . . . . . . . . . . . . . . . . Output enable register 1. . . . . . . . . . . . . . . . . Output enable register 2. . . . . . . . . . . . . . . . . Clock output register . . . . . . . . . . . . . . . . . . . Internal oscillator register . . . . . . . . . . . . . . . . Power management register . . . . . . . . . . . . . Read register . . . . . . . . . . . . . . . . . . . . . . . . . Version register . . . . . . . . . . . . . . . . . . . . . . . Sign detection register . . . . . . . . . . . . . . . . . . Activity detection 1 register . . . . . . . . . . . . . . Activity detection register 2 . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 35 36 37 37 38 38 38 39 40 41 42 42 45 49 50 52 52 52 52 53 55 56 56 56 56 56 56 57
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.
NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 May 2007 Document identifier: TDA8754_7

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Triple 8-bit video ADC up to 270 Msample/s

4. Quick reference data

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 07 3 May 2007

Values are not yet guaranteed.

CKEXT CKREFO SDA SCL

Fig 1. Block diagram

Product data sheet

Rev. 07 3 May 2007

Fig 2. Pin conguration LQFP144 package

ball A1 index area 1 A B C D E F G H J K L M N P R T

Transparent top view

Fig 3. Pin conguration LBGA208 package

7.2 Pin description

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

Table 4. Symbol VSYNCO DEO SDA n.c. n.c. n.c.

Product data sheet

Rev. 07 3 May 2007

Table 4. Symbol GNDA GNDA GNDA

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

8.1.1 Power management

Product data sheet

Rev. 07 3 May 2007

Power-down mode In Power-down mode the status of the blocks is as follows:

8.2 Analog video input

8.2.1 Analog multiplexers

Product data sheet

Rev. 07 3 May 2007

The reference ladders regulators are integrated.

8.3 HSOSEL, DEO and SCHCKREFO

Product data sheet

Rev. 07 3 May 2007

Product data sheet

Rev. 07 3 May 2007

83.5 % 86.0 % 90.5 % test mode

8.6 Programmable coast

8.7 Data enable

8.8 Sync separator

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 07 3 May 2007

9. I2C-bus register description

SDA line Description

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 07 3 May 2007

Table 8. Bit Byte 1 7 to 1 0 Byte 2 7 to 6 5 4 to 0 Byte 3 7 to 0