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A/D and D/A Converters

Andrea Baschirotto
University of Lecce
73100 Lecce - Italy
E-mail: andrea.baschirotto@unile.it

Piero Malcovati and Franco Maloberti


University of Pavia
27100 Pavia - Italy
E-Mail: piero@ele.unipv.it

A. Baschirotto, et al. "A/D and D/A Converters"


ADC and DAC Functionality

• An ADC generates a digital code output as a response to an analogue input signal

• A DAC is a circuit which generates an analogue output signal as a response to a


digital code input
The analogue signal is usually a voltage or a current

F.S.
ANALOG SIGNAL

7/8
6/8
5/8
4/8
3/8
2/8
1/8

000 001 010 011 100 101 110 111 F.S.

DIGITAL CODE

A. Baschirotto, et al. "A/D and D/A Converters"


ADC and DAC Performances
F.S.

ANALOG SIGNAL
7/8
6/8
5/8
4/8
3/8
2/8
1/8

000 001 010 011 100 101 110 111 F.S.

DIGITAL CODE

• Ideal input-output transfer characteristic. It requires an infinite digital resolution.


• The digital resolution if a converter indicates the number of bits used to code the
analog signal. It is expressed in number of bits or as percentage (or part per
million) of the full scale.

• For N bits of resolution 2N different digital codes are allowed. Each code will not
represent a value but an interval of the input voltage.

Step or Channel = VFS/(2N - 1)

A. Baschirotto, et al. "A/D and D/A Converters"


A/D converters: typical architecture
Quantization
noise

Anti Output
Analog
digital
input Aliasing A/D word
signal Filter

Fs

• The Anti-Aliasing Filter limits the filter band to Fs/2 in order to avoid aliasing of
different components.
• Aliasing of two sampled waveforms:
2
• They give the same output samples
and cannot be distinguished 1

Fin1=Fs/10 and Fin2=Fs–Fin1 give the same -1


output samples
-2
0 2 4 6 8 10

A. Baschirotto, et al. "A/D and D/A Converters"


Quantization error (2bit case)
• Input signal
1

0.8 • Quantization error =


0.6

0.4
= Input signal – Quantized signal
Analog value [V]

0.2

-0.2

-0.4 0.5

-0.6 0.4

0.3
-0.8

Quantization error [V]


0.2
-1
0 0.5 1 1.5 2
0.1
Time
0
• Quantized signal -0.1

1.5 -0.2

-0.3
1 -0.4

-0.5
Quantized value [V]

0.5 0 0.5 1 1.5 2


Time

-0.5

-1

-1.5
0 0.5 1 1.5 2
Time

A. Baschirotto, et al. "A/D and D/A Converters"


Quantization Noise
Amplitude

It takes into account the finite resolution

∆/2 2
∆/2 2 1 ⌠ 2

e rms = ∆ e de = 12

−∆/2 ∆/2
–∆

The quantization noise is assumed to be a random process:


• incorrelated with the input signal
• with a uniform distribution in the amplitude range [+∆/2, –∆/2]
• with a white noise spectrum in the frequency range [0–Fs/2]
A. Baschirotto, et al. "A/D and D/A Converters"
Quantization error

Vin/FS 1

3/4

1/2 Erms decreases of a factor 2 (6 dB) for


additional bit
∆V
1/4

in
CODE A/D
000
001

010
011

111
100
101
110

Quantization error
quantization
∆V noise
CODE
000
001

010
011

111
100
101
110

∆V
Erms =
12

A. Baschirotto, et al. "A/D and D/A Converters"


Quantization Noise
Spectrum

It is assumed that the quantization noise has white spectrum

Power
of noise
spectral ∆2 Fs • The noise spectral density
density 12 2 is given by:

Quantization
Fs/2 Fs
Eq(f) = erms

 Fs

noise

A. Baschirotto, et al. "A/D and D/A Converters"


Dynamic range

N +FSC
Let' consider an N bit ADC with 2 quantization levels
2·FSC
∆= N
2 –1
–FSC

2·FSC2 2·FSC2
   
2  2N–1   N 
2 ∆    2 
nrms = 12 = 12 ≈ 12
2
2 FSC
s rms = 2
 FSC
2 
s 2 
 
 rms  2   3 2·N
SNR [dB] = 10·log10  2 = 10·log10  2·FSC2  = 10·log 10 2 2 
nrms   N  
  2  
  
 
12
SNR [dB] = 1.76 + N · 6.02
A. Baschirotto, et al. "A/D and D/A Converters"
Static conversion errors

Gain error
Analog Analog
actual actual
response ideal response
• Offset error ideal
response response
offset

• Gain error
Code Code

• Integral linearity

• Differential linearity Step


amplitude Vact -Videal

• Non monotonicity

A. Baschirotto, et al. "A/D and D/A Converters"


Differential Non-Linearity

DNL = Sin (Cm +1 ) − Sin (Cm ) − 1LSB

ideal

Cm+1 real

Cm
Output
Code

DNL=0.5LSB

Sin
Input Signal

A. Baschirotto, et al. "A/D and D/A Converters"


DNL example (8bit ADC)

[LSB]

0 255
output code
• monotonic: -1 LSB < DNL < +1 LSB
• DNL gives extra noise on top of quantization noise

A. Baschirotto, et al. "A/D and D/A Converters"


Integral Non-Linearity
• INL = the deviation from a straight line
2n

code out

0 full scale
Sin

A. Baschirotto, et al. "A/D and D/A Converters"


INL example (8bit ADC)

[LSB]

0 255
output code
• INL gives extra distortion & noise on top of quatization noise

A. Baschirotto, et al. "A/D and D/A Converters"


Sampling time uncertainty (jitter)

10n
input signal
1n
100kS/s
100p
Sin +dSin Jitter 1MS/s
Sin (sec) 10p
10MS/s
1p
CMOS
t t+dt t [sec] 100MS/s
100f

10f
S in = A sin(ωt ) 2 −n 8 9 10 11 12 13 14 15 16
dSin < 1LSB } dt <
πf in Number of bits

• Example: audio = 16bit, 20kHz: dt < 0.25ns !

A. Baschirotto, et al. "A/D and D/A Converters"


A/D Converters: Total output noise
• Ideal case • Real case

fs=sample frequency distortion


sampling time
jitter DNL, INL,circuit noise
S S
2 1
ε rms = LSB2
12

0 0.5fs 0 0.5fs

• All noise and distortion sources have to be taken into account for DR evaluation
Quantization
Thermal
Jitter
INL & DNL

A. Baschirotto, et al. "A/D and D/A Converters"


A/D Converter: Equivalent Number Of Bit
• Ideal ADC: relation of signal to noise
Signal / noise = 1.76 + 6.02 n[dB ]
• Additional errors: distortion, clock junk, thermal noise etc. “Inverse” definition:
SINAD − 1.76
Effective Number Of Bits :
6.02
n
thermal
noise, jitter,
non-linearity
ENOB

DC specs
INL,DNL
What you get

Highest frequency

0
BW

A. Baschirotto, et al. "A/D and D/A Converters"


A/D Converter: Speed vs. Resolution
• A trade-off exists between Speed and Resolution

22 Sigma-Delta
20
Resolution(bit)

18
16 Pipeline/
14 subrange
12
10
Folding
8
6
4 Flash AD

1kHz 10kHz100kHz 1MHz 10MHz100MHz1GHz


Bandwidth
A. Baschirotto, et al. "A/D and D/A Converters"
A/D Converter power
F.o.M. = energy needed per conversion • signal bandwidth (BW)
[Joules]
• effective number of bits (n)
P
F.o.M. = 2n · 2 · BW • power dissipation (P)

22 super
audio 1 kW
20 1mW 1W
Resolution(bit)

18 GSM Basestation FoM = 5pJ


audio
16 GSM
800 kbit/s
14
12 Cable
DTV
10 1 µW video
8 40 kbit/s 40 Mbit/s
6 Storage
speech Intercon-
4 nectivity

1kHz 10kHz100kHz 1MHz 10MHz100MHz1GHz


Bandwidth

A. Baschirotto, et al. "A/D and D/A Converters"


A/D Converter methods
• Sequential converters: ............... Ramp converter
Successive approximation
• Parallel converters: .................... Flash
Interleaved
• Sequential converters: ............... Pipelined
• Error reduction techniques: ....... Algorithmic (with ratio independent multiplication by 2)
EPROM corrected
Self-calibration
Self-corrected
Dynamic element matching

• Oversampled converters

A. Baschirotto, et al. "A/D and D/A Converters"


Ramp A/D Converter

V
IN
INTEGRAT COMPAR.
V
REF

N-BIT
CONTROL
COUNTER

b0 b1 b2 b3 bN

• Low frequency applications (2N clock periods)


• Low cost
• Inherently monotonic

A. Baschirotto, et al. "A/D and D/A Converters"


Successive Approximation Register (SAR) A/D Converter

• Determines the digital conversion in N successive steps, through the comparison of


the input signal with its suitable approximations

• The approximations of the input signal are generated by a DAC controlled by a


"Successive Approximation Register (SAR)"
VR

Φsampl
V in Comp
S&H +
SAR PHASE
- Φconv CONTROL Φck
V ref
N-bits VR/2
DAC OUT

A. Baschirotto, et al. "A/D and D/A Converters"


Successive Approximation Register (SAR) A/D Converter
Charge redistribution Φ1

implementation
2N-1C 2N-2C 2C C C
-
+
bN-1 bN-1 bN-2 bN-2 b1 b1 b0 b0
Φ1
V in

Φ1
V ref
• During the first clock
period the circuit SAR
samples the input
• The total charge stored on the capacitive array is Qtot = 2N·C · (Vin – Vos)
• Sampling period => The operational amplifier is buffer connected
• Conversion cycle => The operational amplifier is used in open loop as a comparator
• Drawback: Overdrive recovery of the comparator
• Performance : Medium speed (10-20 kHz) & Medium accuracy (≅ 10 bit)

A. Baschirotto, et al. "A/D and D/A Converters"


Successive Approximation with Serial DAC

Φ0+ Φ 1
S1 Φ0
V
REF C1
C
-
S2 A1 -
-V
REF + A3 SAR
+
V
in Φ0 2C C
Φ0+ Φ 2
Φ0
C
Φ1
-
A2 Φ2
+

• The input signal is injected at the beginning of the conversion cycle. Each full clock
period +Vref or -Vref is added and the reminder is multiplied by two
• The active serial DAC with division by two generates the voltage sequence required
by the successive approximation algorithm without the need of a SAR

A. Baschirotto, et al. "A/D and D/A Converters"


Flash A/D Converter
compar
N
• It consists of (2 - 1) comparators used to compare
the input voltage with (2N - 1) reference voltages V
R1 b1

CODE LOGIC
b2
b3
V
R2 b4

• The conversion operation is performed in only one bN


clock period N
V [M = 2 - 1]
RM
V in

V ref V in

Rd /2

-
(2N-1)
Rd +

THERMOMETRIC to BINARY
(2N-2)
Rd +
bN-1
• The reference voltages are generated by a (2N-3)
- bN-2

resistor string divider + bN-3

b2
b1
- b0
(2)
Rd +

-
(1)
Rd/2 +

A. Baschirotto, et al. "A/D and D/A Converters"


Flash A/D Converter
Circuit solution
• The used comparator is the cascade of CMOS inverters with autozero

C az

Cp

• The autozero cycle of the comparators gives rise to charge pumping in the resistor
string network
• Key limitation: offset, components matching, loading
• Performance : Very High speed (>1GHz) & low accuracy (≤ 8 bit)

A. Baschirotto, et al. "A/D and D/A Converters"


Two-step Subranging Flash A/D Converters

• A coarse conversion (m bit) is followed by a fine conversion (n bit)

ΦS
Φ1 Φ2 Φ3
ΦH
V in m-bits + n-bits
S&H ADC DAC - Σ K ADC Φ1

Φ2
V ref V ref (K / 2m)V
MSB’s ref LSB’s
Φ3

• If the subtraction and the amplification by the factor K do not require additional clock
cycles, the conversion time is two clock cycles
• The two-step flash architecture requires two full flash A/D converters, a D/A
converter and a subtracting amplifier
• The number of comparators required is significantly reduced with respect to the full
flash architecture => Only (2m + 2n – 2) instead of 2n + m
A. Baschirotto, et al. "A/D and D/A Converters"
Two-step Subranging Flash A/D Converters
Limitations

ΦS
Φ1 Φ2 Φ3
ΦH
V in m-bits + n-bits
S&H ADC DAC - Σ K ADC Φ1

Φ2
V ref V ref (K / 2m)V
MSB’s ref LSB’s
Φ3

• The subtracting amplifier can be the real limit to speed, since subtraction and
amplification must settle within half of a quantization step, thus requiring time
• Successive samples are weakly correlated => The subtracting amplifier must ensure
large output swing within the subtracting period
• Typically an additional clock cycle for the subtraction and amplification operation is
required
• The mismatch between the coarse and fine reference voltages or an error in the
multiplying factor degrade the linearity

A. Baschirotto, et al. "A/D and D/A Converters"


Interleaved A/D Converter
Φ1
S&H A/D

Φ2 Φ1
S&H A/D
Φ2

DEMUX
IN
Φ3 Φ3
S&H A/D
OUT

ΦN
ΦN 1 2 3 4 N
S&H A/D

• An array of M complete converters: area is increases by a factor M


• It may be used with any converter type, but they must be relatively fast and small
• Crosstalk between adjacent channels
• Throughput increased by a factor M
A. Baschirotto, et al. "A/D and D/A Converters"
Pipeline A/D Converter

• Cascade of stages operating in parallel each producing one or more bits


• Bits relative to successive input samples are determined during the same clock cycle
• The sampling rate increases at the expense of a system latency

1 2 K-1 K
V in(nT)
ADC res ADC res ADC res ADC
+ + + +
RES RES RES RES

j j j j
bkj-1,…,b(k-1)j+1, b(k-1)j b(k-1)j-1,…,b(k-2)j+1, b(k-2)j b2j-1,…,bj+1, bj bj-1,…,b1, b0
Sample n Sample (n-1) Sample (n-K-2) Sample (n-K-1)

A. Baschirotto, et al. "A/D and D/A Converters"


Pipeline A/D Converter
1 2 K-1 K
V in(nT)
ADC res ADC res ADC res ADC
+ + + +
RES RES RES RES

j j j j
bkj-1,…,b(k-1)j+1, b(k-1)j b(k-1)j-1,…,b(k-2)j+1, b(k-2)j b2j-1,…,bj+1, bj bj-1,…,b1, b0
Sample n Sample (n-1) Sample (n-K-2) Sample (n-K-1)

• The signal processing in the analog path must preserve the information content of the
residual bits
• The circuit complexity and the power consumption in a pipeline stage are significantly
lower than in a complete data converter
• The pipeline architecture achieves a better trade-off between speed, area and power
consumption with respect to the interleaved architecture
• The total number of stages K required to obtain a given resolution decreases as the
number of bits of each stage increases, but the analog processing required for
each stage also increases at the expense of speed and the power consumption
=> Trade-off
A. Baschirotto, et al. "A/D and D/A Converters"
Pipeline A/D Converter
• Typically few bits per
+
stage are used => Vin
S&H
j-bit j-bit
Σ 2j
-
CMOS switched ADC DAC

capacitor
implementation of a
one bit per stage
pipeline A/D Vin -Vref /2 +
S&H + Σ 2
converter -
+Vref /2 -

Vref /2

Φo
• During the even clock phase Φe the
Φe Φe
circuit samples the input voltage on C1
two equal capacitors C1 and C2 Vin Φe C2
and the comparator performs the -
auto-zero by storing the offset on Φe COMP Φe
Φo
+
capacitor Cos Cos
-
• During the odd clock phase Fo Φo +
capacitor C1 is connected in
feedback ‹ C1 receives the charge Vref /2 b Vref 0
i
delivered by C2
• Digital correction techniques allows to recover large threshold error
A. Baschirotto, et al. "A/D and D/A Converters"
Digital correction techniques

• Basic idea: to perform a coding redundant and to use the redundant bits for a digital
correction

• The correction can be made using informations stored in a memory (RAM, EPROM)
or automatically with a suitable algorithm

• EPROM corrected

• Self calibration

• Self corrected

• Dynamic Element Matching

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: EPROM corrected
• Used with the successive approximation algorithm
• Whatever input voltage is "reached" by the decision tree through only one path
• If we make the branches of the decision tree overlapped, the same input voltage is
"reached" with different paths (Redundancy)

VR VR

VR/2 VR/2

• A wrong decision to go ups can eventually corrected after few cycles

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: EPROM corrected (II)

IN

D!A CLOCK

REG.

SAR &
LOGIC

EPROM
FULL OUTPUT
ADDER

• Only part of the errors are covered


• EPROM programing after the packaging
• External reference

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self calibration (I)
• Used with the successive approximation algorithm
• A self calibration cycle measures the mismatch of the component values and stores
them in a memory
With weighted capacitor array

MAIN DAC
SAR

REG.
ADDER

DATA
REG.
LOGIC

SUBDAC CALIB. DAC

• 16 bits achievable

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self calibration (II)
• Self calibration cycle begins with the MSB precharged to zero while all other
capacitors are charged to Vref

REST OF THE ARRAY


-
C
+

VREF

REST OF THE ARRAY


-
C
+

VREF

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self calibration (III)
With algorithmic and multiplication by two converter
Vi n
S/H x2
TRIM
ARRAY
+ V
Ref
-

2
1.2

1 2 4 8 1 2 4 8

• Self calibration cycle: Vref is applied to the input. If the gain is smaller than 2 the
conversion result will be less than the full scale. If the gain is larger the converter will
over-range
• Calibration cycle easier, less digital control circuity and less memory
• 13 bits achievable

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self correction (I)

• Consider a k-stages subranging pipelined A/D converter

STAGE STAGE STAGE


#1 #2 #K

n bits n bits n bits


1 2 K

in + residue
S/H
-

ADC DAC

bits

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self correction (II)
• The non linearity of the ADC (only) can be corrected

+ 1/2 LSB

digital
- 1/2 LSB
code
residue

+ 1/2 LSB
analog input
- 1/2 LSB

1
• With an error within ± 2 LSB the residue voltage can range from ± 1 LSB

• The information is not lost if we avoid saturation in the successive stage


1
• If the input is > 2 LSB, 1 bit must be added to the code of the previous stage

1
• If the input is < - 2 LSB, 1 bit must be subtracted to the code of the previous stage

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Self correction (III)
IN
3 BIT 3 BIT 3 BIT 3 BIT

CORRECTION LOGIC

9BIT

STAGE 1 1/2 STAGE 2

• The circuit uses flash A/D converter with differential input and differential reference
comparators

Φ1 C Φ1

Φ2 4C Φ2
- Φ1
Φ1 +VREF Φ1
Φ2
+ S/H+ -
Φ2
4C Φ1
Φ2 -VREF +
Φ1 Φ2
C Φ1 S/H- Φ1

A. Baschirotto, et al. "A/D and D/A Converters"


Digital correction techniques: Dynamic Element Matching

Consider two current sources, nominally


equal IA
IB IA 2∆I

I1 = I + ∆ I
I2 = I - ∆ I I
B

• The mean value of IA and IB is I, the two


currents I1 and I2 are dynamically I
1
I
2
matched
2I 4I

I I I I I I

• Several DEM algorithms have been developed

A. Baschirotto, et al. "A/D and D/A Converters"


D/A Dynamic conversion parameters

• Conversion time

• Latency time

• Settling time

• Hysteresis

• Glitches

0111110 0111111 1000000 1000001 0111110 0111111 1000000 1000001

Ideal response

Glitch

A. Baschirotto, et al. "A/D and D/A Converters"


D/A Converter Methods
• Current Steering

• Resistor-based converters

• Capacitor-based converters

• Serial converters

• Duty cycle converters (pulse width modulation)


• In general the analog output variable A, voltage or current is proportional to a
reference Aref:
A out = Aref WN
where WN is an N bit word:
bN-1 bN-2 bN-1 b0
WN = + +....+ + ....+
21 22 2i 2

• The reference voltage or current generator can be internal or external to the chip
depending on the stability and accuracy requirement

A. Baschirotto, et al. "A/D and D/A Converters"


Current Steering D/A Converters
• Based on binary weighted current sources

I TOT
-

LSB
MSB +

I 2I 4I 8I N-1
2 I

• The switches are driven by the bits


• The current sources obtained by using I ref
ratioed transistors

Advantages:
• Small area for less than 8 bit
• Very high speed of operation (tens of MHz's)
A. Baschirotto, et al. "A/D and D/A Converters"
Current Steering D/A Converters
Problems • On off switching times of current sources (speed, glitches)
• Current source matching (linearity)
Solutions • Use a differential switch, to switch the current sources toward
the output or toward a fictitious load
To the fictitious To the load
load

M1 M2

Key point: waveforms driving the differential switch


• Suitable overlapping
Minimum swing

A. Baschirotto, et al. "A/D and D/A Converters"


Current Steering D/A Converters
• A possible solution for the differential switch driver

VDD
VBias,1
VDD

VBias,2

• The loads and the current source determine the swing


• The bias voltage contribute to modify the waveform overlapping
• The necessary swing is determined by the current and the transistor dimension in
the differential switch, which, in turn determines the capacitive load of the driver.

A. Baschirotto, et al. "A/D and D/A Converters"


Current Steering D/A Converters
Current switch matching

W   δI
2  δk'
2  δW 
2  δL
2  δV Th  2
2
I= k' L  (V GS - VTh)   =   + W  +   +4  
  I   k'    L  V GS - V Th

• VGS is assumed constant. It is true if the drop voltage along the ground connections
is negligible. (Remember: metal lines ≅ 40 µΩ/v)

Solutions:
• Use of a large number of transistors in parallel with W ≅ L; the error due to L and W
are uncorrelated and are summed quadratically; with N transistors in parallel the
error is reduced by a factor between  N/2 and 
√ √N
• Use of transistors closed to the mirroring element
• Use of large overdrive voltage

A. Baschirotto, et al. "A/D and D/A Converters"


Current Steering D/A Converters
Current switch matching

• Careful layout: same boundary effect

Drain
Source

2
1 3 Drain

4 Gate

A. Baschirotto, et al. "A/D and D/A Converters"


Resistor Ladder D/A Converters
• Binary weighted currents are also obtained with R-2R resistor networks
R
R R R 2R
Vref
Req
-
2R 2R 2R 2R 2R VO
+
R
S1 S2 S3 S4 SN vos + vn

V0  R 
+ v'out = (vos + vn) 1 + R 
 eq

• Limitations: Resistor mismatches and distortion from non-linear amplification of offset


and low-frequency noise
REST OF THE
• R-2R network require a high resistor matching for monotonicity LADDER

2R
• The current in the branches must be matched better than 1/2N 2R

A. Baschirotto, et al. "A/D and D/A Converters"


MOS Current Divider D/A Converter
I ref
V
B

V
B

R
S1 S2 S3 S4 SN

-
V
+ 0

• The non linearities of the transistors are cancelled at the first order
• Small silicon area
• Non inherently monotonic
• Only for low accuracy (< 6 bit)
• Noise and offset modulation

A. Baschirotto, et al. "A/D and D/A Converters"


Capacitive divider D/A Converters
• The capacitors are reset (FR) before each conversion
• The input digital word controls the analog switches
• The capacitors are binary weighted
• For high resolution the unity capacitance is very small

ΦR
+
C/32 C/32 C/16 C/8 C/4 C/2 C – VO

S1 S2 S3 S4 S5 S6

Vref

A. Baschirotto, et al. "A/D and D/A Converters"


Capacitive divider D/A Converters
• High resolution => Use of an attenuating capacitor
• The unity capacitance is multiplied by a factor k = 32
• Attenuating capacitor: CATT = C1 / (k – 1)

CATT=0.516 pF
+
0.5pF 0.5pF 1pF 2pF 4pF 8pF 0.5pF 1pF 2pF 4pF 8pF – V
OUT

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10

V
ref

C1=16 pF

A. Baschirotto, et al. "A/D and D/A Converters"


Resistive Divider D/A Converters

Vref
• The reference voltage is divided by a
string of equal resistors R b1

b2
• A particular voltage tap is selected with
R b1
a tree of switches
b3
• The input impedance of the buffer is R b1
very high
R b1
• Features b2

R VO
Intrinsically monotonic b1

b2
Sensitive to the buffer offset R b1

Delay due to several switches in R


series b1
b3

R b1
b2

A. Baschirotto, et al. "A/D and D/A Converters"


Resistive Divider D/A Converters

• Folded resistive string


• Parallel selection of 8 different voltage
taps

SWITCH TREE
• Tree of switches to select one of the 8
voltage taps
• Features
Intrinsically monotonic
Corner resistors difficult to
implement
Compact layout

b0 b1 b2 b3

A. Baschirotto, et al. "A/D and D/A Converters"


Resistive Divider D/A Converters
• Resistor matrix divides the reference Vref

voltage (XY selection)


• Output buffer required
• Features
High speed
Intrinsically monotonic
Up to 10 bits of resolution
Limitations due to the output buffer

Buffer

A. Baschirotto, et al. "A/D and D/A Converters"


Charge Redistribution D/A Converters
• The charge stored the capacitive array during one clock phase is redistributed in the
entire array during the other clock phase
• Offset insensitive architecture
• Output available only during one clock phase

Φ1

C/4 C/2 C +
C/2N–1

Vref

A. Baschirotto, et al. "A/D and D/A Converters"


Resistive and Capacitive D/A Converters
• The m MSBs are provided by a resistive divider DAC while the n LSBs are provided
by a capacitive charge redistribution DAC

R0
K = 2(n–1)
CONTROL SWITCHES

L = 2(m–1) Φ1
R1
-

R2 C/K C/4 C/2 C +

RL
MSB's

A. Baschirotto, et al. "A/D and D/A Converters"


Multiplying D/A Converter
• The charge stored in the array in one clock phase is injected into the feedback
capacitor during the other clock phase
• Features
Inverting or non-inverting
Offset insensitive

Φ1

Φ2
2C Φ1

+
C/2N–1 C/4 C/2 C

Vref

A. Baschirotto, et al. "A/D and D/A Converters"


Algorithmic D/A Converters

• The analog output is built in N successive clock cycles


• During each clock cycle the voltage in the loop is multiplied by 2

Φ0 + Φ1

S1 C
V C1
ref
S2 -
–V
A1
+
ref Φ0

2C C Φ2
Φ0 + Φ2
Φ2
C

-
A2
+

A. Baschirotto, et al. "A/D and D/A Converters"


Algorithmic D/A Converters
• Exact multiplication by 2
• Integrate the input signal two times
C2
Vin C1
-

• Exchange capacitors C1 and C2


C1

C2
-

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters

• The analogue voltage is generated serially bit by bit.

• The conversion of each bit usually requires one clock period

• Passive with division by two

• Active with multiplication by two

• Active with division by two

• Ramp converter

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Passive with division by two

• At the beginning of the conversion C2


(=C1) is discharged
S1 S3
• The word under conversion enters OUT
with the LSB first
V S2
• Before the capacitor C1 is charged to REF C1 S4 C2
Vref if the bit is 1, or discharged
otherwise, and in the successive
phase it is connected in parallel
with C2
• Use the superposition principle
• Large digital section
• Stray sensitive
• Clock feedthrough
• Capacitor mismatch

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Active with multiplication by two

• The word under conversion Φ0 + Φ 1


enters with the MSB first
S1
V
• The signal on the loop is REF C1
-
C
multiplied by two each full S2 A1
-V
clock period REF +
Φ0

• Stray and offset insensitivity in 2C C


Φ1
the by-two multiplication Φ0 + Φ 2 Φ2
• Charge injection C

• Capacitor mismatch -
A2
+

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Active with multiplication by two (II)
• The multiplication by two can be made ratio independent
Principle of operation:
C2
V C1
Integrate Vin twice in
-

C +
Vout = 2 · C1 Vin
2

Exchange capacitors C1

 C  C  C2
Vout = 2 C1 V in C2 = 2Vin -
 2   1
+

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Active with multiplication by two (III)

Problems: Offset
Clock feedthrough

Solution: Phase 1: S1, S4, S5, S6 and companions are


closed
S3
• Op-amp is in unity-gain closed loop
S4 configuration
S7 • C2 is charged to the input-offset
S5 • C2 is charged to the offset
C1 S6
S1 Phase 2: S2, S5, S7 and companions are closed
C2 • First charge injection
-
S2 Phase 3: S1, S4 and companions are closed
+
S1' C2 • op-amp is in unity gain closed loop
S6' configuration
C1
S7' • Second input sampling (offset insensitive)
S5' Phase 4: S2, S3, S5, S6 are closed
S4' • C1 is in feedback around op-amp
• C2 is injecting charge
S3'
• Second injection and capacitor exchange

• 12 bits of accuracy can be reached

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Active with division by two

Φ0 +Φ A

C3 Φ0
ΦB
Φ0 Φ1
V Φ0 Φ1 C2
REF
- Φ2

C1 +
Φ0+ Φ 2 Φ A= Φ 1 * b
Φ B= Φ 2 * b

• Offset insensitive
• Stray compensated
• Operates starting from the MSB
• Generates "useful" intermediate voltage levels

A. Baschirotto, et al. "A/D and D/A Converters"


Serial D/A Converters: Ramp converter
VREF
RAMP
GENERATOR S/H

b0
N-BIT b1
COUNTER COMPARAT.
bN

CLOCK

• Problem: the linearity of the generation of the ramp (integral nonlinearity)


The ramp generator can be a SC Φ0
integrator (staircase
Φ0
generator) C2
Φ1 Φ1
Φ2
• The timing accuracy is no more V
REF C1
important - Φ2
+
Φ2 Φ1
• Slow conversion rate V
OUT

• Inherently monotonic

A. Baschirotto, et al. "A/D and D/A Converters"


Duty-cycle converters
V
REF
• The basic idea is to generate a square
OUT
wave signal with duty-cycle CLOCK COUNTER
carry FLIP LOW
PASS
S FLOP
proportional to the digital word
R

COMPAR

• The low pass filter extracts the mean


value INPUT CODE

• Very low frequency applications

T
• The spectrum is pushed at higher
frequency:

A. Baschirotto, et al. "A/D and D/A Converters"


Which converter for high-resolution?
• Conventional A-to-D converters achieves high-resolution with the use of high-
accuracy integrated components

• High-accuracy integrated components can be obtained using high-cost solutions


(trimming) which however can increase the accuracy of only 2-3 bits

• ADC's are typically used as interface in mixed signal systems where the largest part
(area) is digital; the larger digital section therefore drives the use of digital
technology, in the scaled-down version to reduce chip size

• Scaled-down digital technologies can operate at very high speed but with poor
analog features (poor matching/accuracy)

• Oversampled Σ∆ ADC can achieve high-resolution using low-accuracy technology

speed vs. accuracy


in scaled down technology

A. Baschirotto, et al. "A/D and D/A Converters"


Oversampling converters
Quantization noise presents a uniform distribution in [0-Fs/2]
=> increasing the sampling frequency (oversample) F
OSR = 2·Fs
b
+ digital filtering the out-of-band noise

Signal Signal
Filter

Quantization Fb=Fs/2 Fs Fb Fs/2 Fs


Quantization
noise
noise

• reduces the in-band quantization noise (the power of noise is halved by doubling Fs)
• increases the resolution by 3dB for each sampling frequency doubling
• reduces the required accuracy of anti-aliasing frequency
• this process is limited by the maximum possible Fs
 F 
M = log2 2·Fs  DR = – 3.41 dB + 3·M dB
 b 

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ Noise Shaping

Quantization noise spectral density


2

Digital filter
1.5
Signal band
Standard quantization noise
1

1st order-shaped Quantization Noise


0.5

0
0 0.1 0.2 0.3 0.4 0.5
f/Fs

Use of Σ∆ modulation + digital filtering


• the in-band quantization noise is reduced
• the resolution is increased
• the out-of-band quantization noise is increased and it has to be filtered in the digital
domain
A. Baschirotto, et al. "A/D and D/A Converters"
General features of Σ ∆ modulator

Advantages
• Σ∆ systems can manage high accuracy data conversion with low accuracy circuit
solutions
• Small amount of analog parts (this allows to use a Σ∆ modulator as interface in
digital systems)
• Σ∆ systems can be implemented in standard CMOS technology

Draw-backs
• Σ∆ systems exchange resolution with speed thus they are limited to small signal
bandwidth
• High-speed analog and digital systems are needed (power and performance
limitation)
• No relation exists between input sample and output word
• Latency time

A. Baschirotto, et al. "A/D and D/A Converters"


Data conversion vs. Signal conversion

Data Conversion
• Isolated input sampler (spectra unimportant)
• sample errors specified
• one-to-one correspondence between input sample and output word
example: digital voltmeter

Signal conversion
• attention to waveform and spectrum
• occasional large sample error may be permissible
• RMS SNR specified
example: digital audio

A. Baschirotto, et al. "A/D and D/A Converters"


ADC Time response

Input signal

Conventional
ADC
latency

Sigma-delta
ADC
latency

• A conventional ADC is an FIR system


• A Sigma-Delta ADC is an IIR system

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ A/D Converter
General structure
Q
N o bit
Input Fs
Fs
analog AA Loop Quantizer Digital decimation
Filter (N bit ADC)

Bitstream
signal Filter Filter

DAC

Analog section Digital section


Σ∆ modulator)
(Σ (Decimator)

Degrees of freedom (design choices)


• Transfer function of the loop filter (lowpass or bandpass)


• Oversampling Ratio 

• Order of the loop filter  To increase the DR (No. bit)

• Number of bit of the quantizer 

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ A/D Converter
General structure
Q
N o bit
Input Fs
Fs
analog AA Loop Quantizer Digital decimation
Filter (N bit ADC)

Bitstream
signal Filter Filter

DAC

Analog section Digital section


Σ∆ modulator)
(Σ (Decimator)
• Architecture of the Modulator
Single-loop vs. cascade
Continuous-time vs. discrete time
Differential vs. Single-ended
Voltage vs. Current signals

• Trimming or digital (adaptive) correction

• Stability with or without limiters

• Use of dither signals

• Digital decimation filter


A. Baschirotto, et al. "A/D and D/A Converters"
Σ ∆ A/D Converter: Dynamic range
Q
N o bit
Input Fs
Fs
analog AA Loop Quantizer Digital decimation
Filter (N bit ADC)

Bitstream
signal Filter Filter

DAC

Analog section Digital section


Σ∆ modulator)
(Σ (Decimator)

• Considering only quantization noise

DR = k + (3+6·L)·M dB + 6·(N–1)

N quantizer number of bits

 F 
OSR Oversampling ratio 2·Fs 
 b

M = log 2 (OSR)
L Σ∆ modulator order
A. Baschirotto, et al. "A/D and D/A Converters"
Σ ∆ modulator performance summary (2002)
N DOR Power Quantizer
Process / Supply Filtering
bits (MS/s) (mW) B, bits
3rd-order 4b
[Geerts00] 15.8 2.5 0.65 m-DP@5V 295
Single-Loop DWA
3th-order 3b@last stage
[Brandt91] 12 2.1 1 m-DP@5V 41
2-1 Cascade No calibration
4th-order
[Marques98] 14.8 2.0 1 m-DP@5V 230 1b
2-1-1 Cascade
6th-order
[Feldman98] 13 1.4 0.7 m-DP@3.3V 81 3-level@last stage
2-2-2 Cascade
4th-order 4b@last stage
[Medeiro99] 13 2.2 0.7 m-SP@5V 55
2-1-1 Cascade No calibration
4th-order
[Geerts99] 15 2.2 0.5 m-DP@3.3V 200 1b
2-1-1 Cascade
4th-order 4b@all stages
[Fujimori00] 15 2.5 0.5 m-DP@5V 105
2-1-1 Cascade Bi-directional DWA
4th-order 5b@last stage
[Morizio00a] 13 2.2 0.35 m-DP@3.3V 99
2-2 Cascade dual quantization
4th-order 4b@all stages
[Morizio00b] 14 2.2 0.35 m-DP@3.3V 150
2-2-2 Cascade Bi-directional DWA
[Brooks97] 14.5 2.5 0.6 m DP@5V 550 (A+D) pipeline-overs
[Paul99] 12 18.0 1.2 m-DP@5V 324 pipeline-overs
[Paul99] 10.7 30.0 0.6 m-DP@5V 230 pipeline-overs

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ modulator key-words

• SNR vs. Input signal amplitude • Definitions


Dynamic range: Input signal
amplitude for SNR=0
S/(N+D) peak
SNR Peak: Maximum SNR
Overload Level: Input signal
amplitude at the SNR Peak
distortion
S/(N+D) [dB]
ideal
or
resonance resolution in
no. of bits
• In Σ∆ structures
real
Dynamic range ≠ SNR Peak
Input amplitude [dB] 0 dB [=Vref] (This is true for standard ADC)
Dynamic Overload
range level

A. Baschirotto, et al. "A/D and D/A Converters"


1st order Σ ∆ modulator

• MATLAB Simulation code


1 % First order SD modulator simulation
1 - z -1 Q clear; hold off; format short e; t0 = clock;

X=[0]; U=[0];

Y X U fs=1.024e6;
fin=fs/2^8; ain=0.25;
npoint=2^10; start=2^5;
analog Delay digital
signal signal
for i=2:npoint+start;
Y(i)=ain*sin(2*pi*i*fin/fs);
Delay DAC X(i)=(X(i-1)+(Y(i)-U(i-1)));
if X(i)>0, U(i)=1; else U(i)=-1; end;
z -1 end;
Uout=U(start+1:start+npoint);
fftU=20*log10(abs(fft(Uout)/length(Uout)));
plot(fftU)

fr=0:length(y1)-1;
fr=fr/max(fr);
axis([0 0.2 -100 10])
xlabel('f/Fs'); ylabel('Amplitude [dB]');
plot(fr,fftU)

A. Baschirotto, et al. "A/D and D/A Converters"


Time domain behaviour

1.5

0.5

Amplitude
0

-0.5

-1

-1.5

-2
0 10 20 30 40 50 60
Time

1 1

0.5 0.5
Amplitude

Amplitude
0 0

-0.5 -0.5

-1 -1

0 20 40 60 80 0 20 40 60 80 100 120
Time Time

A. Baschirotto, et al. "A/D and D/A Converters"


Time domain behaviour
0.4

0.2

Y
-0.2

-0.4
0 50 100 150 200 250 300

0
X

-1

-2
0 50 100 150 200 250 300
Time

• A certain correlation is present between input sinewave and integrator output

A. Baschirotto, et al. "A/D and D/A Converters"


Frequency domain behaviour
Σ ∆ Noise Shaping
-10
• Overall output spectrum
-20 input signal
-30

-40

Amplitude [dB]
-50

-60

-70

-80

-90
0 0.2 0.4 0.6 0.8 1
Normalized frequency f/Fs

• In-band output spectrum 0


input signal
-20
Amplitude [dB]

-40

-60

-80

-100
0 0.05 0.1 0.15 0.2
Normalized frequency f/Fs

A. Baschirotto, et al. "A/D and D/A Converters"


1st order Σ ∆ modulator
Dynamic range vs. OSR: DR = – 3.41 dB + 9.03·M dB

90

80

Dynamic range [dB]


70

60

50

40

30

20
3 4 5 6 7 8 9 10
log2(OSR)

• The Dynamic Range increases of 9dB for every OSR doubling

Example 1: To get DR = 60 dB in a 5kHz band


7.1 => Fs= 2·5kHz·138 = 1.38 MHz
=> OSR = 2 = 138
Example 2: To get DR = 80 dB in a 5kHz band
9.3 Fs= 2·5kHz·64 = 6.3 MHz
=> OSR = 2 = 630

A. Baschirotto, et al. "A/D and D/A Converters"


1st order single-bit Σ ∆ modulator

General features
3 3/2
• Dynamic range = OSR
 2·π

DR = – 3.41 dB + 9.03·M dB
• Low modulator complexity
• Low performance sensitivity to component non-idealities and mismatch
• Inherently stable (without excessive delay in the loop or integrator imperfections)
• Large peak in the SNR for DC or slowly varying signals, and the noise includes
single-frequency tones
• Dither is usually necessary (if the signal is not very busy, i.e. rapidly varying and
nearly random)

A. Baschirotto, et al. "A/D and D/A Converters"


2nd order Σ ∆ modulator

Y z -1 X z -1 W U
k1 k2
1 - z -1 1 - z -1

DR = – 11.12 dB + 15.05·M dB

A. Baschirotto, et al. "A/D and D/A Converters"


2st order Σ ∆ modulator
Dynamic range vs. OSR: DR = – 3.41 dB + 15.03·M dB

140

120

Dynamic range [dB]


100

80
2nd order
60

40 1st order

20
3 4 5 6 7 8 9 10
log2(OSR)

• The Dynamic Range increases of 15dB for every OSR doubling

Example 1: To get DR = 60 dB in a 5kHz band


4.8 => Fs= 2·5kHz·28 = 280 kHz (ex 1.38MHz in 1st order)
=> OSR = 2 = 28
Example 2: To get DR = 80 dB in a 5kHz band
6.1 Fs= 2·5kHz·64 = 680 kHz (ex 6.3MHz in 1st order)
=> OSR = 2 = 68

A. Baschirotto, et al. "A/D and D/A Converters"


2nd order Σ ∆ modulator
Output spectrum
• 2nd order modulator output spectrum
0

-20

-40
Amplitude [dB]

-60
• 1st order vs. 2nd order modulator in-
-80
band output spectrum
-100
0
-120
0 0.2 0.4 0.6 0.8 1 -20
f/Fs
-40

Amplitude [dB]
• 1st order vs. 2nd order modulator -60

-80

0 -100

-20 -120
0 0.05 0.1 0.15 0.2
f/Fs
-40
Amplitude [dB]

-60

-80

-100

-120
0 0.2 0.4 0.6 0.8 1
f/Fs

A. Baschirotto, et al. "A/D and D/A Converters"


2nd order Σ ∆ modulator

• Plot SNR vs. input signal amplitude

100

80

60
SNR [dB]

40

20

-20
-100 -80 -60 -40 -20 0
Input amplitude [dB]

7
• For OSR = 2 = 128 => DR = – 11.12 dB + 15.05·7 dB = 94.23dB

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ D/A Converter
Motivation (I)

• High-accuracy DAC are not easely realized (without trimming, etc...) in term of:
accurate frequency response
accurate linearity
Example: 16bit audio DAC: The input signal is a 16bit word at 44.1kHz. The DAC
must cancel the image, very close to the signal

signal bandwidth=20kHz
DAC analog filter with multi-bit input

word lenghth=16bit

Fs=44.1kHz

A. Baschirotto, et al. "A/D and D/A Converters"


Σ ∆ D/A Converter
Motivation (II)

• A digital interpolator is then added which increases the sampling frequency and
separate signal from image

signal bandwidth=20kHz
DAC analog filter with multi-bit input

word lenghth=16bit

Fs = k·44.1kHz

• The output word is now a 16bit word with high-frequency rate which should require
high-accuracy analog components.

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
Motivation (III)

signal bandwidth=20kHz
• The 16bit HF word is then DAC analog filter with 1bit input
translated into a 1bit word 16bit-to-1bit quantization noise
with a digital Σ∆
modulator, which pass to word lenghth=1bit
a 1bit code with added
quantization noise
Fs = k·44.1kHz

signal bandwidth=20kHz
• Finally the bitstream is filtered DAC analog filter with 1bit input
with an analog filter which
cancel the high-frequency
noise

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
Architecture

In Interpolation Sigma-Delta M-Bit Low-Pass Vout


Filter Modulator DAC Filter

N Bits @ fS N Bits @ OSR fS M Bits @ OSR fS

Fig. 10. Audio DAC chip block diagram.

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
Digital-to-Analog conversion interface: Single-bit vs. Multibit

Single-bit
+ Linear DAC
+ Simple
– Tones (single bit from single loop)
– Stability (order higher than 2th)

Multibit
+ Stability (for order higher than 2th)
+ Low step (output on more levels)
– Linear DAC
– Linearization algorithm
A. Baschirotto, et al. "A/D and D/A Converters"
DAC Σ ∆ Converter
Analog smoothing filter

• Low distortion: To avoid in-band folding of tones (present for low signal level)
• Low noise: To maintain the dynamic range featured by the previous oversampler
• Sampled-data structures for the first stage reduces coupling problem between the
input bitstream (digital signal) and the analog section
• The SC technique gives an accurate frequency response and allows to reduce the
effects of the bit-stream non-idealities (like clock jitter and non-accurate edges)
1.05
• Accurate SC transfer function can be
compensated in the FIR frequency
response FIR Preemphasis

Amplitude gain [dB]


1 Total

SC frequency response

0.95
0 5 10 15 20
Frequency [kHz]

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
SC Filter architecture
• Low-noise solution (Inverse-Follow-the-Leader-Feedback)

Vin Vin

Vout
Vout
vn1
vn1 vn2
vn2
vn3
vn3

Only the noise vn1 reaches the output node


• Low-distortion solution

Vin

Vout

vn1
vn2
vn3

Opamp 3 has to charge no capacitor => low slew-rate distortion


Vn1 and vn3 reach the output node

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
• Key features
Low-noise performance: to achieve large DR
High-linearity:
at high signal level, because the at low signal level, because large tones
distortion of the signal which are in (eventually present close to Fs/2)
the band reduces DR could be folded in the signal band
by non-linearity
=> at low signal level the linearity
appers lower

A. Baschirotto, et al. "A/D and D/A Converters"


DAC Σ ∆ Converter
Avoiding tones folding: Possible solution
• Use of digital Σ∆ modulator with small high-frequency tones
• MASH structure (multibit output)
• Use of dither (increased in-band quantization noise

A. Baschirotto, et al. "A/D and D/A Converters"


References: A/D Conversion Fundamentals
F. Maloberti, J. Franca, R. S. Soin, ”Analogue-Digital ASICs”, Peter Peregrinus, London, UK, 1991.
David A. Johns, Ken Martin, “Analog Integrated Circuit Design”, John Wiley, New York, USA, 1997.
Rudy van de Plassche, “Integrated Analog-To-Digital and Digital-To-Analog Converters”, Kluwer Academic Publishers, Dordrecht,
The Nederlands, 1994.
A. B. Grebene, “Bipolar and MOS Analog Integrated Circuits Design”, John Wiley, New York, USA, 1984.
Analog Devices, “Analog-Digital Conversion Handbook”, Prentice Hall, New Jersey, USA, 1986.
R. L. Geiger, P. E. Allen, N. R. Strader, “VLSI design Techniques for Analog and Digital Circuits”, Mc Graw Hill, New York, USA, 1990.
F. Maloberti, F. Francesconi, P. Malcovati and O. J. A. P. Nys, “Design Considerations on Low-Voltage Low-Power Data Converters”,
IEEE Transactions on Circuits and Systems, vol. 42, pp. 853-863, Nov. 1995.
V. Liberali, S. Brigati, F. Francesconi, F. Maloberti, “Progress in High-Speed and High-Resolution CMOS Data Converters”,
Microelectronics and Reliability, vol. 37, pp. 1411-1420, Sept. 1997

References: Full Flash and Two-Step Flash A/D Converters


K. Ono, “BiCMOS Flash A/D Converter, FCDL Error Suppressing Encode Logic”, IEEE Journal of Solid-State Circuits, vol. 30, pp.
1460-1464, Sept. 1997.
M. Yotsuyanagi, H. Hasegawa, M. Yamaguchi, M. Ishida, K. Sone, “A 2 V 10 bit 20Ms/s Mixed-Mode Subranging CMOD A/D
converter”, IEEE Journal of Solid-State Circuits, vol. 30, pp. 1533-1537, Dec. 1995.
B. Zojer, B. Astegher, H. Jessner, R. Petschacher, ”A 10 bit 75 MHz subranging A/D converter”, IEEE Journal of Solid-State Circuits,
vol. 25, pp. 1339-1346, Dec. 1990.
Y. Yoshi, M. Nakamura , K. Hirasawa, A. Kayanuma, K. Asano, “An 8 bit 350 MHz Flash ADC”, ISSCC Digest of Technical Papers, pp.
96-97, Feb. 1987.

A. Baschirotto, et al. "A/D and D/A Converters"


A. Dingwall, V. Zazzu, “An 8 MHz CMOS Subranging 8 bit A/D Converter”, IEEE Journal of Solid-State Circuits, vol. 20, pp. 1138-
1143, Dec. 1985.
A.Cremonesi, F. Maloberti, G. Torelli, C. Vacchi, "An 8-bit Two-Step Flash A/D Converter for Video Applications", Proceedings of
Custom Integrated Circuit Conference, pp. 6.3.1-6.3.4, May 1989.
Bang-Sup Song, S. H. Lee, M. F. Tompsett, “A 10 bit 15 MHz Recycling Two Step A/D Converter”, IEEE Journal of Solid-State
Circuits, vol. 25, pp. 1328-1337, Dec. 1990.

References: Folding, Interpolating and Interleaved A/D Converters


R. E. J. van de Grift, I. W. J. M. Rutten, M. van der Veen, “An 8 bit Video ADC Incorporating Folding and Interpolation Techniques”,
IEEE Journal of Solid-State Circuits, vol. 22, pp. 944-953, Dec. 1987.
C. J. van Valburg, R. J. van de Plassche, ”An 8 Bit 650 MHz Folding ADC”, IEEE Journal of Solid-State Circuits, vol. 27, pp. 1662-
1666, Dec. 1992.
P. Vorenkamp, R. Roovers, “A 12 bit 60 MS/s Cascaded Folding and Interpolating ADC”, IEEE Journal of Solid-State Circuits, vol. 32,
pp. 1876-1886, Dec. 1997.
A. G. W. Venes, R. van de Plassche, “An 80 MHz 80 mW 8 bit Folding A/D Converter with Distributed Track & Hold Preprocessing”,
IEEE Journal of Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
M. P. Flynn, D. J. Allstot, “CMOS Folding A/D Converters with Current-Mode Interpolation”, IEEE Journal of Solid-State Circuits, vol.
31, pp. 1248-1257, Dec.1996.
B. Nauta, A. G. W. Venes, “A 70 MS/s 110 mW 8-Bit CMOS Folding and Interpolating A/D Converter”, IEEE Journal of Solid-State
Circuits, vol. 30, pp. 1302-1308, Dec. 1995.
R. Roovers, “CMOS ADC 6bit 160 mW 3.3 V Interpolating Architecutre”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 938-944,
Dec. 1996.
M. K. Mayers, “Time-Interleaved ADC 12 bit 1 MHz 25 mW Low Power Operation”, IEEE Journal of Solid-State Circuits, vol. 31, pp.
169-178, Dec. 1996.

A. Baschirotto, et al. "A/D and D/A Converters"


W. C. Black Jr. and D. A. Hodges, “Time Interleaved Converter Arrays”, IEEE Journal of Solid-State Circuits, vol. 15, pp. 1022-1029,
Dec. 1980.
F. Goodenough, “Interpolators Put 10 bit 75 MHz A/D Converters in 8 bit Digital Process”, Electronic Design, pp. 29-30, Dec. 1989.
M. Steyaert, R. Roovers, J. Craninchx, “A 100 MHz 8 bit CMOS Interpolating A/D Converter”, Proceedings of Custom Integrated Circuit
Conference, pp 28.1.1-28.1.4, May 1993.

References: Pipeline A/D Converters


M. K. Mayers, S. W. Chin, “A 200 mW 1 MS/s 16 Bit Pipelined A/D Converter with On-Chip 32 Bit Microcontroller”, IEEE Journal of
Solid-State Circuits, vol. 315, pp. 1862-1872, Dec. 1996.
P. C. Yu, H. Lee, “A 2.5 V 12 Bit 5 MS/s Pipelined CMOS ADC”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1854-1861, Dec.
1996.
T. Hsiung, K. Bacrania, R. Gokhale, “BiCMOS Fully-Differential Pipelined A/D Converter, 10 Bit 40 MS/s”, IEEE Journal of Solid-State
Circuits, vol. 31, pp. 1507-1510, Dec. 1996.
D. W. Cline, “CMOS Pipelined A/D Converter, Power Optimized Design”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 294-303,
Dec. 1996.
T. B. Cho, P. R. Gray, “A 10 Bit MS/s 35 mW Pipeline A/D Converter”, IEEE Journal of Solid-State Circuits, vol. 30, pp. 166-172, Dec.
1995.
K. Nakamura, M. Hotta, L. R. Carley, D. J. Allstot, “An 85 mW 10 bit 40 MS/s CMOS Parallel Pipelined ADC”, IEEE Journal of Solid-
State Circuits, vol. 30, pp. 173-183, Dec. 1995.
C. Yu, C. C. Chen, J. J. Cho, “CMOS Pipelined ADC Current Mode Circuit Technique”, IEEE Journal of Solid-State Circuits, vol. 30,
pp. 522-532, Dec. 1995.
W. T. Colleran, T. H. Phan, A. A. Abidi, “A 10 bit 100 MS/s Pipelined A/D Converter”, ISSCC Digest of Technical Papers, pp. 68-69,
Feb. 1993.

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K. Kusumoto et al. “A 10 bit 20 MHz 30 mW Pipelined Interpolating CMOS ADC”, ISSCC Digest of Technical Papers, pp. 62-63, Feb.
1993.
Y-M. Lin, B. Kim, P. R. Gray, “A 13 Bit 2.5 MHz Self-Calibrated Pipelined A/D Converter in 3µm CMOS”, IEEE Journal of Solid-State
Circuits, vol. 26, pp. 628-636, Dec. 1991.
K. W. Martin, “A High-Speed High-Accuracy Pipelined A/D Converter”, Proceedings of Asilomar Conference on Circuits, Systems and
Computers, Nov. 1981.
B. S. Song, M. F. Tompsett, K. R. Lakshmikumar, “A 12 bit 1 MS/s Capacitor Error-Averaging Pipelined A/D Converter”, IEEE Journal
of Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.
P. Vorenkamp, J. P. M. Verdaasdonk, “A 10 Bit 50 MS/s Pipelined ADC”, ISSCC Digest of Technical Papers, pp. 32-33, Feb. 1992.
S. Sutarja, P. R. Gray, “A Pipelined 13 Bit 250 kS/s 5 V Analog-to-Digital Converter”, IEEE Journal of Solid-State Circuits, vol. 23, pp.
1316-1323, Dec. 1988.

References: Sigma Delta A/D Converters


K. C. H. Chao, S. Nadeem, W. L. Lee, C. G. Sodini, “A Higher Order Topology for Interpolative Modulators for Oversampling A/D
Converters”, IEEE Transactions of Circuits and Systems, vol. 37, pp. 309-318, Mar. 1990.
V. F. Diaz, “A Design Environment for Switched Capacitor Noise Shaping A/D Converters”, Ph. D. Dissertation, University of Pavia,
Department of Electronics, 1991.
J. C. Candy, “A Use of Double Integration in Sigma-Delta Modulation”, IEEE Transactions on Communications, vol. 35, pp. 481-489,
May 1987.
F. Francesconi, G. Caiulo, V. Liberali, F. Maloberti, “A 30-mW 10.7-MHz Pseudo-N-Path Sigma-Delta Band-Pass Modulator”,
Symposium on VLSI Circuits Digest of Technical Papers, pp. 60-61, June, 1996.
F. Francesconi, V. Liberali, F. Maloberti, “A 10.7-MHz N-Path Fourth-Order Bandpass Sigma-Delta Modulator”, Proceedings of
European Solid-State Circuit Conference, pp. 216-219, Sept. 1996.

A. Baschirotto, et al. "A/D and D/A Converters"


S. R. Norsworthy, R. Schreier, G. C. Temes, “Delta-Sigma Data Converters: Theory, Design, and Simulation”, IEEE Press, New York,
USA, 1997.
M. J. Hawksford, “N-th Order Recursive Sigma-ADC Machinery at the Analogue-Digital Gateway”, Audio Engineering Society
Convention, May 1985.
Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, T. Yoshitome, “A 16-Bit Oversampling A-to-D Conversion Technology
Using Triple Integration Noise Shaping”, IEEE Journal of Solid-State Circuits, vol. 22, pp. 921-929, Dec. 1987.
S. H. Ardalan, J. J. Paulos, “An Analysis of Nonlinear Behavior in Delta-Sigma Modulators”, IEEE Transactionson Circuits and
Systems, vol. 34, pp. 593-603, June 1987.
L. E. Larsen, T. Cataltepe, G. C. Temes, “Multi-Bit Oversampled SD A/D Converter with Digital Error Correction”, Electronic Letters,
vol. 24, pp. 1051-1052, Aug. 1988.
V. F. Dias, G. Palmisano, P. O’Leary, F. Maloberti, “Fundamental Limitations of Switched-Capacitor Sigma-Delta Modulators”, IEE
Proceedings-G, vol. 139, Feb. 1992.
D. A. Kerth, D. B. Kasha, T. G. Mellissinos, D. S. Piasecki, E. J. Swanson, “A 120 dB Linear Switched-Capacitor Delta-Sigma
Modulator”, ISSCC Digest of Technical Papers, pp. 196-197, Feb. 1994.
R. W. Adams, T. W. Kwan, “Data-Directed Scrambler for Multi-bit Noise Shaping D/A Converters”, U.S. patent no. 5.404.142, Apr.
1995.
R. T. Baird, T. S. Fiez, “Improved Delta-Sigma DAC Linearity Using Data-Weighted Averaging”, Proceedings of International
Symposium on Circuits and Systems, pp. 13-16, May 1995.
J. C. Candy, G. C. Themes, “Oversampling Methods for A/D and D/A Conversion”, Oversampling Delta-Sigma Data Converters, J. C.
Candy and G. C. Themes, Ed., IEEE Press, New York, USA, 1992.
F. Chen, B. H. Leung, “A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging”, IEEE Journal of Solid-
State Circuits, vol 30, pp. 430-460, Apr. 1995.
V. F. Dias, V. Liberali, F. Maloberti, “TOSCA: a User-Friendly Behavioural Simulator for Oversampling A/D converters, Prodeedings of
International Symposium on Circuits and Systems, pp. 2677-2680, May 1991.

A. Baschirotto, et al. "A/D and D/A Converters"


References: D/A Converters
A.Cremonesi, F. Maloberti, G. Polito, “A 100 MHz CMOS DAC for Video-Graphic Systems”, IEEE Journal of Solid-State Circuits, vol.
24, pp. 635-639, June 1989.
A.Cremonesi, F. Maloberti, G. Torelli, C. Vacchi, ”An 8-bit Two-Step Flash A/D Converter for Video Applications”, Proceedings of
Custom Integrated Circuit Conference, pp. 6.3.1-6.3.4, May 1989.
S. Brigati, G. Caiulo, F. Maloberti, G. Torelli, “Active Compensation of Parasitic Capacitances for Very High Frequency CMOS DACs”,
Proceedings of International Symposium on Circuits and Systems, pp. 1208-1211, May 1993.
D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, C. A. A. Bastiaansen, “A Self Calibration Technique for Monolithic High
Resolution D/A Converters”, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1571-1522, Dec. 1989.
A. R. Hamade, “A Single-Chip All-MOS 8 Bit A/D Converter”, IEEE Journal of Solid-State Circuits, vol.13, pp. 785-791, Dec. 1978.
J. W. Yang, K. W Martin, “High resolution Low-Power CMOS D/A Converter”, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1458-
1461, Oct. 1989.
H. J. Schouwenaars, D. W. J. Groeneveld, H. A. H. Termeer, “Low Power Stereo 16 Bit CMOS D/A Converter for Digital Audio”, IEEE
Journal of Solid-State Circuits, vol. 23, pp. 1290-1297, Dec. 1988.
P.H. Saul, J. S. Urquhart, “ Techniques and Technology for High-Speed D/A Conversion”, IEEE Journal of Solid-State Circuits, vol.
19, pp. 628-68, Dec. 1984.
A. Baschirotto, G. Brasca, F. Montecchi, F. Stefani, “Low Power BiCMOS SC Filter for Audio Codec Applications”, IEEE Journal of
Solid-State Circuit, vol. 32, pp. 1127-1131, July 1997.

References: Other Techniques


K. C. Hsieh, P. R. Gray, D. Senderowicz, “A Low Noise Chopper-Stabilized Differential Switched-Capacitor Filtering Fechnique”, IEEE
Journal of Solid-State Circuits, vol. 16, pp. 708-715, Dec. 1981.

A. Baschirotto, et al. "A/D and D/A Converters"


P. W. Li, M. J. Chin, P. R. Gray, R. Castello, “A Ratio-Independent Algorithmic Analog-to Digital Conversion Technique”, IEEE Journal
of Solid-State Circuits, vol.19, pp. 828-836, Dec. 1984.
K. W. Martin, L. Ozcolak, Y. S. Lee, G. C. Themes, “A Differential Switched Capacitor Amplifier”, IEEE Journal of Solid-State Circuits,
vol. 22 , pp. 104-106, Feb. 1987.

A. Baschirotto, et al. "A/D and D/A Converters"

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