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Andrea Baschirotto
University of Lecce
73100 Lecce - Italy
E-mail: andrea.baschirotto@unile.it
F.S.
ANALOG SIGNAL
7/8
6/8
5/8
4/8
3/8
2/8
1/8
DIGITAL CODE
ANALOG SIGNAL
7/8
6/8
5/8
4/8
3/8
2/8
1/8
DIGITAL CODE
• For N bits of resolution 2N different digital codes are allowed. Each code will not
represent a value but an interval of the input voltage.
Anti Output
Analog
digital
input Aliasing A/D word
signal Filter
Fs
• The Anti-Aliasing Filter limits the filter band to Fs/2 in order to avoid aliasing of
different components.
• Aliasing of two sampled waveforms:
2
• They give the same output samples
and cannot be distinguished 1
0.4
= Input signal – Quantized signal
Analog value [V]
0.2
-0.2
-0.4 0.5
-0.6 0.4
0.3
-0.8
1.5 -0.2
-0.3
1 -0.4
-0.5
Quantized value [V]
-0.5
-1
-1.5
0 0.5 1 1.5 2
Time
∆/2 2
∆/2 2 1 ⌠ 2
∆
e rms = ∆ e de = 12
⌡
−∆/2 ∆/2
–∆
Vin/FS 1
3/4
in
CODE A/D
000
001
010
011
111
100
101
110
Quantization error
quantization
∆V noise
CODE
000
001
010
011
111
100
101
110
∆V
Erms =
12
√
Power
of noise
spectral ∆2 Fs • The noise spectral density
density 12 2 is given by:
Quantization
Fs/2 Fs
Eq(f) = erms
√
Fs
noise
N +FSC
Let' consider an N bit ADC with 2 quantization levels
2·FSC
∆= N
2 –1
–FSC
2·FSC2 2·FSC2
2 2N–1 N
2 ∆ 2
nrms = 12 = 12 ≈ 12
2
2 FSC
s rms = 2
FSC
2
s 2
rms 2 3 2·N
SNR [dB] = 10·log10 2 = 10·log10 2·FSC2 = 10·log 10 2 2
nrms N
2
12
SNR [dB] = 1.76 + N · 6.02
A. Baschirotto, et al. "A/D and D/A Converters"
Static conversion errors
Gain error
Analog Analog
actual actual
response ideal response
• Offset error ideal
response response
offset
• Gain error
Code Code
• Integral linearity
• Non monotonicity
ideal
Cm+1 real
Cm
Output
Code
DNL=0.5LSB
Sin
Input Signal
[LSB]
0 255
output code
• monotonic: -1 LSB < DNL < +1 LSB
• DNL gives extra noise on top of quantization noise
code out
0 full scale
Sin
[LSB]
0 255
output code
• INL gives extra distortion & noise on top of quatization noise
10n
input signal
1n
100kS/s
100p
Sin +dSin Jitter 1MS/s
Sin (sec) 10p
10MS/s
1p
CMOS
t t+dt t [sec] 100MS/s
100f
10f
S in = A sin(ωt ) 2 −n 8 9 10 11 12 13 14 15 16
dSin < 1LSB } dt <
πf in Number of bits
0 0.5fs 0 0.5fs
• All noise and distortion sources have to be taken into account for DR evaluation
Quantization
Thermal
Jitter
INL & DNL
DC specs
INL,DNL
What you get
Highest frequency
0
BW
22 Sigma-Delta
20
Resolution(bit)
18
16 Pipeline/
14 subrange
12
10
Folding
8
6
4 Flash AD
22 super
audio 1 kW
20 1mW 1W
Resolution(bit)
• Oversampled converters
V
IN
INTEGRAT COMPAR.
V
REF
N-BIT
CONTROL
COUNTER
b0 b1 b2 b3 bN
Φsampl
V in Comp
S&H +
SAR PHASE
- Φconv CONTROL Φck
V ref
N-bits VR/2
DAC OUT
implementation
2N-1C 2N-2C 2C C C
-
+
bN-1 bN-1 bN-2 bN-2 b1 b1 b0 b0
Φ1
V in
Φ1
V ref
• During the first clock
period the circuit SAR
samples the input
• The total charge stored on the capacitive array is Qtot = 2N·C · (Vin – Vos)
• Sampling period => The operational amplifier is buffer connected
• Conversion cycle => The operational amplifier is used in open loop as a comparator
• Drawback: Overdrive recovery of the comparator
• Performance : Medium speed (10-20 kHz) & Medium accuracy (≅ 10 bit)
Φ0+ Φ 1
S1 Φ0
V
REF C1
C
-
S2 A1 -
-V
REF + A3 SAR
+
V
in Φ0 2C C
Φ0+ Φ 2
Φ0
C
Φ1
-
A2 Φ2
+
• The input signal is injected at the beginning of the conversion cycle. Each full clock
period +Vref or -Vref is added and the reminder is multiplied by two
• The active serial DAC with division by two generates the voltage sequence required
by the successive approximation algorithm without the need of a SAR
CODE LOGIC
b2
b3
V
R2 b4
V ref V in
Rd /2
-
(2N-1)
Rd +
THERMOMETRIC to BINARY
(2N-2)
Rd +
bN-1
• The reference voltages are generated by a (2N-3)
- bN-2
b2
b1
- b0
(2)
Rd +
-
(1)
Rd/2 +
C az
Cp
• The autozero cycle of the comparators gives rise to charge pumping in the resistor
string network
• Key limitation: offset, components matching, loading
• Performance : Very High speed (>1GHz) & low accuracy (≤ 8 bit)
ΦS
Φ1 Φ2 Φ3
ΦH
V in m-bits + n-bits
S&H ADC DAC - Σ K ADC Φ1
Φ2
V ref V ref (K / 2m)V
MSB’s ref LSB’s
Φ3
• If the subtraction and the amplification by the factor K do not require additional clock
cycles, the conversion time is two clock cycles
• The two-step flash architecture requires two full flash A/D converters, a D/A
converter and a subtracting amplifier
• The number of comparators required is significantly reduced with respect to the full
flash architecture => Only (2m + 2n – 2) instead of 2n + m
A. Baschirotto, et al. "A/D and D/A Converters"
Two-step Subranging Flash A/D Converters
Limitations
ΦS
Φ1 Φ2 Φ3
ΦH
V in m-bits + n-bits
S&H ADC DAC - Σ K ADC Φ1
Φ2
V ref V ref (K / 2m)V
MSB’s ref LSB’s
Φ3
• The subtracting amplifier can be the real limit to speed, since subtraction and
amplification must settle within half of a quantization step, thus requiring time
• Successive samples are weakly correlated => The subtracting amplifier must ensure
large output swing within the subtracting period
• Typically an additional clock cycle for the subtraction and amplification operation is
required
• The mismatch between the coarse and fine reference voltages or an error in the
multiplying factor degrade the linearity
Φ2 Φ1
S&H A/D
Φ2
DEMUX
IN
Φ3 Φ3
S&H A/D
OUT
ΦN
ΦN 1 2 3 4 N
S&H A/D
1 2 K-1 K
V in(nT)
ADC res ADC res ADC res ADC
+ + + +
RES RES RES RES
j j j j
bkj-1,…,b(k-1)j+1, b(k-1)j b(k-1)j-1,…,b(k-2)j+1, b(k-2)j b2j-1,…,bj+1, bj bj-1,…,b1, b0
Sample n Sample (n-1) Sample (n-K-2) Sample (n-K-1)
j j j j
bkj-1,…,b(k-1)j+1, b(k-1)j b(k-1)j-1,…,b(k-2)j+1, b(k-2)j b2j-1,…,bj+1, bj bj-1,…,b1, b0
Sample n Sample (n-1) Sample (n-K-2) Sample (n-K-1)
• The signal processing in the analog path must preserve the information content of the
residual bits
• The circuit complexity and the power consumption in a pipeline stage are significantly
lower than in a complete data converter
• The pipeline architecture achieves a better trade-off between speed, area and power
consumption with respect to the interleaved architecture
• The total number of stages K required to obtain a given resolution decreases as the
number of bits of each stage increases, but the analog processing required for
each stage also increases at the expense of speed and the power consumption
=> Trade-off
A. Baschirotto, et al. "A/D and D/A Converters"
Pipeline A/D Converter
• Typically few bits per
+
stage are used => Vin
S&H
j-bit j-bit
Σ 2j
-
CMOS switched ADC DAC
capacitor
implementation of a
one bit per stage
pipeline A/D Vin -Vref /2 +
S&H + Σ 2
converter -
+Vref /2 -
Vref /2
Φo
• During the even clock phase Φe the
Φe Φe
circuit samples the input voltage on C1
two equal capacitors C1 and C2 Vin Φe C2
and the comparator performs the -
auto-zero by storing the offset on Φe COMP Φe
Φo
+
capacitor Cos Cos
-
• During the odd clock phase Fo Φo +
capacitor C1 is connected in
feedback ‹ C1 receives the charge Vref /2 b Vref 0
i
delivered by C2
• Digital correction techniques allows to recover large threshold error
A. Baschirotto, et al. "A/D and D/A Converters"
Digital correction techniques
• Basic idea: to perform a coding redundant and to use the redundant bits for a digital
correction
• The correction can be made using informations stored in a memory (RAM, EPROM)
or automatically with a suitable algorithm
• EPROM corrected
• Self calibration
• Self corrected
VR VR
VR/2 VR/2
IN
D!A CLOCK
REG.
SAR &
LOGIC
EPROM
FULL OUTPUT
ADDER
MAIN DAC
SAR
REG.
ADDER
DATA
REG.
LOGIC
• 16 bits achievable
VREF
VREF
2
1.2
1 2 4 8 1 2 4 8
• Self calibration cycle: Vref is applied to the input. If the gain is smaller than 2 the
conversion result will be less than the full scale. If the gain is larger the converter will
over-range
• Calibration cycle easier, less digital control circuity and less memory
• 13 bits achievable
in + residue
S/H
-
ADC DAC
bits
+ 1/2 LSB
digital
- 1/2 LSB
code
residue
+ 1/2 LSB
analog input
- 1/2 LSB
1
• With an error within ± 2 LSB the residue voltage can range from ± 1 LSB
1
• If the input is < - 2 LSB, 1 bit must be subtracted to the code of the previous stage
CORRECTION LOGIC
9BIT
• The circuit uses flash A/D converter with differential input and differential reference
comparators
Φ1 C Φ1
Φ2 4C Φ2
- Φ1
Φ1 +VREF Φ1
Φ2
+ S/H+ -
Φ2
4C Φ1
Φ2 -VREF +
Φ1 Φ2
C Φ1 S/H- Φ1
I1 = I + ∆ I
I2 = I - ∆ I I
B
I I I I I I
• Conversion time
• Latency time
• Settling time
• Hysteresis
• Glitches
Ideal response
Glitch
• Resistor-based converters
• Capacitor-based converters
• Serial converters
• The reference voltage or current generator can be internal or external to the chip
depending on the stability and accuracy requirement
I TOT
-
LSB
MSB +
I 2I 4I 8I N-1
2 I
Advantages:
• Small area for less than 8 bit
• Very high speed of operation (tens of MHz's)
A. Baschirotto, et al. "A/D and D/A Converters"
Current Steering D/A Converters
Problems • On off switching times of current sources (speed, glitches)
• Current source matching (linearity)
Solutions • Use a differential switch, to switch the current sources toward
the output or toward a fictitious load
To the fictitious To the load
load
M1 M2
VDD
VBias,1
VDD
VBias,2
W δI
2 δk'
2 δW
2 δL
2 δV Th 2
2
I= k' L (V GS - VTh) = + W + +4
I k' L V GS - V Th
• VGS is assumed constant. It is true if the drop voltage along the ground connections
is negligible. (Remember: metal lines ≅ 40 µΩ/v)
Solutions:
• Use of a large number of transistors in parallel with W ≅ L; the error due to L and W
are uncorrelated and are summed quadratically; with N transistors in parallel the
error is reduced by a factor between N/2 and
√ √N
• Use of transistors closed to the mirroring element
• Use of large overdrive voltage
Drain
Source
2
1 3 Drain
4 Gate
2R
• The current in the branches must be matched better than 1/2N 2R
V
B
R
S1 S2 S3 S4 SN
-
V
+ 0
• The non linearities of the transistors are cancelled at the first order
• Small silicon area
• Non inherently monotonic
• Only for low accuracy (< 6 bit)
• Noise and offset modulation
ΦR
+
C/32 C/32 C/16 C/8 C/4 C/2 C – VO
S1 S2 S3 S4 S5 S6
Vref
CATT=0.516 pF
+
0.5pF 0.5pF 1pF 2pF 4pF 8pF 0.5pF 1pF 2pF 4pF 8pF – V
OUT
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
V
ref
C1=16 pF
Vref
• The reference voltage is divided by a
string of equal resistors R b1
b2
• A particular voltage tap is selected with
R b1
a tree of switches
b3
• The input impedance of the buffer is R b1
very high
R b1
• Features b2
R VO
Intrinsically monotonic b1
b2
Sensitive to the buffer offset R b1
R b1
b2
SWITCH TREE
• Tree of switches to select one of the 8
voltage taps
• Features
Intrinsically monotonic
Corner resistors difficult to
implement
Compact layout
b0 b1 b2 b3
Buffer
Φ1
C/4 C/2 C +
C/2N–1
Vref
R0
K = 2(n–1)
CONTROL SWITCHES
L = 2(m–1) Φ1
R1
-
RL
MSB's
Φ1
Φ2
2C Φ1
+
C/2N–1 C/4 C/2 C
Vref
Φ0 + Φ1
S1 C
V C1
ref
S2 -
–V
A1
+
ref Φ0
2C C Φ2
Φ0 + Φ2
Φ2
C
-
A2
+
C2
-
• Ramp converter
• Capacitor mismatch -
A2
+
C +
Vout = 2 · C1 Vin
2
Exchange capacitors C1
C C C2
Vout = 2 C1 V in C2 = 2Vin -
2 1
+
Problems: Offset
Clock feedthrough
Φ0 +Φ A
C3 Φ0
ΦB
Φ0 Φ1
V Φ0 Φ1 C2
REF
- Φ2
C1 +
Φ0+ Φ 2 Φ A= Φ 1 * b
Φ B= Φ 2 * b
• Offset insensitive
• Stray compensated
• Operates starting from the MSB
• Generates "useful" intermediate voltage levels
b0
N-BIT b1
COUNTER COMPARAT.
bN
CLOCK
• Inherently monotonic
COMPAR
T
• The spectrum is pushed at higher
frequency:
• ADC's are typically used as interface in mixed signal systems where the largest part
(area) is digital; the larger digital section therefore drives the use of digital
technology, in the scaled-down version to reduce chip size
• Scaled-down digital technologies can operate at very high speed but with poor
analog features (poor matching/accuracy)
Signal Signal
Filter
• reduces the in-band quantization noise (the power of noise is halved by doubling Fs)
• increases the resolution by 3dB for each sampling frequency doubling
• reduces the required accuracy of anti-aliasing frequency
• this process is limited by the maximum possible Fs
F
M = log2 2·Fs DR = – 3.41 dB + 3·M dB
b
Digital filter
1.5
Signal band
Standard quantization noise
1
0
0 0.1 0.2 0.3 0.4 0.5
f/Fs
Advantages
• Σ∆ systems can manage high accuracy data conversion with low accuracy circuit
solutions
• Small amount of analog parts (this allows to use a Σ∆ modulator as interface in
digital systems)
• Σ∆ systems can be implemented in standard CMOS technology
Draw-backs
• Σ∆ systems exchange resolution with speed thus they are limited to small signal
bandwidth
• High-speed analog and digital systems are needed (power and performance
limitation)
• No relation exists between input sample and output word
• Latency time
Data Conversion
• Isolated input sampler (spectra unimportant)
• sample errors specified
• one-to-one correspondence between input sample and output word
example: digital voltmeter
Signal conversion
• attention to waveform and spectrum
• occasional large sample error may be permissible
• RMS SNR specified
example: digital audio
Input signal
Conventional
ADC
latency
Sigma-delta
ADC
latency
Bitstream
signal Filter Filter
DAC
• Oversampling Ratio
• Order of the loop filter To increase the DR (No. bit)
• Number of bit of the quantizer
Bitstream
signal Filter Filter
DAC
Bitstream
signal Filter Filter
DAC
DR = k + (3+6·L)·M dB + 6·(N–1)
F
OSR Oversampling ratio 2·Fs
b
M = log 2 (OSR)
L Σ∆ modulator order
A. Baschirotto, et al. "A/D and D/A Converters"
Σ ∆ modulator performance summary (2002)
N DOR Power Quantizer
Process / Supply Filtering
bits (MS/s) (mW) B, bits
3rd-order 4b
[Geerts00] 15.8 2.5 0.65 m-DP@5V 295
Single-Loop DWA
3th-order 3b@last stage
[Brandt91] 12 2.1 1 m-DP@5V 41
2-1 Cascade No calibration
4th-order
[Marques98] 14.8 2.0 1 m-DP@5V 230 1b
2-1-1 Cascade
6th-order
[Feldman98] 13 1.4 0.7 m-DP@3.3V 81 3-level@last stage
2-2-2 Cascade
4th-order 4b@last stage
[Medeiro99] 13 2.2 0.7 m-SP@5V 55
2-1-1 Cascade No calibration
4th-order
[Geerts99] 15 2.2 0.5 m-DP@3.3V 200 1b
2-1-1 Cascade
4th-order 4b@all stages
[Fujimori00] 15 2.5 0.5 m-DP@5V 105
2-1-1 Cascade Bi-directional DWA
4th-order 5b@last stage
[Morizio00a] 13 2.2 0.35 m-DP@3.3V 99
2-2 Cascade dual quantization
4th-order 4b@all stages
[Morizio00b] 14 2.2 0.35 m-DP@3.3V 150
2-2-2 Cascade Bi-directional DWA
[Brooks97] 14.5 2.5 0.6 m DP@5V 550 (A+D) pipeline-overs
[Paul99] 12 18.0 1.2 m-DP@5V 324 pipeline-overs
[Paul99] 10.7 30.0 0.6 m-DP@5V 230 pipeline-overs
X=[0]; U=[0];
Y X U fs=1.024e6;
fin=fs/2^8; ain=0.25;
npoint=2^10; start=2^5;
analog Delay digital
signal signal
for i=2:npoint+start;
Y(i)=ain*sin(2*pi*i*fin/fs);
Delay DAC X(i)=(X(i-1)+(Y(i)-U(i-1)));
if X(i)>0, U(i)=1; else U(i)=-1; end;
z -1 end;
Uout=U(start+1:start+npoint);
fftU=20*log10(abs(fft(Uout)/length(Uout)));
plot(fftU)
fr=0:length(y1)-1;
fr=fr/max(fr);
axis([0 0.2 -100 10])
xlabel('f/Fs'); ylabel('Amplitude [dB]');
plot(fr,fftU)
1.5
0.5
Amplitude
0
-0.5
-1
-1.5
-2
0 10 20 30 40 50 60
Time
1 1
0.5 0.5
Amplitude
Amplitude
0 0
-0.5 -0.5
-1 -1
0 20 40 60 80 0 20 40 60 80 100 120
Time Time
0.2
Y
-0.2
-0.4
0 50 100 150 200 250 300
0
X
-1
-2
0 50 100 150 200 250 300
Time
-40
Amplitude [dB]
-50
-60
-70
-80
-90
0 0.2 0.4 0.6 0.8 1
Normalized frequency f/Fs
-40
-60
-80
-100
0 0.05 0.1 0.15 0.2
Normalized frequency f/Fs
90
80
60
50
40
30
20
3 4 5 6 7 8 9 10
log2(OSR)
General features
3 3/2
• Dynamic range = OSR
2·π
√
DR = – 3.41 dB + 9.03·M dB
• Low modulator complexity
• Low performance sensitivity to component non-idealities and mismatch
• Inherently stable (without excessive delay in the loop or integrator imperfections)
• Large peak in the SNR for DC or slowly varying signals, and the noise includes
single-frequency tones
• Dither is usually necessary (if the signal is not very busy, i.e. rapidly varying and
nearly random)
Y z -1 X z -1 W U
k1 k2
1 - z -1 1 - z -1
DR = – 11.12 dB + 15.05·M dB
140
120
80
2nd order
60
40 1st order
20
3 4 5 6 7 8 9 10
log2(OSR)
-20
-40
Amplitude [dB]
-60
• 1st order vs. 2nd order modulator in-
-80
band output spectrum
-100
0
-120
0 0.2 0.4 0.6 0.8 1 -20
f/Fs
-40
Amplitude [dB]
• 1st order vs. 2nd order modulator -60
-80
0 -100
-20 -120
0 0.05 0.1 0.15 0.2
f/Fs
-40
Amplitude [dB]
-60
-80
-100
-120
0 0.2 0.4 0.6 0.8 1
f/Fs
100
80
60
SNR [dB]
40
20
-20
-100 -80 -60 -40 -20 0
Input amplitude [dB]
7
• For OSR = 2 = 128 => DR = – 11.12 dB + 15.05·7 dB = 94.23dB
• High-accuracy DAC are not easely realized (without trimming, etc...) in term of:
accurate frequency response
accurate linearity
Example: 16bit audio DAC: The input signal is a 16bit word at 44.1kHz. The DAC
must cancel the image, very close to the signal
signal bandwidth=20kHz
DAC analog filter with multi-bit input
word lenghth=16bit
Fs=44.1kHz
• A digital interpolator is then added which increases the sampling frequency and
separate signal from image
signal bandwidth=20kHz
DAC analog filter with multi-bit input
word lenghth=16bit
Fs = k·44.1kHz
• The output word is now a 16bit word with high-frequency rate which should require
high-accuracy analog components.
signal bandwidth=20kHz
• The 16bit HF word is then DAC analog filter with 1bit input
translated into a 1bit word 16bit-to-1bit quantization noise
with a digital Σ∆
modulator, which pass to word lenghth=1bit
a 1bit code with added
quantization noise
Fs = k·44.1kHz
signal bandwidth=20kHz
• Finally the bitstream is filtered DAC analog filter with 1bit input
with an analog filter which
cancel the high-frequency
noise
Single-bit
+ Linear DAC
+ Simple
– Tones (single bit from single loop)
– Stability (order higher than 2th)
Multibit
+ Stability (for order higher than 2th)
+ Low step (output on more levels)
– Linear DAC
– Linearization algorithm
A. Baschirotto, et al. "A/D and D/A Converters"
DAC Σ ∆ Converter
Analog smoothing filter
• Low distortion: To avoid in-band folding of tones (present for low signal level)
• Low noise: To maintain the dynamic range featured by the previous oversampler
• Sampled-data structures for the first stage reduces coupling problem between the
input bitstream (digital signal) and the analog section
• The SC technique gives an accurate frequency response and allows to reduce the
effects of the bit-stream non-idealities (like clock jitter and non-accurate edges)
1.05
• Accurate SC transfer function can be
compensated in the FIR frequency
response FIR Preemphasis
SC frequency response
0.95
0 5 10 15 20
Frequency [kHz]
Vin Vin
Vout
Vout
vn1
vn1 vn2
vn2
vn3
vn3
Vin
Vout
vn1
vn2
vn3