EX6 DIGITAL ELECTRONICS G________

After completing the task and studying Units 2.5, 2.8, and 2.9, students will be able to: (check all that
apply):

† Design synchronous sequential systems or finite state machines (FSM) using the canonical method consisting
in the following steps:
a) FSM specifications using functions tables and state and timing diagrams
b) Particularization of the general FSM structure for the given problem
c) State coding in Gray, binary, one-shot, etc.
d) Design the CS2 for generating the output functions
e) Drawing the state memory using one of the following flip-flops: D-type, JF-FF, T-FF flip-flop
f) Design the CS1 to determine the future state using transition tables and the design-table for the type
of FF selected
g) Simulate and verify the design applying a suitable testbench

† Deduce how to structure CS1 using multiplexers for implementing distinct state diagrams (count enable,
parallel load, etc.)
† Expand counters using TC and CE signals to produce for example a real time clock in HH:MM:SS
† Produce a written solution for the exercise using the instructions from:
http://epsc.upc.edu/projectes/ed/unitats/unitat_1_1/Criteris_Correccio_Exercici.pdf
† Work cooperatively in a team of 3 members using the method described in:
http://epsc.upc.edu/projectes/ed/problemes/metode_resolucio_cooperativa_recomanat.pdf

Write down the most significant doubts or questions you have had while or after completing the task:
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STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX3 as a member of the group,
(2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document,
and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual
member in completing this document.

Today’s date: __________________

Active members Roles: (reporter, simulator, etc.)
(1) ___________________________ _______________
(2) ___________________________ _______________
(3) ___________________________ _______________

Acknowledgement of individual(s) who assisted this group in completing this document:

(1) _______________________
(2) _______________________

Group (count all hours devoted to the study including class sessions)
Individual Student 1
Study time (in hours)
Student 2
Student 3

1
 On the systematic (canonical) design of synchronous FSM

For example, the counters HH:MM:SS for the real time clock

In Fig. 1 we have the entity for the real time clock for the application project, which gets the inputs from de
keyboard encoder subsystem and produces the outputs for the multiplexed 7-segment display system.
CLOCK_SYSTEM

COD[3..0] COD[3..0] Q2 X2
Q1 X1
GSD GSD Q0 X0

FC[1..0] FC[1..0] HT[3..0] HT[3..0]

GSF GSF TT[3..0] TT[3..0]
TH[3..0] TH[3..0]
ENTER ENTER H[3..0] H[3..0]
T[3..0] T[3..0]
HM HM U[3..0] U[3..0]

REAL_TIME_CLOCK

Fig. 1 The core of the real time clock to be designed as an application project

1. Designing the basic module‐6 binary counter

a) Implement (steps a, b, c, d, e, and f of the canonical method) the basic module-6 counter to activate
the multiplexed display subsystem as a canonical FSM using JK-FF which has the entity represented
in Fig. 2.
MUX_SWEEPER

QX[2..0] QX[2..0]

clk CLK

3-BIT BINARY COUNTER

Fig. 2 Block for the binary module-6 counter to sweep the 7-segment displays

b) Implement a 600 Hz clock based on the 555 chip to autonomously run the multiplexed display
system

c) Verify it in Proteus –VSM (step g of the canonical method) the and add the module to the main
application project schematics

2. Designing the basic building block: a 1‐digit BCD universal counter

a) Specifications

Fig. 3 represents the basic block for a cascadable 1-digit BCD universal counter. Sketch all the state
diagrams for the counter.

2
 LD LD
IN[3..0] IN[3..0]

CE CE
Q[3..0] Q[3..0]
UD_L UD_L

CD CD
clk CLK TC10
1-DIGIT BCD COUNTER

Fig. 3 Inputs and outputs for the FSM

- Q[3..0]: BCD outputs

- IN[3..0]: parallel inputs
- LD: parallel load signal
- CE: count enable signal
- UD_L: up (active high) or down (active low) signal
- CD: asynchronous reset
- CLK: clock input
- TC10: terminal count
• Signal LD has precedence over CE, and CE has precedence over UD_L.
• TC10 is high when counting up for Q[3..0] = ‘1001’, and is high when counting down
for Q[3..0] = ‘0000’

LD CE UD_L Synchronous function mode

1 X X Parallel load (parallel-parallel register)
0 0 X Inhibit (do nothing)
0 1 0 BCD down counter
0 1 1 BCD up counter

Fig. 4 Precedence table to determine the synchronous operation modes of the FSM to be designed

b) Particularise the general architecture of a FSM for the given problem and name all inputs, outputs
and internal variables if D-type FF are used as state registers.

c) Code each state in BCD

d) Design the CS2 for generating the output functions constructing the truth table and using any method
from Chapter 1

e) Draw the state memory using D-type FF

f) On the design of the CS1 to determine the future state:

1. Due to its complexity, use multiplexers to organize and structure the combinational block
2. Using a transition table and the design-table of the D-type FF, complete the truth table for
each of the circuits: CS1UP, CS1DW, CSINH and CS1LD.
3. Produce each of the combinational blocks using whichever of the Chapter 1 methods
4. Produce the multiplexers chaining elementary MUX2

3
 g) Simulate and verify the design applying a suitable testbench to demonstrate or “cover” the FSM
operation

3. Designing the MM:SS blocks

Propose an architecture for the entity in Fig. 5 which has to be based on cascading the 1-digit BCD modules
designed previously plus extra combinational blocs. In the application project must be two module-60
counters for producing the seconds (SS) and minutes (MM).
MINUTES
LDT
data_t[3..0] tens[3..0]

LDU
data_u[3..0] units[3..0]

CE
UD_L

CD
CLK TC60
MODULE-60 COUNTER

Fig. 5 Entity for the SS or the MM modules to be designed

4. And, how about the HH module?

The hours HH module has to work in AM-PM or 24 hours depending on the position of a switch HM (hour
mode)
- HM = ‘0’ Æ 24 hours mode:
00, 01, 02, ……, 22, 23, 00, 01, …..

- HM = ‘1’ Æ AM-PM mode plus LED outputs to illuminate labels:

12, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
AM =1 PM = 1
Draw in Fig. 6 the entity to be designed for the HH module.
HOURS
LDT
data_t[3..0] tens[3..0]

LDU
data_u[3..0] units[3..0]

CE
PM_LED
UD_L
AM_LED
HM

CD TC24
CLK
MODULE-24 COUNTER

Fig. 6 Entity for the HH module

Design the HH module using the basic 1-digit cascadable BCD counter and proposing an architecture
similar to the one represented in Fig. 5.

4
 DIGITAL ELECTRONICS G________

Working plan1 for solving the exercise EX____

Explain succinctly how the cooperative group has organize the realization of the exercise: i.e., which has
been your working plan; in which way has you divided the task fairly so that more or less all of you are
doing a similar amount of work; how have you learned each other’s materials; what has been worked out in
class time (sessions A and B) and what has been resolved in sessions C; and so on... white down also your
impressions or opinions about how your group work is going2 ...

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Active members’ signatures

1
This document, filled before delivering the exercise, will be included in the group learning portfolio
2
Check similar documents in http://epsc.upc.edu/projectes/ed/unitats/ED_05-06_Q1_Autoavaluacio_Grup_Base.pdf, and
http://epsc.upc.edu/projectes/ed/unitats/que_va_malament_al_grup.pdf