Points Addressed in this Lecture

• Exclusive-OR & Exclusive NOR gates

Lecture 6: More Gates and their Applications
Professor Peter Cheung
Department of EEE, Imperial College London
• Usefulness of Logic Gates (as functions)
• Parity Circuits using XOR gates
• Multiplexer and Demultiplexer circuits
• Alternative logic symbols – IEEE Standard

(Floyd 3.6, 6.8-6.10)

(Tocci 3.13-3.15, 4.6-4.8, 9.6-9.8)

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Exclusive-OR Exclusive-XNOR
Exclusive-NOR (XNOR) produces a HIGH output
Exclusive-OR (XOR) produces a HIGH output whenever whenever the two inputs are at the same level.
the two inputs are at opposite levels.

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 XNOR gate may be used to simplify circuit implementation.

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Parity Generator and Checker Enable/Disable Circuits

AND gate function act as enable/disable circuits:-

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 Enable/Disable Circuits cont. Merging & Inversion Circuits
Design a logic circuit that will allow a signal to pass to the output only
when control inputs B and C are both HIGH; otherwise, the output will OR gate performs signal merging function:-
stay LOW.
A

X
Design a logic circuit that will allow a signal to pass to the output only
when one, but not both, of the control inputs are HIGH; otherwise, the XOR gate performs selectable inversion function:-
output will stay HIGH.

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Multiplexers (Data Selectors)

Multiplexers cont.

Two-input multiplexer.

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 Multiplexers cont.

Four-input multiplexer.

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Multiplexers cont. Mux used to Implement Logic Function

two 74HC151s combined to form
a 16-input multiplexer.
f = ABC + ABC + ABC
f = ∑ ( 3,4 ,7 )

0 D0
A B C f
0 D1
0 0 0 0 0 D2
0 0 1 0 1 D3
Y f
0 1 0 0 1 D4
0 D5
0 1 1 1
0 D6
1 0 0 1 1 D7
1 0 1 0
A
1 1 0 0
1 1 1 1
Variables { B
C

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 Demultiplexers (Data Distributors)
Another example
A DEMUX takes a single input and distributes it over
several outputs.

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Demultiplexers (Data Distributors) cont.

Demultiplexers

• 2-line-to 4-line demux

1-line-to-8-line demux
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 Demultiplexers (Data Distributors) cont.

The 74ALS138 demultiplexer with E1 used as the data input. (b)

Typical waveforms for a select code of A2 A 1 A 0 = 000 show that O0
is identical to the data input I on E1.

A clock demultiplexer transmits the clock signal to a destination

determined by the select code inputs.

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Alternative Symbols for Gates

– identical elements can be grouped as an array
• The symbols presented so far are International Standards of with common control signals
ANSI and IEEE
– Here is a 4 identical AND gates sharing a single
• Other (older) symbols are still widely used
enable signal
1 1 & >1 =1

EN

A1 &
OUT1
B1

A2
OUT2
B2
– inputs are on the left, outputs on the right
A3
OUT3
– qualifying symbol top centre: B3

1 Straight through (buffer) A4

OUT4
B4
& AND ≥1 OR
=1 XOR Σ Adder
P Multiplier MUX Multiplexer

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 Numbered Dependencies
• Other Dependencies
• Data inputs and outputs can be uniquely numbered
• Control input dependency labels can be followed by a number
– indicates which inputs or outputs they affect
Label Nam e On assertion ... On de-assertion ...
EN Enable perm its action prevents action – E.g.
G AN D (Gate) perm its action forces output low
V OR forces output high perm its action ENABLE G1
N NOT (Invert) Inverts output N o effect N2
INV
S Set forces output high N o effect
R Reset forces output low N o effect 1
OUT1
A1 1 2

A2 OUT2

– An array of buffers with

• inputs (1) are ANDed with the ENABLE signal
• outputs (2) are inverted if INV is asserted (active low)

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Active High and Active Low Inputs

IEEE Standard symbol for 4-input MUX
• Consider a device with an additional "enable" input
Enable
EN

Data Inputs
Outputs MUX
. .
0
}
. . A 0
. . select inputs G3
B 1
f
0
• The chip is enabled if the Enable input is "asserted”. 1
data inputs 2
3
• What does asserted mean?
– If the input is labelled EN, asserted means set Enable to 1
• Active High
– If the input is labelled EN , asserted means set Enable to 0
• Active Low

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