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Progress In Electromagnetics Research Symposium, Beijing, China, March 2327, 2009

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A Low Cost 1 Watt Doherty Power Amplier for WLAN and WiMAX Applications
Shilei Jin, Jianyi Zhou, Lei Zhang, and Wei Hong State Key Lab. of Millimeter Waves, School of Information Science and Engineering Southeast University, Nanjing 210096, China

Abstract This paper presents the design and implementation of a low-cost 1 Watt Doherty
Amplier with high eciency for the WLAN and WiMAX applications. Two 1 Watt Heterostructure FETs with SOT-89 surface-mount package are adopted as the nal stage of the carrier amplier and the peak amplier. The proposed Doherty amplier has the characteristic of both high power added eciency (PAE) and acceptable linearity. The superior performance is achieved through selecting the best operation point of the peak amplier. The sweet point of the developed Doherty amplier is about 3.5 dB back-o from the saturated power. According to the experimental results, the output P1dB power is about 33.5 dBm. When the output power is 30 dBm, the tested PAE is about 31.5% and the IMD3 is about 34 dBc. 1. INTRODUCTION

It is well known that the power amplier (PA) is one of the most important components in an RF transceiver. With the fast development and commercial applications of transmitters for the wireless local area network (WLAN) and worldwide interoperability for microwave access (WiMAX), the demand of medium output PA (about 1 Watt) is increasing rapidly [1]. Because of the high peak-to-average power ratio (PAPR) signals in the WLAN and WiMAX transceivers, the linearity of the transmitter becomes one of the most key factors in the system design. In fact, as the power amplier operates close to the saturation region where both high eciency and high output power are achieved, the degradation in linearity becomes signicant. Consequently PA must operate at a large amount of back-o from the peak output power, thus eciency is rather poor. Power amplication architectures with inherently more power ecient are being considered to improve the power eciency. Such techniques are included load modulation technique [2], envelope elimination and restoration (EER) [3], switching mode ampliers [4], and envelope tracking [5]. These techniques can provide high PEA, however the architectures are complicated with other disadvantages. The Doherty Power Amplier (DPA) is a promising candidate with advantages of high PAE, low cost and simple construction [6]. Doherty amplier techniques have been extensively studied to improve eciency, and could provide the advantage of improving the eciency and linearity simultaneously using a simple circuit [7]. Some advanced techniques of DPA have been reported [810] such as envelop tracking technique, using defected ground structure (DGS) microstrip line and weighted polynomial digital predistortion technique. These methods improve performance of DPA however there are many drawbacks including complex circuit conguration, modest enhancement and high cost. In this paper, two Heterostructure FETs (HFET) are adopted to construct a low-cost 1 Watt 2.4 GHz DPA for WLAN and WiMAX applications as shown in Figure 1. By selecting bias level of the peak amplier, the PAE of the DPA is signicantly improved with acceptable linearity at the 30 dBm output power. Additionally comparison between DPA and conventional Class-AB balanced power ampliers (CPA) is discussed in terms of power gain, PAE and IMD3.
2. CIRCUIT CONFIGURATION OF DOHERTY AMPLIFIER

The Doherty amplier was rst proposed by W. H. Doherty in 1936 [11]. A DPA consists of a carrier amplier and a peak amplier. At low input levels the peak amplier is cut o and carrier amplier operates as a linear class-AB amplier. For the input power above the transition point peak amplier turns on. Carrier amplier is still saturated to achieve high eciency and peak amplier provides additional power required. At peak output power both power ampliers are saturated. The output load is connected to the carrier amplier through an impedance inverter (a quarter-wave transmission line) and directly to the peaking amplier. Key concept of DPA is obtaining maximum eciency over 6 dB dynamic range using load modulation. The details of the discussion about the eciency enhancement principles are in [12].

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PIERS Proceedings, Beijing, China, March 2327, 2009

Figure 1 shows the schematic diagram of a DPA with o-set transmission lines at the output circuits which are used to fully match the two ampliers and enhance eciency of DPA [13].

Figure 1: Schematic diagram of Doherty power amplier. 3. EXPERIMENTAL RESULTS 3.1. Performance of Doherty Amplier at Dierent Bias Level

The research on the performance of the Doherty amplier focuses on dierent bias voltage of peak amplier. P1dB of HFET used to construct the proposed Doherty amplier is 30.8 dBm and the quiescent drain current is 250 mA operating at 2.4 GHz. At dierent bias level the peak amplier works at dierent operation points. As the bias voltage decreases, drain current degrades and peak amplier operates from class AB to class C. The carrier amplier is biased at class AB when peak amplier is cut-o to provide linear output power. Figure 2(a) shows measured PAE of Doherty amplier working at dierent bias level. Figure 2(b) shows the IMD3 character of two-tone signals measurement. The center of the two-tone signals is 2.4 GHz with space of 10 MHz. Table 1 shows values of quiescent drain current, IMD3, power gain and PAE at the average output power of 30 dBm. When the peak amplier is biased at class AB, both of quiescent drain current and power are higher. The peak amplier starts working at low input power so the PAE cannot hold a high level

(a)

(b)

Figure 2: (a) Measured PAE performance of Doherty power amplier at dierent operation points, (b) measured IMD3 performance of Doherty power amplier at dierent operation points. Table 1: Measure performance of Doherty amplier at dierent bias point. Drain Current [mA] 86 42 13 1 IMD3 [dBc] 36.2 33.6 32 28.1 Gain [dB] 14.1 13.7 13.3 12.8 PAE [%] 28.6 31.6 33.1 34.3

Progress In Electromagnetics Research Symposium, Beijing, China, March 2327, 2009

557

over a broad range at high input level. At class c level peak amplier turns on hardly when carrier amplier is saturated. Consequently PAE is improved. Because peak amplier turns on later when biased at deeper class c, the peak PEA is lower than other biased level. Although PAE performance of deeper class c is best at output power of 30 dBm the IMD3 deteriorates greatly. We can draw the conclusion that DPA with the bias voltage of 2.2 V and quiescent drain current of 13 mA works better than other operation points because of high PAE and acceptable linearity.
3.2. Measured Performance of the Proposed Doherty Amplier Biased at Perfect Point

Figure 3 shows a photograph of the implemented Doherty amplier applying technique of o-set line. In order to validate the proposed DPA, we design a CPA. Both ampliers use the same HFETs and work at 2.4 GHz. Peak amplier of the Doherty amplier is biased at the point we select above. The implemented Doherty ampliers have been further optimized experimentally to achieve high eciency and good linearity by modifying the o-set lines.

Figure 3: A photograph of the proposed Doherty amplier with o-set lines.

Figure 4(a) shows the power gain characters and measured PAE performance of the two ampliers at dierent output power levels. We can see that gain of DPA is degraded about 0.61.1 dB due to the lower bias voltage. The PAE of the Doherty amplier is improved over a broad average output power levels and enhanced by 9.1% at the output power of 30 dBm. The enhancement of PAE is not signicantly high because of consideration the linearity of Doherty amplier. Two-tone measurements results of the two ampliers are shown in Figure 4(b). Input signals are centered at 2.4 GHz with 10 MHz and 5 MHz spacing. Due to the dierent phase between carrier amplier and peak amplier third order harmonics tend to cancel out with each other. Through modifying the o-set lines we can change the phase to trade o between PAE and linearity. As shown in the gure, there is a trough around the output power of 30 dBm and the linearity is improved 24 dBc by harmonic cancellation.

(a)

(b)

Figure 4: (a) Measured gain and PAE performance of Doherty amplier and balanced amplier, (b) measured IMD3 performance of Doherty amplier and balanced amplier with the two-tone signal. 4. CONCLUSION

In this paper, we have constructed a low-cost 1 Watt average output power Doherty power amplier using two 1 Watt HFETs. To select the suitable operation point we measured the performance of

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PIERS Proceedings, Beijing, China, March 2327, 2009

the DPA with dierent bias level and chose the quiescent drain current of 13 mA as the perfect level. Additionally we optimized the Doherty amplier by modifying the o-set line. Working at 2.4 GHz the proposed DPA has signicantly improved the eciency over a broad average output power compared to the conventional balanced amplier. Moreover because of the harmonic cancellation of dierent IM3 phase the linearity of DPA is improved without any linearity enhancement techniques.
ACKNOWLEDGMENT

This work was supported in part by NSFC under Grant 60621002 and in part by the National High-Tech Project under Grant 2007AA01Z2B4.
REFERENCES

1. Ma, L. and D. Jia, The competition and cooperation of WiMax, WLAN and 3G, Mobile Technology, Applications and Systems 2nd International Conference, 15, Nov. 2005. 2. Nam, J., J. H. Shin, and B. Kim, A handset power amplier with high eciency at low level using load modulation technique, IEEE Trans. Microw. Theory Tech., Vol. 53, No. 8, Aug. 2005. 3. Raab, F. H., B. E. Sigmon, R. G. Myers, and R. M. Jackson, L-band transmitter using Kahn EER technique, IEEE Trans. Microw. Theory Tech., Vol. 46, No. 12, 22202225, Dec. 1998. 4. Tsai Pi, H., A. G. Metzger, P. J. Zampardi, M. Iwamoto, and P. M. Asbeck, Design of high eciency current-mode class D amplier for wireless handsets, IEEE Trans. Microw. Theory Tech., Vol. 53, No. 1, Jan. 2005. 5. Kimball, D. F., J. Jeong, C. Hsia, P. Draxler, S. Lanfranco, W. Nagy, K. Linthicum, L. E. Larson, and P. M. Asbeck, High-eciency envelope tracking W-CDMA base-station amplier using GaN HFETs, IEEE Trans. Microw. Theory Tech., Vol. 54, No. 11, 38483856, Nov. 2006. 6. McMorrow, R. J., D. M. Upton, and P. R. Maloney, The microwave Doherty amplier, IEEE MTT-S Int. Microwave Symp. Dig., 16531656, 1994. 7. Kenington, P. B., High-linearity RF Amplier Design, Artech House, Norwood, MA, 1999. 8. Yang, Y., J. Cha, B. Shin, and B. Kim, A microwave Doherty amplier employing envelop tracking technique for high eciency and linearity, IEEE Microw. Wireless Compon. Lett., Vol. 13, No. 9, Sep. 2003. 9. Choi, H. J., J. S. Lim, and Y. C. Jeong, A new design of Doherty ampliers using defected ground structure, IEEE Micro. Wireless Compon. Lett., Vol. 16, No. 12, Dec. 2006. 10. Hong, S., Y. Y. Woo, J. Kim, and J. Cha, Weighted polynomial digital predistortion for low memory eect Doherty amplier, IEEE Trans. Microw. Theory Tech., Vol. 55, No. 5, May 2007. 11. Doherty, W. H., A new high eciency power amplier for modulated waves, Proc. IRE, Vol. 24, No. 9, 11631182, 1936. 12. Raab, F. H., Eciency of Doherty RF power amplier system, IEEE Trans. Broadcast., Vol. BC-33, No. 3, 7783, Sep. 1987. 13. Yang, Y., J. Yi, Y. Y. Woo, and B. Kim, Optimum design for linearity and eciency of microwave Doherty amplier using a new load matching technique, Microwave J., Vol. 44, No. 12, 2036, Dec. 2001.

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