INTRODUCTION

In 1964 Texas Instruments introduced transistor-transistor logic (TTL), a widely used family of digital devices. TTL is fast, inexpensive, easy to use. TTL is a class of digital devices built from bipolar junction transistors (BJTs) and resistors. It is called transistor-transistor logic gating function and the amplifying signal are performed by transistors. TTL is notable for being a widespread integrated circuit chip (IC) family used in many applications such as computers, industrial control, test equipment and instrumentation , consumer electronics, etc. Transistortransistor logic is based on diode-transistor logic when it is discovered that one transistor could do the job of two diodes in space one diode even better, by more quickly switching off the following stage. The most widely known basic logic gates implemented by TTL technology are AND, OR, NAND, NOR, EXCLUSIVE-OR and EXCLUSIVE-NOR.

EXPERIMENT OBJECTIVES 1. 2. 3. 4. To gain experience with TTL gates formed by discrete transistors. To present basic characteristics and limitations of gates. To test different types of logic TTL gates. To construct TTL circuits using discrete transistors.

EQUIPMENT LIST 1. 2. 3. 4. 5. 6. 7. 8. 9. BC 107 transistor (2). 1N4148 diode (3). 3.9 K resistor (2). 1.8 k resistor (1). 1 k resistor (2). 100 resistor (1).
DC power supply. Breadboard. Connection wires.

EXPERIMENT PROCEDURE Logic Gate Implementation with Discrete BJTs

PART 1: Transistor NAND Gate

TTL contrasts with the preceding resistortransistor logic (RTL) and diode transistor logic (DTL) generations by using transistors not only to amplify the output but also to isolate the inputs. The p-n junction of a diode has considerable capacitance, so changing the logic level of an input connected to a diode, as in DTL, requires considerable time and energy.

V1
5V

R2
3.9k;

R4 R3
1.8k; 100;

D2
1N4148

Q3

D1
1N4148

Q1

BC107BP

V2
5V

BC107BP

D3
1N4148

R1
3.9k;

Q2
+ -

U1
-2.376m V DC 10M;

BC107BP

Fig 1. Is shown NAND gate consisting of diodes, transistors and resistors . As precisely mentioned in the experiment manual, a two-input transistor NAND gate has been connected and for which the truth table has been verified using a +5V voltage level for representing logic 1, although a 0V voltage level for representing logic 0 as two inputs to our TTL NAND gate. We have therefore measured the actual output voltage appearing at the Y output of the circuit for each set of input logic levels. Eventually, our goal of getting an exactly high value of +5V for logic 1 has been obtained as well as done for logic 0 when a 0V low value was applied.

Now, as will be shown below. Two truth tables will be made for showing all the realistic voltage measurements taken by measuring instruments, where the first truth table demonstrates the most widely known logic levels verified for a TTL NAND gate in view of a theoretical perspective. In addition , the second one completely represents those voltage levels taken in the lab. All of these measurements are verified for a TTL NAND gate.
A 0 0 1 1 B 0 1 0 1 OUTPUT 1 1 1 0

A (V) 0 0 5 5

B (V) 0 5 0 5

OUTPUT(V) 4.34 4.34 4.31 0.0057

PART 2: Transistor NOR Gate

V1
5V 1.0k;

U1
+

R2
3.9k;

R1 Y

0.054 DC 10M;

3.9k;

R5

Q1 A Q3 V2
5V BC107BP BC107BP

Q2 B Q4
BC107BP BC107BP

V3
5V

Fig 2. A two-input TTL NOR gate

The circuit drawn in the previous page is a TTL NOR gate when two high voltage levels are being applied at its two inputs making its output voltage level taken at node Y to be low. Now, the procedure method by which the experiment will be made is written below. As precisely mentioned in the experiment manual, a two-input transistor NOR gate has been connected and for which the truth table has been verified using a +5V voltage level for representing logic 1, although a 0V voltage level for representing logic 0 as two inputs to our TTL NOR gate. We have therefore measured the actual output voltage appearing at the Y output of the circuit for each set of input logic levels. Eventually, our goal of getting an exactly high value of +5V for logic 1 has been obtained as well as done for logic 0 when a 0V low value was applied.

A 0 0 1 1

B 0 1 0 1

OUTPUT 1 0 0 0

A (V) 0 0 5 5

B (V) OUTPUT(V) 0 5 0 5 5.08 0.017 0.017 0.017

Conclusion:
Within the TTL family, there are many second-generation families, each with different operating characteristics. Two important factors in the consideration of each logic family are speed and power consumption. These two tend to be directly related; i.e , higher aped consumes more power. Families can be characterized by the relationship delay and power. Most importantly, we have learned the way of constructing TTL NAND and TTL NOR gate by using only discrete transistor as well as the truth tables of which have been verified.

Homework Questions:
A: Design (a) a two input diode OR gate and (b) a two input diode AND gate as shown in fig 8. Choose suitable logic zero and one levels and define limits between the two states. Set up a truth table (a) and (b) and verify it. List the advantages and disadvantages of simple diode logic.
Ans : The circuit of figure (a) is an OR gate, the voltage level (0V) can be represented as logic (0), and the voltage level (5V) can be represented as logic (1). Here we should make it clear that the limits of voltages applied to inputs of an OR gate are { ViL=0 volts, VoL= 0 volt, ViH= 5 volts, VoH= 4.414 volts}. The idea of operation of this gate is now to be summarized in a few lines. When the input voltage is less than the forward voltage drop of diode, the diode will be in its OFF state which the output to be at its 0 level. When either input is higher than the forward voltage of diode connected, the current will now pass through the diode, causing in creating a voltage drop across the resistance ( 3.3 k) which makes the output to be at its high state.

The truth table of an OR gate :

A 0 0 1 1

B 0 1 0 1

OR
0 1 1 1

A second truth table verified for an OR gate by applying +5V as logic 1 and 0V as logic 0:

A 0 0 1 1

B 0 1 0 1

OR
0 4.395 4.395 4.414

The advantages of this circuit are easy to construct and the is not complicated. Whereas its main disadvantages are that there is not noise margin; i.e. the transfer characteristic between the output and the input is linear, so even if the input voltage is less than 5V the output will be high until we reach 1.6V, the output is 0.9V, meaning that it could be as a high voltage level for some other circuits.

The truth table of an AND gate : A 0 0 1 1 B 0 1 0 1

AND
0 0 0 1

A second truth table verified for an AND gate by applying +1.47V as logic 1 and 0V as logic 0: A 0 0 1 1 B 0 1 0 1

AND
0.067 0.080 0.080 1

Advantages of this AND diode gate are the ease of construction the gate and the loss of complexity. Whereas the disadvantages of which are that the low output state doesn t stay almost constant at low input voltages, but it varies between 0.067 to 0.08 volts when the input varies from 0 to 0.7 volts respectively.

Q2: design the circuits shown in figure 9 (a) and 9 (b), vary the input from 0 to +5 volts and plot the transfer characteristic which Vo vs Vi. Ans:

The circuit in figure 9(a) works as an inverter, if the input is high the transistor Q1 will be saturated, all the current will pass through it, so the output will be low. If the input is low the transistor Q1 will be cutoff, so the output will be high. The circuit in figure 9(b) works where it has a low output voltage if the input is low, the is because the output is taken from the emitter of Q2, so when the input is low transistor Q2 will be OFF and then there is no

current passing through 4.7k , leading the output to at its low state, if the input is high transistor Q2 will be saturated and the current will pass through causing a voltage drop across 4.7k , then the output will be high.

Q3: As an application of figure build a two input NOR gate using two BITs and three resistors . Observe the output voltage if one input is grounded and the second one is varied bet . 0 to +5 volts ? Ans :

This circuit works as a NOR gate . In case (a) the input of Q1 is low the same thing for Q2 , so Q1 and Q2 both of them will work at the cutoff region , as result the output will be low .

In case (b) the input of Q1 is high, so transistor Q1 works at saturation region, so all the source current will pass through Q1 so the output voltage will be low .