Thuc Hien Bo Loc FIR Thich Nghi Dung Thuat Toan LMS

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MC LC
BNG K HIU VIT TT ............................................................................................................................... 2
LI M U ........................................................................................................................................................ 4
CHNG 1............................................................................................................................................................ 5
TNG QUAN V FPGA V NGN NG VHDL............................................................................................ 5
1.1. TNG QUAN V FPGA ............................................................................................................................. 5
1.1.1. Lch s ra i ca FPGA.................................................................................................................... 5
1.1.2. Khi nim c bn v cu trc ca FPGA .......................................................................................... 6
1.1.3. Cc ng dng ca FPGA ................................................................................................................... 8
1.2. TNG QUAN V NGN NG VHDL ...................................................................................................... 8
1.2.1. Gii thiu v ngn ng m t phn cng VHDL .............................................................................. 8
1.2.2. Cu trc mt m hnh h thng m t bng ngn ng VHDL ....................................................... 10
CHNG 2.......................................................................................................................................................... 12
B LC FIR........................................................................................................................................................ 12
2.1. B LC FIR TRUYN THNG .............................................................................................................. 12
2.2. B LC FIR S DNG KIN TRC SYSTOLIC ARRAY.................................................................... 13
2.2.1. Tng quan v systolic array .............................................................................................................. 13
2.2.2. B lc FIR thc hin theo kin trc systolic array mt chiu......................................................... 14
CHNG 3.......................................................................................................................................................... 16
B LC FIR THCH NGHI DNG THUT TON LMS ............................................................................ 16
3.1. T VN ............................................................................................................................................ 16
3.2. CU TRC CA MCH LC THCH NGHI ......................................................................................... 18
3.3. MCH LC WIENER FIR ....................................................................................................................... 19
3.4. CC THUT TON THCH NGHI V NG DNG ............................................................................. 22
3.4.1. Phng php gim bc nhanh nht .............................................................................................. 22
3.4.2. Thut ton ton phng trung bnh ti thiu (LMS) ...................................................................... 25
CHNG 4.......................................................................................................................................................... 29
H THNG S B HAI V CC PHP TON............................................................................................ 29
4.1. BIU DIN S M TRONG H THNG S B HAI ........................................................................... 29
4.2. THC HIN CC PHP TNH TRONG H THNG S B HAI ......................................................... 30
4.2.1. Thc hin php cng trong h thng s b hai ............................................................................... 30
4.2.2. Thc hin php tr trong h thng s b hai .................................................................................. 31
4.2.3. Hin tng trn s ............................................................................................................................ 32
4.2.4. Thc hin php nhn trong s b hai .............................................................................................. 33
CHNG 5.......................................................................................................................................................... 35
THC NGHIM ................................................................................................................................................. 35
5.1. M T PHN CNG CA KIT VIRTEX-II PRO................................................................................... 35
5.2. KT QU THU C VI B LC FIR TRUYN THNG................................................................ 36
5.3. KT QU THU C VI B LC FIR THEO KIN TRC SYSTOLIC .......................................... 38
5.4. KT QU THU C VI B LC FIR THCH NGHI ....................................................................... 38
KT LUN .......................................................................................................................................................... 41
TI LIU THAM KHO................................................................................................................................... 42
PH LC ............................................................................................................................................................. 43
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BNG K HIU VIT TT
K Hiu
Din Gii
ASIC
Application Specific Integrated Circuit
ADC
Analog to Digital Converter
ALU
Arithmetic Logic Unit
ASM
Auto Senquencing Memory
CPLD
Complex Programmable Logic Device
CPU
Central Processing Unit
DSP
Digital Signal Processing
DAC
Digital to Analog Converter
DPU
Data Processing Unit
FIR
Finite Impulse Response
FPGA
Field Programmable Gate Array
HDL
Hardware Description Language
IC
Integrated Circuit
IEEE
Institute of Electrical and Electronics Engineers
JTAG
Joint Test Action Group
LED
Light Emitting Diode
LUT
Look Up Table
LMS
Least Mean Square
PAL
Programmable Array Logic
PLA
Programmable Logic Array
PCI
Peripheral Component Interconnect
PE
Process Element
RAM
Random Access Memory
ROM
Read Only Memory
RS232
Recommended Standard 232
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SoC
System on chip
SRAM
Static Random Access Memory
SPLD
Simple Programable Logic Device
USB
Universal Serial Bus
VHDL
Very High Speed Itergrated Circuit

Hardware Description Language
VHSIC
Very High Speed Itergrated Circuit
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LI M U
Ngy nay, x l tn hiu v lc s l mt ngnh pht trin ht sc mnh m, cc
cng ngh, thut ton ngy cng c i mi v ti u ho nhm nng cao tnh hiu
qu ca n. Tuy nhin, cng ngh pht trin cng cao th i hi phn cng phi
nhanh x l. Cc mch lc tng t trc y khng cn kh nng p ng
yu cu na. V vy, FPGA ra i nh mt gii php cung cp mi trng lm
vic hiu qu cho cc ng dng thc t. Tnh linh ng cao trong qu trnh thit k cho
php FPGA gii quyt nhng bi ton phc tp m trc kia ch thc hin nh phn
mm my tnh. Ngoi ra, nh mt cng logic cao, FPGA c ng dng cho nhng
bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi
gian thc. Nhng ng dng trong thc t ca FPGA rt rng ri, bao gm: cc h
thng hng khng, v tr, quc phng, tin thit k mu ASIC(ASIC prototyping), cc
h thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m
hc, m hnh phn cng my tnh...c bit, vi kh nng ti lp trnh, ngi s dng
c th thay i li thit k ca mnh ch trong vi gi.
Chnh v tnh thit thc m FPGA mang li, em quyt nh chn FPGA lm
hng nghin cu ca mnh. Trong bi kho lun ny, em xin trnh by mt ng dng
c th ca FPGA trong x l tn hiu s l Thc hin b lc FIR thch nghi
dng thut ton LMS. ti c thc hin ti phng th nghim mc tiu Cc h
tch hp thng minh ( SIS LAB) trc thuc trng i hc Cng ngh - HQG HN.
Em xin chn thnh cm n cc thy c gio c bit l PGS.TS Trn Quang Vinh
v Th.S Nguyn Kim Hng tn tnh hng dn v gip em hon thnh bn
lun vn ny mt cch tt p.
Do thi gian v kin thc c hn nn cng trnh ny khng th trnh khi sai st,
v vy em rt mong nhn c cc kin ng gp ca cc thy c v cc bn.
Em xin chn thnh cm n !
H Ni, Ngy 27 Thng 3 Nm 2008
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Chng 1
TNG QUAN V FPGA V NGN NG VHDL
1.1. TNG QUAN V FPGA
1.1.1. Lch s ra i ca FPGA
FPGA c thit k u tin bi Ross Freeman, ngi sng lp cng ty Xilinx
vo nm 1984, kin trc mi ca FPGA cho php tch hp s lng tng i ln cc
phn t bn dn vo 1 vi mch so vi kin trc trc l CPLD. FPGA c kh nng
cha ti t 100.000 n hng vi t cng logic, trong khi CPLD ch cha t 10.000
n 100.000 cng logic; con s ny i vi PAL, PLA cn thp hn na ch t vi
nghn n 10.000.
CPLD c cu trc t s lng nht nh cc khi SPLD (Simple programable
logic device) thut ng chung ch PAL, PLA. SPLD thng l mt mng logic
AND/OR lp trnh c c kch thc xc nh v cha mt s lng hn ch cc
phn t nh ng b (clocked register). Cu trc ny hn ch kh nng thc hin
nhng hm phc tp v thng thng hiu sut lm vic ca vi mch ph thuc vo
cu trc c th ca vi mch hn l vo yu cu bi ton.
Kin trc ca FPGA l kin trc mng cc khi logic, mi khi ny nh hn
nhiu nu em so snh vi mt khi SPLD, u im ny gip FPGA c th cha nhiu
hn cc phn t logic v pht huy ti a kh nng lp trnh ca cc phn t logic v h
thng mch kt ni, t c mc ch ny th kin trc ca FPGA phc tp hn
nhiu so vi CPLD.
Mt im khc bit na vi CPLD l trong nhng FPGA hin i c tch hp
nhiu b logic s hc c ti u ha, h tr RAM, ROM, tc cao, hay cc b
nhn, cng dng cho nhng ng dng x l tn hiu s.
Ngoi kh nng cu trc li vi mch mc ton cc, mt s FPGA hin i cn
h tr cu trc li mc cc b, tc l kh nng cu trc li mt b phn ring l
trong khi vn m bo hot ng bnh thng cho cc b phn khc
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1.1.2. Khi nim c bn v cu trc ca FPGA

FPGA (Field-programmable gate array) l vi mch dng cu trc mng phn t
logic m ngi dng c th lp trnh c. Ch field y mun ch n kh nng ti
lp trnh bn ngoi tu theo mc ch ng dng ca ngi s dng, khng ph thuc
vo dy chuyn sn xut phc tp ca nh my bn dn. Kin trc tng quan v FPGA
c m t nh hnh 1:
Hnh 1: Kin trc tng quan ca FPGA
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Vi mch FPGA c cu thnh t cc b phn:

Cc khi logic c bn lp trnh c (logic block)
Phn t chnh ca FPGA l cc khi logic (logic block). Khi logic c cu
thnh t LUT v mt phn t nh ng b flip-flop. LUT (Look up table) l
khi logic c th thc hin bt k hm logic no t 4 u vo, kt qu ca hm
ny ty vo mc ch m gi ra ngoi khi logic trc tip hay thng qua phn
t nh flip-flop.
Khi logic c m t nh hnh 2:
Hnh 2: Khi logic lp trnh c ca FPGA
Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi nim

SLICE, 1 Slice gm 4 khi logic to thnh, s lng cc Slices thay i t vi
nghn n vi chc nghn ty theo loi FPGA.
H thng mch lin kt lp trnh c
Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai
phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c
chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt
ni: ngn, di v rt di. Cc ng kt ni c ni vi nhau thng qua cc
khi chuyn mch lp trnh c (programable switch), trong mt khi chuyn
mch cha mt s lng nt chuyn lp trnh c, m bo cho cc dng lin
kt phc tp khc nhau.
Khi vo/ra (IO Pads)
Khi vo/ra nhiu hay t l tu thuc vo tng loi FPGA. Chng c th c
kt ni vi cc thit b bn ngoi nh LED, USB, RS232, RAM....tu theo mc
ch s dng
Cc phn t tch hp sn
Ngoi cc khi logic, ty theo cc loi FPGA khc nhau m c cc phn t tch
hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex
4, 5 ca Xilinx c cha nhn x l PowerPC, hay cho nhng ng dng x l tn
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hiu s trong FPGA c tch hp cc DSP Slice l b nhn, cng tc cao,

thc hin hm A*B+C, v d dng Virtex ca Xilinx cha t vi chc n hng
trm DSP slices vi A, B, C 18-bit.
1.1.3. Cc ng dng ca FPGA
ng dng ca FPGA bao gm: x l tn hiu s, cc h thng hng khng, v tr,
quc phng, tin thit k mu ASIC(ASIC prototyping), cc h thng iu khin trc
quan, phn tch nhn dng nh, nhn dng ting ni, mt m hc, m hnh phn cng
my tnh...
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp
nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi ra
nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi
lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.
1.2. TNG QUAN V NGN NG VHDL

Thit k hay lp trnh cho FPGA c thc hin ch yu bng cc ngn ng m
t phn cng HDL nh VHDL, Verilog ...cc hng sn xut FPGA ln nh Xilinx,
Altera thng cung cp cc gi phn mm v thit b ph tr cho qu trnh thit k,
cng c mt s cc hng th ba cung cp cc gi phn mm kiu ny nh Synopsys,
Synplify... Cc gi phn mm ny c kh nng thc hin tt c cc bc ca ton b
quy trnh thit k IC chun vi u vo l m thit k trn HDL (cn gi l m RTL).
Trong bi Lun vn ny, c s dng ngn ng m t phn cng VHDL, do ta
ch tp chung tm hiu v ngn ng VHDL.
1.2.1. Gii thiu v ngn ng m t phn cng VHDL
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt
loi ngn ng m t phn cng c pht trin dng cho trng trnh VHSIC( Very
High Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin
VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho
php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h
thng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics,
IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm 1983. Phin
bn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chc
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IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v

VHDL( tiu chun IEEE-1076-1987).
VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i
v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu
m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu k lng ti
liu . Vi mt ngn ng m phng phn cng tt vic xem xt cc ti liu m t tr
nn d dng hn v b ti liu c th c thc thi m phng hot ng ca h
thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trong
mt m hnh thng nht.
VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt
phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c
th t do la chn cng ngh, phng php thit k trong khi ch s dng mt ngn
ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc k
ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc:
- Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh
ph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca
nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m
phng h thng.
- Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL
cho php thit k bng nhiu phng php, v d phng php thit k t trn
xung, hay t di ln da vo cc th vin sn c. VHDL cng h tr cho
nhiu loi cng c xy dng mch nh s dng cng ngh ng b hay khng
ng b, s dng ma trn lp trnh c hay s dng mng ngu nhin.
- Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh
ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th
c chuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch
to phn cng mi ra i n c th c p dng ngay cho cc h thng thit
k .
- Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phn
cng t mc h thng s cho n mc cng. VHDL c kh nng m t hot
ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch
thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm
c cc h con c m t chi tit.
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- Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chp

nhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu
chun VHDL. Cc kt qu m t h thng c th c trao i gia cc nh
thit k s dng cng c thit k khc nhau nhng cng tun theo tiu chun
VHDL. Cng nh mt nhm thit k c th trao i m t mc cao ca cc h
thng con trong mt h thng ln (trong cc h con c thit k c lp).
- Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thit
k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th
c s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu
ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th
nghim v chia s thit k. V n cng cho php dng li cc phn c sn.
1.2.2. Cu trc mt m hnh h thng m t bng ngn ng VHDL
Mc ch ca phn ny s nhm gii thiu s qua v cu trc khung c bn ca
VHDL khi m t cho mt m hnh thit k thc.
Thng thng mt m hnh VHDL bao gm ba phn: thc th, kin trc v cc
cu hnh. i khi ta x dng cc gi (packages) v m hnh kim tra hot ng ca h
thng (testbench).
+ Thc th (entity): Khai bo thc th trong VHDL l phn nh ngha cc ch
tiu pha ngoi ca mt phn t hay mt h thng. Thc cht ca vic khai bo thc
th chnh l khai bo giao din ca h thng vi bn ngoi. Ta c th c tt c cc
thng tin kt ni mch vo mch khc hoc thit k tc nhn u vo phc v cho
mc ch th nghim. Tuy nhin hot ng tht s ca mch khng nm phn khai
bo ny
+ Kin trc (Architecture): Phn th 2 trong m hnh VHDL l khai bo kin
trc. Mi mt khai bo thc th u phi i km vi t nht mt kin trc tng ng.
VHDL cho php to ra hn mt kin trc cho mt thc th. Phn khai bo kin trc c
th bao gm cc khai bo v cc tn hiu bn trong, cc phn t bn trong h thng,
hay cc hm v th tc m t hot ng ca h thng. Tn ca kin trc l nhn c
t tu theo ngi s dng. C hai cch m t kin trc ca mt phn t ( hoc h
thng) l m hnh hot ng (Behaviour) hay m t theo m hnh cu trc
(Structure). Tuy nhin mt h thng c th bao gm c m t theo m hnh hot ng
v m t theo m hnh cu trc.
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+ M t kin trc theo m hnh hot ng: M hnh hot ng m t cc hot

ng ca h thng ( h thng p ng vi cc tn hiu vo nh th no v a ra kt
qu g ra u ra) di dng cc cu trc ngn ng lp trnh bc cao. Cu trc c th
l PROCESS, WAIT, IF, CASE, FOR-LOOP
+ M t kin trc theo m hnh cu trc: M hnh cu trc ca mt phn t
(hoc h thng) c th bao gm nhiu cp cu trc bt u t mt cng logic n gin
n xy dng m t cho mt h thng hon thin. Thc cht ca vic m t theo m
hnh cu trc l m t cc phn t con bn trong h thng v s kt ni ca cc phn t
con . Nh vi v d m t m hnh cu trc mt flip-flop RS gm hai cng NAND
c th m t cng NAND c nh ngha tng t nh v d vi cng NOT, sau
m t s mc ni cc phn t NAND to thnh trig RS
+ Cu trc Process: Process l khi c bn ca vic m t theo hot ng.
Process c xt n nh l mt chui cc hnh ng n trong sut qu trnh dch.
Cu trc tng qut:
[tn nhn]:
process
[(danh sch cc yu t kch thch hot ng)]

[khai bo cc bin]
begin
[cc cu lnh]
end process;
+ Mi trng kim tra (testbench): Mt trong cc nhim v rt quan trng l

kim tra bn m t thit k. Kim tra mt m hnh VHDL c thc hin bng cch
quan st hot ng ca n trong khi m phng v cc gi tr thu c c th em so
snh vi yu cu thit k.
Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kim
tra sinh ra cc tc ng ln bn thit k v cho php quan st hoc so snh kt qu hot
ng ca bn m t thit k. Thng thng th cc bn m t u cung cp chng
trnh th. Nhng ta cng c th t xy dng chng trnh th (testbench). Mch th
thc cht l s kt hp ca tng hp nhiu thnh phn. N gm ba thnh phn: m
hnh VHDL qua kim tra, ngun d liu v b quan st. Hot ng ca m hnh
VHDL c kch thch bi cc ngun d liu v kim tra tnh ng n thng qua b
quan st.
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Chng 2
B LC FIR
2.1. B LC FIR TRUYN THNG

B lc FIR l b lc c p ng xung chiu di hu hn, tc l p ng xung ch
khc khng trong mt khong c chiu di hu hn N (t 0 n N-1). B lc FIR vi
bc ca b lc l N c biu din nh hnh 3:
Hnh 3: Cu trc ca b lc FIR truyn thng
Trong :
x[n]: l tn hiu li vo ca mch
y[n]: l tn hiu li ra ca mch
h[n]: l p ng xung ca mch
Li ra y[n] v li vo x[n] lin h vi nhau bi cng thc:
N 1
y[n] =
h[k ]x[n k ]
k =0
tnh c cc gi tr y[k] t cc mu li vo x[k] th cc mu ln lt qua cc

b tr, b nhn v b cng. Vi b lc FIR c bc l N th phi sau N php nhn v N1 php cng th mi tnh c gi tr ca li ra.
Nh vy, b lc FIR c cu trc nh trn c nhc im l kh nng p ng
chm, cc mu li ra khng c lin tc m sau mt khong thi gian tnh ton xong
cc php nhn v php cng mi c xut ra.
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khc phc nhc im , ta s dng kin trc systolic array nng cao kh
nng p ng ca mch
2.2. B LC FIR S DNG KIN TRC SYSTOLIC ARRAY

2.2.1. Tng quan v systolic array
Systolic array l cu trc x l song song c bit cha cc khi x l d liu
(data processing unit gi tt l DPU), cc khi x l ny c sp xp thnh mt
mng. DPU tng t nh CPU nhng n khng c b m chng trnh. Tng khi
DPU nh l mt trigger truyn thng bi s lun chuyn d liu t DPU ny n cc
DPU ln cn. Thng thng, nhng d liu khc nhau th s lun chuyn theo cc
hng khc nhau. Cc lung d liu ti v ri khi cc cng DPU c pht t ASM
(Auto senquencing memory l thnh phn khng th thiu ca cu trc Non-VonNeumann. Trong cu trc ny, c ch senquencing ng vai tr l b m chng
trnh). Mi ASM ng vai tr l b m d liu. Trong h thng ny, lung d liu
vo c th vo t u ra ca thit b ngoi vi v ngc li.
Cc b x l (DPU) tnh ton d liu, lu tr d liu theo nhng cch c lp vi
nhau. Cc b x l ny c th c mt vi thanh ghi v khi ALU. Cc DPU c kh
nng l tr v x l d liu c lp vi nhau. Mi DPU sau khi x l d liu xong s
chia s d liu cho cc Cell ln cn.
Trong hnh 4, m t kin trc Systolic array mt chiu, d liu chuyn ng theo
mt hng
PE
PE
PE
PE
PE
Hnh 4: Cu trc systolic array mt chiu
Hnh 5 m t kin trc systolic array hai chiu, d liu chuyn ng hai hng
theo chiu ca mi tn qua cc b DPU. D liu ra cng theo hai hng
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Hnh 5: Kin trc systolic array hai chiu
2.2.2. B lc FIR thc hin theo kin trc systolic array mt chiu
cho vic x l d liu c nhanh hn, b lc FIR theo kin trc Systolic
array s bao gm mt dy cc phn t x l hay cn gi l PE (Process Element).
Trong cng mt thi im, cc PE s thc hin ng thi cc nhim v ring, v do
, tn hiu li ra s c a ra mt cch lin tc m khng phi mt mt khong
thi gian tnh ton do n c tnh t trc .
Cu trc ca mt PE ca b lc FIR SYSTOLIC c trnh by nh trong hnh 6
Hnh 6: Cu trc ca mt PE
Nh vy, cu trc ca b lc FIR Systolic vi bc b lc l N, gm N+1 PE

c trnh by nh hnh 7
14
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Yin
+
..
x aN
yout
x ao
xin
..
xout
Hnh 7: Cu trc b lc FIR systolic bc N
Khc vi b lc FIR thng thng, u ra ca b cng li c a qua 2 b

cht lm tr, n c tc dng chia ng truyn tn hiu ca mch thnh nhng on
nh, do lm tng tn s hot ng ca mch, ng thi lm cho tn hiu xin v yin
vo b cng cng mt lc, do , tn hiu ra s c lin tc, p ng nhanh, bi vic
tnh ton c thc hin trc .
Vi vic chia ng truyn di nht ca mch thnh nhng on nh nh cc
thanh ghi cht, ta cn c th ti u b lc FIR systolic hn na. Hnh 8 m t cu trc
ti u ca b lc FIR systolic.
Yin
+
yout
..
x aN
x ao
xin
..
xout
Hnh 8: Cu trc ti u ca b lc FIR systolic bc N
M hnh ny v tng vn ging m hnh trc, bao gm cc thanh ghi cht,

b cng, b nhn ca m hnh trc, tuy nhin, c s thay i v tr ca cc thanh ghi
cht, trc b nhn v b cng ta chn thm mt thanh ghi cht vo chia nh
ng truyn tn hiu. Do , lm cho tn s hot ng ca mch tng ln.
15
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Chng 3
B LC FIR THCH NGHI DNG THUT TON LMS
3.1. T VN
Thut ng lc dng ch tt c cc h thng c kh nng khi phc li dng ca
cc thnh phn tn s ca tn hiu li vo to ra tn hiu li ra tha mn cc yu cu
mong mun. Vi b lc FIR trnh by trn, th h s ca b lc lun khng i. Do
, nu c s thay i t ngt ca mt hoc mt vi yu t u vo(nh tn hiu
nhiu chng hn) th b lc s khng cn c ti u na. Hay ni cch khc, ta
khng thu c tn hiu mong mun.
khc phc nhc im trn, ngi ta a ra mt b lc FIR c cu trc mi,
m trong , cc h s ca b lc c th thay i c c th thch ng vi s thay
i bt ng ca cc yu t li vo. Mch lc FIR c cc h s thay i nh vy c
gi l mch lc FIR thch nghi. Gin khi ca mch lc nh vy c trnh by
trong hnh 9.
Tn hiu mong mun

d(n)
+
Tn hiu vo x[n]
__
h[n]=h0,h1...
+
y[n]
Tn hiu sai s
e[n]
Hnh 9: Gin khi ca mch lc thch nghi
Trong s ny, tn hiu li vo l mt dy thi gian ri rc x[n], mch lc c

c trng bi p ng xung h[n], cn tn hiu li ra thi im n l mt dy y[n].
16
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Li ra ny c s dng xc nh mt p ng mong mun d[n]. Cc h s

ca mch lc phi c chn la sao cho dy tn hiu mong mun c dng ph hp
nht vi tn hiu li vo. iu ny c th c thc hin nu dy tn hiu sai s e[n]
hi t v khng nhanh nht. lm c iu ny, ta phi ti u ho mt hm sai s
c xc nh theo phng php thng k hoc phng php quyt nh. i vi
phng php thng k, th hm sai s c s dng l gi tr ton phong trung bnh
ca tn hiu sai s e[n]. Nu tn hiu vo v tn hiu mong mun l nhng tn hiu
dng, th vic cc tiu ho sai s ton phng trung bnh a n mt mch lc rt ni
ting l mch lc Wiener, c gi l ti u theo ngha ton phng trung bnh.
Hu ht cc thut ton thch nghi l p dng cho cc loi mch lc Wiener. Trong
phng php quyt nh, cch chn hm sai s l mt tng trng s ca tn hiu sai s
ton phng. Vic cc tiu ho hm ny dn n mt mch lc ti u i vi dy d
liu cho.
Nh vy, mch lc c thit k hoc bng cc cng thc thng k hoc bng
cc cng thc xc nh. Trong cc thit k xc nh, cn phi tnh ton mt s i
lng trung bnh khi s dng dy d liu cho m mch lc cn x l. Ni cch khc,
thit k c mch lc Wiener cn phi bit trc cc tnh cht thng k ca cc tn
hiu c s. Trong trng hp ny, cc dy tn hiu c s thng c cho l tn hiu
dng v trung bnh theo thi gian bng trung bnh thng k.
Mc d php o trc tip cc gi tr trung bnh ca tn hiu c th c thc hin
thu c nhng thng tin cn thit cho vic thit k mch lc Wiener hoc cc
mch lc ti u, nhng trong nhiu ng dng thc t, cc gi tr trung bnh ca tn hiu
li c s dng theo cch gin tip, trong sai s li ra ca mch lc tng quan
vi cc mu ca tn hiu vo ca mch lc theo mt s cch v s dng kt qu ca
phng trnh quy iu chnh cc h s ca mch theo kiu lp.
S dng phng php lp c th a n cc li gii thch nghi c kh nng t
hiu chnh. C ngha l nu cc tnh cht thng k ca tn hiu thay i i vi thi
gian, th nh nghim lp, cc h s ca mch lc c th t iu chnh thch nghi
vi cc tnh cht thng k mi.
Nghim lp, ni chung rt c a chung v n d m ho trong phn mm v
d thc thi trong phn cng hn cc nghim khng lp.
17
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
3.2. CU TRC CA MCH LC THCH NGHI

Cu trc thng c s dng trong mch lc thch nghi c m t nh hnh
10:
x[n]
-1
x[n-1]
wN-1[n]
w1[n]
wo[n]
x
x[n-N+1]
z-1
-1
+
y[n] e[n]
Thut ton thch nghi
+
+
Hnh 10: Cu trc ca mch lc FIR thch nghi
Trong :
x[n] : Vector tn hiu u vo ca mch lc.
x[n] = [xn xn-1 xn-2 xn-N+1]T
w: L vector trng s ca b lc thch nghi
w = [w0 w1wN-1]T
y[n] : l li ra ca mch lc
y[n] =
N 1
w[k ]x[n k ] wT x[n]
(3.1)
k =0
d[n] : l li ra mong mun

e[n] : l sai s gia tn hiu mong mun d[n] v tn hiu u ra y[n]
e[n]=d[n]-y[n]
(3.2)
18
Nguyn Anh Cng
d[n]
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Bi ton thch nghi s t iu chnh ma trn cc trng s w sao cho sai s e[n] l
nh nht.
3.3. MCH LC WIENER FIR

V wTx[n] l mt v hng nn bng chuyn v ca n, tc l:wTx[n]=xT[n]w.
Do , t (3.1) v (3.2) ta c:
e[n]=d[n]-y[n]=d[n]-wTx[n]=d[n]-xT[n]w
(3.3)
i vi mch lc Wiener, hm hiu nng c chn l sai s ton phng trung

bnh:
J= E[|e[n]|2]
(3.4)
Trong k hiu E[.] l k vng thng k. Thay (3.3) vo (3.4) ta c:

J= E[(d[n]-wTx[n])(d[n]-xT[n]w)]
(3.5)
Khai trin (3.5) v ch w c th a ra ngoi ton t E[.] v n khng phi l

bin s thng k, ta thu c:
J=E[d2[n]]wTE[x[n]d[n]] E[d[n]xT[n]]w + wTE[x[n]xT[n]]w
(3.6)
Ta nh ngha vector tng quan cho bc Nx1:

P = E[x[n]d[n]] = [P0 P1 PN-1 ] T
(3.7)
V ma trn tng quan:
R=E[x[n]x [n]] =
R00
R01
R02
R0 N-1
R10
R11
R12
R1 N-1
..
..
.
.
.....
..
..
..
..
..
..
RN-1 0 RN-1 1 RN-1 2
19
(3.8)
RN-1 N-1
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Ch l: E[d[n]xT[n]] = PT; wTP = PTw, ta thu c:

J = E[d2[n]] 2wTP + wTRw
(3.9)
thu c tp trng s ng vi hm ph tn J c gi tr cc tiu, ta cn phi

gii h phng trnh c to thnh t o hm bc nht ca J i vi mi tp trng s
wi bng khng, tc l:
J
=0
wi
, vi i = 0,1,2N-1
(3.10)
Cc phng trnh trn c th vit di dng ma trn:

J = 0
(3.11)
y l ton t vi phn c xc nh nh mt vect ct:
w[ 0 ]
w[1]
w[ N 1]
(3.12)
tm cc o hm ring ca J i vi cc tp trng s wi ca mch lc, trc

ht phi khai trin h thc (3.9) thnh dng tng minh:
N 1
N 1 N 1
k =0
k =0 m =0
J = E[d2[n]] 2 P[k ]w[k ] + w[k ]w[m]R[k , m]
(3.13)
Tng kp trong (3.13) c th khai trin di dng:

N 1 N 1
w[k ]w[m]R[k , m] =
k =0 m =0
N 1 N 1
w[k ]w[m]R[k , m] +wi

k =0 m 0
k #i m #i
+wi2R[k,i]
N 1
w[k ]R[k , i] +wi

k =0
k #i
N 1
w[m]R[k , m]
m =0
m #k
(3.14)
Thay (3.14) vao` (3.13), sau ly o hm ring phn ca J theo wi v thay

th m cho k ta c:
20
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
J
= -2Pi +
w[i ]
Kho lun tt nghip
N 1
w[k ]( R[k , i] + R[i, k ] )
, vi i=0,1,2,,N-1
(3.15)
k =0
Trong trng hp ny ta thy:

Rki = E[x[n-k]x[n-i]] = xx[i-k]
(3.16)
y xx[i-k] l hm t tng quan ca x[n]

Tng t:
Rik = xx[k-i]
(3.17)
Do tnh cht i xng ca hm t tng quan nn xx[k] =xx[-k], ta thu c:

Rki = Rik
(3.18)
Thay (3.18) vo phng trnh (3.15) ta c:

J
= -2Pi + 2
w[i ]
N 1
R[i, k ]w[k ] , vi i = 0,1,2,N-1
(3.19)
k =0
Phng trnh trn c th biu din di dng ma trn:

J = 2Rw 2P
(3.20)
t J=0 ta s thu c phng trnh ti u ho tp trng s ca mch lc

Wiener
Rwo = P
(3.21)
y l phng trnh Wiener-Hopf i vi vetor trng s ti u wo:

wo = R-1P
(3.22)
Thay gi tr wo va tm c t phng trnh Wiener-Hopf v Rwo=P vo

phng trnh (3.9) ta s tm c gi tr cc tiu ca hm ph tn J:
Jmin = E[d2[n]] - woT P
= E[d2[n]] - woTRwo
(3.23)
l sai s cc tiu m mch lc Wiener FIR W(z) c th t c khi tp trng

s ca n l nghim ca phng trnh Wiener-Hopf, ngha l nghim ti u (3.22)
21
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
3.4. CC THUT TON THCH NGHI V NG DNG

Trong phn ny, chng ta nghin cu ch yu thut ton ton phng trung bnh
ti thiu LMS. Thut ton ny c p dng rng ri trong x l s thch nghi v
thng k do tnh cht bn vng v n gin ca n. Nh thut ton ny m dy sai s
hi t v khng vi tc nhanh, tu theo bc gim cp. V vy, da trn thut ton
ny, ngi ta pht trin nhiu thut ton nhanh
3.4.1. Phng php gim bc nhanh nht
y l phng php lp tm tp trng s tng ng vi im cc tiu ca mt
sai s ca mch lc Wiener FIR. Trong phng php ny, hm ph tn cn cc tiu
ho c gi thit l phn k v xut pht t mt m bt k trn mt sai s, ta ly mt
bc nh theo hng m trong hm ph tn gim nhanh nht. Ti im , hm ph
tn ca mch lc Wiener s c gi tr ti u.
x[n]
z-1
x[n-1]
z-1
wN-1[n]
w1[n]
wo[n]
x
z-1
y[n] __
e[n]
Thut ton thch nghi
d[n]
Hnh 11: Mch lc Wiener FIR
i vi mch lc Wiener nh hnh, dy tn hiu vo mch lc l x[n] v dy tn

hiu mong+ mun d[n] v tp trng s wi c gi thit l nhng dy s thc. Khi ,
dy li ra ca mch lc:
22
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
y[n] = wTx[n] = w xT[n]
(4.1)
Nhc li rng khi hm ph tn t gi tr cc tiu th tp vector trng s t n

gi tr ti u, tho mn phng trnh Wiener-Hopf:
Rwo=P
(4.2)
y, thay cho vic gii phng trnh mt cch trc tip, ta gii bi ton bng
cch tm mt phng php lp.
Theo phng php ny, xut pht t gi tr d on trc i vi wo, gi l w(0),
nh tnh ton quy thc hin nhiu php lp hi t ti wo. Thut ton lp ny
thng xuyn c s dng trong cc mch lc thch nghi.
Phng php gim bc nhanh nht c thc hin theo cc bc sau:
1.
Xut pht t cc thng s d on ban u m cc gi tr ti u ca n

tm c cc tiu ho hm ph tn.
2.
Tm gradient ca hm ph tn ng vi cc thng s ti im xut pht
3.
Cp nht cc thng s bng cch ly mt bc theo hng ngc vi

vector gradient thu c trong bc 2. iu tng ng vi bc gim
nhanh nht trong hm ph tn. Ngoi ra, kch thc ca bc c chn t
l vi kch thc ca vector gradient
4.
Lp li cc bc 2 v 3 cho n khi khng th thay i c na trong

cc thng s
Theo cc th tc trn, nu w(k) l vector tp trng s ti php lp th k, th

phng trnh truy hi sau y c th c s dng cp nht w(k):
w(k+1) = w(k) - kJ
(4.3)
trong :
kJ = 2Rw(k)-2P
(4.4)
Thng s l i lng v hng dng c gi l kch thc ca bc. y

l thng s rt quan trng v tc hi t ca w(k) ti gi tr ti u wo ph thuc vo
thng s ny, tc l vo kch thc ca bc la chn. Nu kch thc bc ln c
th s hi t s nhanh hn, nhng b li tnh n nh s km hn
23
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Thay (4.4) vo (4.3) ta c:

w(k+1) = w(k) - 2(Rw(k) P)
(4.5)
c th thy s cp nht cc gi tr w(k) cho hi t ti wo, ta vit li (4.5) :

w(k+1) - wo = (I-2R)(w(k)-wo)
(4.6)
Ta nh ngha vector:
v(k) = w(k) - wo
(4.7)
Khi (4.6) tr thnh:

v(k+1) = (I-2R)v(k)
(4.8)
Phng trnh (4.8) s c dng n gin hn na nu ta a ma trn tng quan R

v dng cho. Ngha l ta t:
R=QQT
(4.9)
V thay ma trn n v I=QQT, khi (4.8) tr thnh:

v(k+1) = (QQT - 2QQT)v(k) = Q(I-2)QTv(k)
(4.10)
Trong l ma trn cho c to thnh t cc gi tr ring ca ma trn tng

quan R, cn Q l ma trn c to thnh t cc vector ring trc giao tng ng
t:
v(k) = QTv(k)
(4.11)
Nh vy ta thu c phng trnh truy hi i vi vector v(k) nh sau:

v(k+1) =(I-2)v(k)
(4.12)
phng trnh vector (4.12) c th tch thnh cc phng trnh v hng :

vi(k+1) = (1-2i) vi(k)
vi i=0,1,,N-1
(4.13)
y, vi(k) l phn t th i ca vector v(k)

Nu bt u t dy gi tr ban u vo(0), v1(0),,vN-1(0) v sau k php lp
chng ta s thu c:
vi(k) = (1-2i)vi(0)
vi i=0,1,,N-1
(4.14)
T (4.7) v (4.11) ta thy rng w(k) hi t ti wo khi v ch khi v(k) hi t ti

vector khng. Nhng (4.14) li cho thy vi(k) hi t ti khng khi v ch khi thng s
bc c chn sao cho:
24
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
|1-2i| < 1 , vi i=0,1,,N-1
(4.15)
Khi (4.15) tho mn th thnh phn th i ca vector vi(k) s hi t nhanh v

khng theo hm e-m khi s lng php lp tng ln. Ngoi ra (4.15) cng l iu kin
chn kch thc ca bc sao cho thut ton gim cp nhanh nht v n nh.
iu kin c th khai trin di dng :
-1<1-2i<1 hay:
0<<
1
i
(4.16)
Do kch thc bc c p dng cho tt c cc gi tr ca i, nn tnh cht hi

t v n nh ca thut ton gim bc nhanh nht c m bo khi:
0<<
1
max
(4.17)
Vi max l gi tr ring cc i ca cc gi tr ring: 0,1, N-1

By gi ta vit thut ton gim bc nhanh nht cho vector tp trng s w(k) ca
mch lc. Ta thy :
w(k) = wo + v(k) = wo + Qv(k)
= wo+[qo q1qN-1 ] [vo(k) v1(k) .vN-1(k)]T
= wo +
N 1
q[i]v'[i](k )
(4.18)
i =0
y qo,q1,qN-1, l cc vector ring gn vi cc gi tr ring o, 1, N-1 ca ma trn

tng quan R.
Thay (4.14) vo (4.18) ta thu c:
w(k) = wo+
N 1
v' i(0)(1-2i)k qi
(4.19)
i =0
Kt qu ny cho thy mi gi tr ring i xc nh mt kiu hi t ring theo mt

hng c xc nh bi vector ring tng ng qi ca n. Cc kiu hi t khc nhau
hot ng c lp vi nhau. Vi mt gi tr chn la ca thng s bc , th tha s
1-2i xc nh gi tr i kiu hi t th i hi t nhanh nht.
3.4.2. Thut ton ton phng trung bnh ti thiu (LMS)
Thut ton ton phng trung bnh ti thiu LMS (Least Mean Square) l
thut ton c p dng rng ri trong x l s tn hiu thch nghi. N thuc h cc
25
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
thut ton gradient thng k ln u tin c Windrow-Hoff p dng nm 1960 v

sau pht trin thnh nhiu thut ton mi nh tnh cht n gin v bn vng ca
thut ton ny. N l thut ton lc thch nghi tuyn tnh bao gm hai qu trnh: qu
trnh lc v thch nghi. Trong qu trnh lc, thut ton ny s dng mch lc ngang
tuyn tnh c li vo x(n) v li ra y(n). Qu trnh thch nghi c thc hin nh s
iu khin t ng cc tp trng s ca cc h s ca mch lc sao cho n tng ng
vi tn hiu sai s l hiu ca tn hiu li ra vi tn hiu mong mun d(n). S ca
thut ton nh trong hnh.
x[n]
z-1
x[n-1]
z-1
wN-1[n]
w1[n]
wo[n]
x
z-1
y[n] __
Thut ton LMS
e[n]
+
+
d[n]
Hnh 12: Mch lc FIR thch nghi dng thut ton LMS
Gi s mch lc ngang c N- tp trng s v l dy s thc, khi tn hiu li ra

c vit:
y[n] =
N 1
w k[n] x[n-k]
(4.20)
k =0
Trong tp trng s wo[n]..,wN-1 [n] c chn la nh th no sai s:

e[n]= d[n] - y[n]
(4.21)
c gi tr cc tiu. Ni chung trong mch lc thch nghi, tp trng s l hm ca

ch s thi gian n, v chng c thch nghi lin tc vi s thay i thng k ca tn
hiu. Thut ton LMS iu chnh tp trng s ca mch lc sao cho sai s e[n] c
26
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
cc tiu ho theo ngha ton phng trung bnh, v th mi c tn l thut ton ton
phng trung bnh ti thiu. Khi cc qu trnh x[n] v d[n] l cc qu trnh ngu nhin
dng, th thut ton ny hi t n nghim ca phng trnh Wiener-Hopf. Ni cch
khc, thut ton LMS l mt s thc t thc hin cc mch lc Wiener-Hopf,
nhng khng gii mt cch tng minh phng trnh Wiener-Hopf. N l mt thut
ton tun t c s dng thch nghi tp trng s ca mch lc nh s quan st lin
tc tn hiu li vo x[n] v tn hiu li ra mong mun d[n].
Nh vy, thut ton LMS chnh l s thc thi thng k ca thut ton gim bc
nhanh nht, trong hm ph tn J=E[e2[n]] c thay bng gi tr xc nh tc thi
j^[n] = e2[n]. Khi phng trnh truy hi tnh tp trng s ca mch lc c xc
nh bng phng trnh:
w[n+1] = w[n] - e2[n]
(4.22)
trong w[n] = [wo[n],w1[n],.,wN-1[n]]T, l thng s bc ca thut ton cn

l ton t vi phn c xc nh bng vector ct nh sau:

w[0]
w[1]

w[N 1]
(4.23)
Nh vy thnh phn th k ca vector e2[n] l:

2
e[n]
e [n] = 2e[n]
wi
wi
(4.24)
Thay e[n]=d[n]-y[n] vo phng trnh trn v do d[n] c lp vi wi, ta c:

2
y[n]
e [n] = -2e[n]
wi
wi
(4.25)
By gi, thay y[n] t (4.20) vo (4.25) ta c:

2
e [n] = - 2e[n]x[n-i]
wi
(4.26)
27
Nguyn Anh Cng
H Cng Ngh- HQG H Ni
Kho lun tt nghip
Hoc di dng tng qut l:

e2[n] = -2e[n]x[n]
(4.27)
Trong : x[n]=[ x[n], x[n-1].x[n-N+1]]T

Thay kt qu t (4.27) vo (4.22) ta c:
w[n+1] = w[n] + 2e[n]x[n]
(4.28)
y l phng trnh truy hi xc nh tp trng s ca mch lc i vi cc

dy li vo v dy sai s. N c gi l thut ton LMS qui, thch nghi mt cch
quy cc h s ca mch lc c sau mi mu mi ca tn hiu li vo x[n] v mu tn
hiu mong mun d[n]. Cc phng trnh (4.20), (4.21), (4.28), theo th t l ba bc
hon chnh mi mt php lp ca thut ton LMS. Phng trnh (4.20) l qu trnh
lc, n c to thnh thu c tn hiu li ra ca mch lc. Phng trnh (4.21)
c s dng tnh sai s. Cn phng trnh (4.28) dng thch nghi mt cch
quy tp trng s ca mch lc sao cho sai s xc nh t gi tr cc tiu. Trong
phng trnh ny, l thng s bc, n iu khin tc hi t ca thut ton ti
nghim ti u. Nu chn ln th tc hi t nhanh; cn nu chn gi tr b th tc
hi t s chm hn. Tuy nhin, nu qu ln th thut ton s khng n nh v do
vy m bo tnh cht n nh ca thut ton LMS, phi c chn sao cho:
0<<
1
3trace[ R ]
(4.29)
trong : trace[R] =
N 1
[ k ]
, Vi N l bc ca b lc
k =0
------------------------------
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Chng 4
H THNG S B HAI V CC PHP TON
4.1. BIU DIN S M TRONG H THNG S B HAI
Trong h thng s b hai, s dng vn c biu din nh cc s khng du
khc. Do vy, ta ch tm hiu cch biu din s m trong h thng s b 2.
Gi s P l s dng, c biu din bi n bit trong s b hai, khi :
-P = K = 2n P.
V d: nu ta s dng s 4 bit biu din th +5 =0101 v -5 = 100000101=1011 v -3=10000-0011=1101
Vic tm s b hai nh cch trn thng t c s dng, do s phc tp ca n
khi phi s dng cc php tnh. V th, ta a ra mt phng php khc d dng hn:
Gi s s B = bn-1 bn-2b1 bo v K = kn-1 kn-2k1 ko l s b hai ca B.
Khi , s K c th c to ra t B bng cch : gi nguyn cc s bng 0 t
phi sang tri ca B cho n s u tin bng 1 ca B;cc s tip theo ca B s c
o ngc li(1 thnh 0 v 0 thnh 1).
V d: B=0110, khi k0=b0 =0 v k1=b1=1, cc s cn li thu c B bng vic
o cc bit tng ng : k2=0 v k3 = 1. Kt qu l: K=1010 l s b hai ca B=0110
Hnh di biu din s b hai 4 bit
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Hnh 13:S b hai c biu din bi 4 bit
Cc s c biu din trong h thng s b hai c biu din bi cng thc:

B=(-bn-1 x 2n-1) + bn-2 x 2n-2 +.+ b1 x 21 + bo
Trong B = bn-1 bn-2b1 bo l s n bit c biu din trong h thng s b hai.
4.2. THC HIN CC PHP TNH TRONG H THNG S B HAI

4.2.1. Thc hin php cng trong h thng s b hai
Thc hin php cng trong s b hai ht sc n gin, nh cng s nh phn
thng thng. Ta xt mt vi v d v vic thc hin php cng vi cc s b hai 4 bit:
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Lu : vi php cng:(+5)+(-2)=(+3) v (-5)+(-2)=(-7) th trong trng hp ny

ta c th b qua bit th 5
4.2.2. Thc hin php tr trong h thng s b hai
thc hin php tr trong s b hai, ta ch vic tm s b hai ca s b tr ri
thc hin php cng vi s tr.Ta xt cc v d sau:
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Lu : vi v d (+5)-(+2) =(+3) v (-5)-(+2)=(-7) ta c th b qua bit th 5.

4.2.3. Hin tng trn s
Nu dng n bit biu din s c du th ta c th biu din cc s trong khong
t --2n-1 n 2n-1 1. Nu sau qu trnh thc hin php ton(cng, tr, nhn) m kt
qu thu c khng nm trong di trn th ta ni c hin tng trn s.
Ta xt cc v d sau:
Trong v d trn, ta thy: (+7)+(+2) = (+9) v (-7)+(-2) = (-9) c kt qu b trn

do (+9) v (-9) khng c trong di biu din s c du 4 bit(t -8 n 7). Cc kt qu
cn li khng trn do vn nm trong di biu din.
Ngoi ra, c mt cch khc nhn bit c kt qu c trn hay khng m khng
cn quan tm n di biu din l:
Overflow = c3 xor c4
Nu dng n bit biu din s c du th ta c:
Overflow = cn xor cn-1
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4.2.4. Thc hin php nhn trong s b hai

Trc khi tho lun v php nhn hai s b hai, ta cn phi bit v php nhn vi
lu tha ca 2.
Gi s B=bn-1bn-2b1bo. Khi : 2 x B = bn-1bn-2b1bo0.
Ta ch vic dch B sang tri 1 s ri thm 1 s 0 vo cui.
Tng qut hn, nu ta thc hin php nhn: 2k x B th ta ch vic dch B sang tri
k s ri thm k s 0 vo cui.
Ta thy php nhn ca s c du vi lu tha ca 2 ging nh ca s khng du.
Tuy nhin, vi php chia th li khc hn. chia s B cho 2k, ta dch s B sang phi k
s(tc l b i k s cui). Sau , ta thm vo trc s B k bit du(bit du l bit c
trng s cao nht).
V d:
B = 011000 = (24)10 , B:2 = 001100 = (12)10, v B:4= 000110 =(6)10
Tng t vi s m: B=101000=(-24)10 , B:2= 110100 =(-12)10
Nh vy, ta bit cch thc hin php nhn v chia ca s b hai vi lu thu
ca 2. By gi ta tho lun xem cch nhn 2 s b hai c thc hin nh th no.
Ta xt hai v d sau:
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T 2 v d trn, ta rt ra c cch nhn 2 s b hai n bit A=an-1an-2 a1ao v

B=bn-1bn-2....b1bo tng t nh trn.
---------------------------------
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Chng 5
THC NGHIM
5.1. M T PHN CNG CA KIT VIRTEX-II PRO
Phn cng ca kit Virtex-II Pro bao gm:
FPGA Spartan-II dng to giao tip PCI hoc USB
2 LED trng thi hin th 3 mu:cam, , vng
Gic cm cho mch np JTAG
2 knh ADC c lp(ADC 14 bit) vi tc ly mu ti a l 105Mhz
2 knh DAC c lp(DAC 14 bit) vi tc bin i ti a l 160Mhz
2 rnh ZBT SRAM c lp vi b nh 512K x 32
FPGA virtex-II XC2V80-4CS144 to clock
FPGA virtex-II pro XC2VP30-4FF1152 l FPGA chnh cho ngi s dng
C ng kt ni vi clock ngoi
C thch anh 65Mhz trong mch
Tng th v kit virtex-II Pro c m t nh hnh 14:
Hnh 14: Ton b mt trn ca Kit virtex-II pro
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5.2. KT QU THU C VI B LC FIR TRUYN THNG

Lu tin hnh thc hin b lc FIR truyn thng nh hnh 15:
Dao ng k
My
pht
ADC
FPGA
DAC
Hnh 15: Lu thc hin b lc FIR truyn thng
Sau khi qua bin i ADC, d liu c biu din di dng s b hai s c
a vo FPGA x l. FPGA c nhim v thc hin thut ton lc theo yu cu ca
ngi lp trnh. S thc hin thut ton i vi b lc FIR c trnh by nh trong
hnh 3 ca chng 2. Trong , li vo x[n] ca b lc chnh l cc gi tr sau khi qua
bin i ADC, cc h s h[n] l cc hng s c cho trc(c tnh ton bng
Matlab) v y[n] l kt qu sau khi qua b lc FIR. Cc kt qu ny cng c biu
din di dng s b hai v c a qua b bin i DAC hin ln trn dao ng
k.
Trong bi lun vn ny, em thit k b lc FIR thng thp, vi bc b lc l 50,
tn s m b lc bt u suy gim v trit tiu l t 800Hz n 1250Hz, tn s ly
mu l 20Khz.
Cc h s h[n] s c tnh ton bng cng c fdatool trong Matlab. p ng tn
s tnh ton bng Matlab c m t nh hnh 16:
Hnh 16: p ng tn s ca mch lc FIR
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Kt qu thu c khi thc hin trn chp FPGA:

Tn hiu bt u suy gim ti tn s 700Mhz, c cho bi hnh 17:
Hnh 17: Tn hiu bt u suy gim
Tn hiu b trit tiu ti tn s 1237Hz, c cho bi hnh 18:
Hnh 18: Tn hiu b trit tiu
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5.3. KT QU THU C VI B LC FIR THEO KIN TRC SYSTOLIC

Vi b lc FIR thc hin theo kin trc systolic array, lu v kt qu t c
cng tng t nh vi b lc FIR thng thng. Tuy nhin, tc thc hin li nhanh
hn nhiu. Vi cng c place and route tools ca phn mm ISE, cho ta kt qu nh
sau:
Vi b lc FIR thc hin theo kin trc systolic array, tn s hot ng ln nht
ca mch l 141.947 Mhz v s dng ht 1775 slice.
Vi b lc FIR truyn thng, tn s hot ng ca ln nht ca mch l 19.857
Mhz v s dng ht 417 slice.
Nh vy, ta c th thy b lc FIR thc hin theo kin trc systolic array c tc p
ng nhanh hn nhiu so vi b lc FIR thng thng, tuy nhin, n li tn nhiu ti
nguyn hn. Do , tu theo tng ng dng c th m ta chn thit k theo phng
php no
5.4. KT QU THU C VI B LC FIR THCH NGHI

B lc FIR thch nghi c rt nhiu ng dng nh: Kh nhiu, nhn dng h thng
cha bit, d bo kt qu vi h thng c tn hiu vo l ngu nhin.
Trong bi lun vn ny, em xin trnh by v ng dng ca b lc FIR thch nghi
kh nhiu 50Hz-l nhiu do ngun sinh ra. y l loi nhiu ph bin v gy nh
hng ln n cc thit b in t.
Lu cho vic kh nhiu 50HZ c m t nh hnh 19:
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d(n) = s(n)+v(n)
+
v1(n)
v(n) __
FIR
e(n)
output
LMS
Hnh 19: M hnh kh nhiu 50 Hz
Trong :
s(n) l tn hiu mong mun

v(n) l tn hiu nhiu
v1(n) l tn hiu cng dng vi v(n)(c th khc nhau v bin v pha)
v(n) u ra ca b lc FIR thch nghi
e(n) l tn hiu sai s, ng thi l li ra.
Thut ton LMS s c nhim v iu chnh cc h s ca b lc FIR sao cho li

ra v(n) c dng gn nht vi tn hiu nhiu v(n). Khi , e(n)=d(n) - v(n) s t n
tn hiu mong mun s(n). Tc l ta kh c nhiu.
Kt qu thu c khi tin hnh trn chip FPGA:
Tn hiu ln vi nhiu 50Hz trc khi lc, c cho bi hnh 20
Hnh 20: Tn hiu ln vi nhiu
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Tn hiu sau khi lc c cho bi hnh 21
Hnh 21: Tn hiu thu c sau khi lc
Tn hiu thu c sau khi qua b lc FIR thch nghi loi b c nhiu 50Hz.
Tuy nhin, vn khng c trn tru v c mp m nh. S d nh vy l do cc
nguyn nhn sau:
Do b bin i ADC l 14 bit, nn khi qua b lc FIR(bao gm cc b nhn v
b cng) th d liu ln ti 28 bit, m u ra DAC ch h tr 14 bit, v vy,
trc khi d liu c a vo b lc FIR, ta phi chia d liu cho 27 u ra
DAC l 14 bit. Do , kt qu c sai s nht nh
B bin i DAC ch h tr cc s nguyn, do , ta phi lm trn cc h s
thnh s nguyn, v vy, kt qu t c cng khng c nh l thuyt
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KT LUN
Trong thi gian tin hnh hon thin kho lun tt nghip, ngoi vic cng c li
nhng kin thc c hc trong sut 4 nm qua, em cn thu c mt s kin thc
v kt qu nht nh:
c tm hiu v thc hnh trn chip FPGA ca hng Xilinx
Bit s dng thnh tho phn mm ISE
C thm nhiu kinh nghim trong vic lp trnh vi ngn ng VHDL
Thc hin thnh cng b lc FIR thng thp trn FPGA theo kin trc
truyn thng v theo kin trc systolic array. So snh c u im,
nhc im ca tng loi
Thc hin thnh cng b lc FIR thch nghi dng thut ton LMS trn
FPGA loi b nhiu 50 Hz
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TI LIU THAM KHO

[1] Simon Haykin. Adaptive filter theory, Third edition
[2] Uwe Meyer-Baese.Digital Signal Processing with Field Programmable Gate
Arrays, Third Edition
[3] John G.Proaskis,Dimitris G.Manolakis. Digital Signal Processing, Third edition
[4] Alexander D.Poularikas, Zayed M.Ramanda. Adaptive filtering primer with matlab,
2006.
[5] Douglas L.Perry. VHDL: Programming by Example .McGraw Hill, Fourth
Edition
[6]. Volnei A.Pedroni, Circuit Design With VHDL, MIT Press, 2004
[7] Jan Van der Spiegel. VHDL tutorial
[8] Nguyn Kim Giao, K thut in t s, Nh xut bn i hc Quc gia H Ni,
2006.
[9]. Tng Vn On, Thit k mch s vi VHDL v Verilog, Nh xut bn lao ng x
hi, 2007.
[10] H Vn Sung. X l s tn hiu a tc v dn lc, Nh xut bn KH-KT, 2007
[11] http://en.wikipedia.org
[12] http://www.xilinx.com
[13] http://www.fpga4fun.com
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PH LC
PHN CHNG TRNH

1. Chng trnh thit k b lc FIR theo kin trc truyn thng
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Toplevel is
port (
-- main clock input from oscilator
CLK1_FB
: in std_logic;
-- main reset input from mb
RESETl
: in std_logic;
-- configuration done signal
CONFIG_DONE : out std_logic;
-- dac 14 bit data outputs
DAC1_D
: out std_logic_vector(13 downto 0);
DAC2_D
-- adc 14 bit data inputs
ADC1_D
: in std_logic_vector(13 downto 0);
ADC2_D
-- dac reset signals
DAC1_RESET : out std_logic;
-- dac setup
DAC1_MOD0
: out std_logic;
DAC1_MOD1
: out std_logic;
DAC2_MOD0
: out std_logic;
DAC2_MOD1
: out std_logic;
-- dac clock divider setup
DAC1_DIV0
: out std_logic;
DAC1_DIV1
: out std_logic;
DAC2_DIV0
: out std_logic;
DAC2_DIV1
: out std_logic;
-- led flash signals
LED1_Red
: out std_logic;
LED2_Red
: out std_logic;
LED1_Green : out std_logic;
LED2_Green : out std_logic
);
end Toplevel;
architecture Behavioral of Toplevel is
-- clock components
component BUFG
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port (
I : in std_logic;
O : out std_logic
);
end component;
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
component DCM
generic (
DLL_FREQUENCY_MODE
: string :=
DUTY_CYCLE_CORRECTION : string :=
STARTUP_WAIT
: string :=
);
port (
CLKIN
: in std_logic;
CLKFB
: in std_logic;
DSSEN
: in std_logic;
PSINCDEC : in std_logic;
PSEN
: in std_logic;
PSCLK
: in std_logic;
RST
: in std_logic;
CLK0
: out std_logic;
CLK90
: out std_logic;
CLK180
: out std_logic;
CLK270
: out std_logic;
CLK2X
: out std_logic;
CLK2X180 : out std_logic;
CLKDV
: out std_logic;
CLKFX
: out std_logic;
CLKFX180 : out std_logic;
LOCKED
: out std_logic;
PSDONE
: out std_logic;
STATUS
: out std_logic_vector(7
);
end component;
-- end of clock components
"LOW";
"TRUE";
"FALSE"
downto 0)
-- internal clock and reset signals

Component FIR_Filter
Generic(n: integer :=14; -- width of data
m: integer := 51); -- order of FIR
Port (
Xin: in std_logic_vector(n-1 downto 0);
clk,reset: in std_logic;
Yout: out std_logic_vector(n-1 downto 0)
);
end Component;
component chiatan
port
clk_i :
in
std_logic;
sochia
clk_o :
:
in
integer;
out std_logic
);
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end component;
signal CLKIN_OSC, CLKFB_OSC, CLK_OSC, RESET, RSTl : std_logic;
-- temporary registers
signal ADC1, ADC2 : std_logic_vector(13 downto 0);
signal DAC1
:std_logic_vector(13 downto 0);
signal data
-- common ground
signal GND : std_logic;
signal clk:std_logic;
begin
GND <= '0';
RESET <= not RESETl;
-----------------------------clock deskew section----------------------------- IBUFG Instantiation for CLK_IN
U0_IBUFG : IBUFG
port map (
I => CLK1_FB,
O => CLKIN_OSC
);
-- BUFG Instantiation for CLKFB
U0_BUFG : BUFG
port map (
I => CLKFB_OSC,
O => CLK_OSC
);
-- DCM Instantiation for internal deskew of CLK0
U0_DCM : DCM
port map (
CLKIN
=> CLKIN_OSC,
CLKFB
=> CLK_OSC,
DSSEN
=> GND,
PSINCDEC => GND,
PSEN
=> GND,
PSCLK
=> GND,
RST
=> RESET,
CLK0
=> CLKFB_OSC,
LOCKED
=> RSTl
);
-----------------------------end of clock deskew----------------------------- module configured
CONFIG_DONE <= '0';
-- set low pass filter response and no zero stuffing for both DACs
DAC1_MOD0 <= '0';
DAC1_MOD1 <= '0';
DAC2_MOD0 <= '0';
DAC2_MOD1 <= '0';
-- disable resets for DACs
DAC1_RESET <= '0';
DAC2_RESET <= '0';
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-- optimum settings for sampling rate

DAC1_DIV0 <= '1';
DAC1_DIV1 <= '0';
DAC2_DIV0 <= '1';
DAC2_DIV1 <= '0';
-- digital output of adc to digital input of DAC
U0: chiatan port map(CLK_OSC,5250,clk);
DataRegisters : process (clk,RSTl)
begin
if RSTl = '0' then
ADC1
<= "00000000000000";
ADC2
<= "00000000000000";
DAC1_D <= "00000000000000";
DAC2_D <= "00000000000000";
elsif clk = '1' and clk'event then
--ADC1
<= ADC1_D;
--ADC2
<= ADC2_D;
if(ADC1_D(13)='1') then
ADC1<="1111111"&ADC1_D(13 downto 7);
else
ADC1<="0000000"&ADC1_D(13 downto 7);
end if;
DAC1_D <= not (not DAC1(13) & DAC1(12 downto 0));
--DAC2_D <= not (not ADC2(13) & ADC2(12 downto 0));
end if;
end process;
thuchien:FIR_Filter port map (ADC1(13 downto 0),clk,RSTl,DAC1);

-----------------------------led flasher section----------------------------- led flash counter
process (CLK_OSC, RSTl)
variable COUNT : std_logic_vector(26 downto 0);
begin
if RSTl = '0' then
COUNT
:= (others => '0');
-- led assignments
LED1_Red
<= '0';
LED2_Red
<= '0';
LED1_Green <= '0';
LED2_Green <= '0';
elsif CLK_OSC = '1' and CLK_OSC'event then
COUNT
:= COUNT + 1;
-- led assignments
LED1_Red
<= COUNT(26);
LED2_Red
<= COUNT(25);
LED1_Green <= COUNT(25);
end if;
end process;
-----------------------------end of led flasher---------------------------end Behavioral;
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Library ieee;
Use ieee.std_logic_1164.all;
Entity FIR_Filter is
Port (
);
end FIR_FIlTER;
architecture arch_FIR of FIR_FILTER is
Component FF_D
Generic(n: integer :=14);
Port (
D :in std_logic_vector(n-1 downto 0);
Clk,Reset: in std_logic;
--enable: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end Component;
component PE is
Port (
Xin,Ain: in std_logic_vector(n-1 downto 0);
Yin: in std_logic_vector(n-1 downto 0);
clk,reset : in std_logic;
Xout: inout std_logic_vector(n-1 downto 0);
);
end component;
type A_cof is array(natural range m-1 downto 0) of std_logic_vector(n-1

downto 0);
type Y_cof is array(natural range m-1 downto 0) of std_logic_vector(n-1
downto 0);
constant Ain : A_cof :=
("00000000000001","00000000000001","00000000000001","00000000000001","00000
000000001","00000000000000","00000000000000","11111111111111","111111111111
11","11111111111110","11111111111110","11111111111110","11111111111110","11
111111111110","11111111111111","00000000000000","00000000000001","000000000
00010","00000000000100","00000000000101","00000000000110","00000000001000",
"00000000001001","00000000001010","00000000001010","00000000001010","000000
00001010","00000000001010","00000000001001","00000000001000","0000000000011
0","00000000000101","00000000000100","00000000000010","00000000000001","000
00000000000","11111111111111","11111111111110","11111111111110","1111111111
1110","11111111111110","11111111111110","11111111111111","11111111111111","
00000000000000","00000000000000","00000000000001","00000000000001","0000000
0000001","00000000000001","00000000000001");
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signal Xout: std_logic_vector(n-1 downto 0);

signal Ytin,Ytout: std_logic_vector(n-1 downto 0);
signal X: a_cof;
signal Y: Y_cof;
begin
Y(m-1) <="00000000000000"; -- (others => '0');
PE_for:
for i in 0 to m-2 generate
-- Concurrent Statement(s)
PE1: PE port map (X(m-2-i),Ain(i),Y(m-1-i),clk,reset,X(m-1i),Y(m-2-i));
end generate;
PE2: PE port map (Xin,Ain(m-1),Y(0),clk,reset,X(0),Ytout);
REGST1: FF_D port map (ytout,clk,reset,Yout);
--REGST2: FF_D port map (Ytout,clk,reset,Yout);
end arch_FIR;
-----------Library ieee;
Entity PE is
Port (
);
end PE;
architecture arch_PE of PE is
Component adder
PORT
(
dataa
: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
datab
result
: OUT STD_LOGIC_VECTOR (13 DOWNTO 0)
);
END Component;
Component mult
PORT
(
dataa
datab
result
);
END Component;
-- Declarations (optional)
Component FF_D
Port (
--Enable: in std_logic;
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);
end Component;
signal S1,S2,S3: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
signal rmul: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
begin
REGX: FF_D
generic map (n => 14)
port map (Xin,clk,reset,Xout);
Multi: mult port map (xout,ain,rmul);
--REGS0: FF_D port map (s1,clk,reset,rmul);
adderS: adder port map (rmul,Yin,Yout);
--REGS1: FF_D port map (S2,clk,reset,S3);
--REGS2: FF_D port map (S3,clk,reset,Yout);
end arch_PE;
Entity FF_D is
Port (
);
end FF_D;
architecture arch_FFD of FF_D is
Begin
Process (clk,reset)
begin
if clk'event and clk = '1' then
--if enable = '1' then
if reset = '0' then
Q <= (others =>'0');
else
Q <= D;
end if;
--end if;
end if;
end process;
end arch_FFD;
-------------------------------library IEEE;
use IEEE.STD_LOGIC_SIGNED.all;
entity mult is
PORT
(
dataa
datab
result
);
END mult;
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architecture run_mult of mult is

begin
result <= dataa*datab;
--result(13)<= dataa(7) xor datab(7);
end run_mult;
------------------------------------------------------------library IEEE;
entity adder is
PORT
(
dataa
datab
result
);
END adder;

architecture run_add of adder is

begin
result<=dataa+datab;
end run_add;
-------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity chiatan is
port( clk_i
sochia
clk_o
:
:
:
in
std_logic;
in
integer;
out std_logic
);
end chiatan;
architecture run_chia of chiatan is
begin
process(clk_i)
variable i
: integer range 0 to 50001 :=0;
variable j
variable temp
: std_logic:='1';
begin
j:=sochia/2;
if(clk_i'event and clk_i='1') then
i:=i+1;
if(i>=j) then i:=0;temp:=not(temp);--;j:=j+1;
--if(j>=sochia) then j:=0; temp:=not(temp);
end if;
end if;
--end if;
clk_o<=temp;
end process;
end run_chia;
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2. Chng trnh thit k b lc FIR theo kin trc systolic array

library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity Toplevel is
port (
CLK1_FB
: in std_logic;
RESETl
: in std_logic;
DAC1_D
DAC2_D
ADC1_D
ADC2_D
-- dac setup
DAC1_MOD0
: out std_logic;
DAC1_MOD1
: out std_logic;
DAC2_MOD0
: out std_logic;
DAC2_MOD1
: out std_logic;
DAC1_DIV0
: out std_logic;
DAC1_DIV1
: out std_logic;
DAC2_DIV0
: out std_logic;
DAC2_DIV1
: out std_logic;
LED1_Red
: out std_logic;
LED2_Red
: out std_logic;
);
end Toplevel;
-- clock components
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
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component DCM
generic (
DLL_FREQUENCY_MODE
: string :=
DUTY_CYCLE_CORRECTION : string :=
STARTUP_WAIT
: string :=
);
port (
CLKIN
: in std_logic;
CLKFB
: in std_logic;
DSSEN
: in std_logic;
PSEN
: in std_logic;
PSCLK
: in std_logic;
RST
: in std_logic;
CLK0
: out std_logic;
CLK90
: out std_logic;
CLK180
: out std_logic;
CLK270
: out std_logic;
CLK2X
: out std_logic;
CLKDV
: out std_logic;
CLKFX
: out std_logic;
LOCKED
: out std_logic;
PSDONE
: out std_logic;
STATUS
: out std_logic_vector(7
);
end component;
"LOW";
"TRUE";
"FALSE"
downto 0)

Component FIR_Filter
Port (
);
end Component;
component chiatan
port( clk_i :
in
sochia
clk_o :
);
std_logic;
:
in
integer;
out std_logic
end component;
signal DAC1
signal DAC2
signal data
-- common ground
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begin
GND <= '0';
U0_IBUFG : IBUFG
port map (
I => CLK1_FB,
O => CLKIN_OSC
);
U0_BUFG : BUFG
port map (
I => CLKFB_OSC,
O => CLK_OSC
);
U0_DCM : DCM
port map (
CLKIN
=> CLKIN_OSC,
CLKFB
=> CLK_OSC,
DSSEN
=> GND,
PSINCDEC => GND,
PSEN
=> GND,
PSCLK
=> GND,
RST
=> RESET,
CLK0
=> CLKFB_OSC,
LOCKED
=> RSTl
);
CONFIG_DONE <= '0';
DAC1_MOD0 <= '0';
DAC1_MOD1 <= '0';
DAC2_MOD0 <= '0';
DAC2_MOD1 <= '0';
DAC1_RESET <= '0';
DAC2_RESET <= '0';
DAC1_DIV0 <= '1';
DAC1_DIV1 <= '0';
DAC2_DIV0 <= '1';
DAC2_DIV1 <= '0';
U0: chiatan port map(CLK_OSC,5250,clk);
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begin
if RSTl = '0' then
ADC1
<= "00000000000000";
ADC2
<= "00000000000000";
DAC1_D <= "00000000000000";
DAC2_D <= "00000000000000";
--ADC1
<= ADC1_D;
--ADC2
<= ADC2_D;
if(ADC1_D(13)='1') then
ADC1<="1111111"&ADC1_D(13 downto 7);
else
ADC1<="0000000"&ADC1_D(13 downto 7);
end if;
DAC2<=ADC1_D;
end if;
end process;
thuchien:FIR_Filter port map (ADC1(13 downto 0),clk,RSTl,DAC1);

begin
if RSTl = '0' then
COUNT
:= (others => '0');
-- led assignments
LED1_Red
<= '0';
LED2_Red
<= '0';
LED1_Green <= '0';
LED2_Green <= '0';
COUNT
:= COUNT + 1;
-- led assignments
LED1_Red
<= COUNT(26);
LED2_Red
<= COUNT(25);
end if;
end process;
-----------------------------end of led flasher---------------------------end Behavioral;
Library ieee;
Entity FIR_Filter is
Port (
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);
end FIR_FIlTER;
architecture arch_FIR of FIR_FILTER is
Component FF_D
Port (
--enable: in std_logic;
);
end Component;
component PE is
Port (
);
end component;
type A_cof is array(natural range m-1 downto 0) of std_logic_vector(n-1

downto 0);
type Y_cof is array(natural range m-1 downto 0) of std_logic_vector(n-1
downto 0);
constant Ain : A_cof :=
("00000000000001","00000000000001","00000000000001","00000000000001","00000
000000001","00000000000000","00000000000000","11111111111111","111111111111
11","11111111111110","11111111111110","11111111111110","11111111111110","11
111111111110","11111111111111","00000000000000","00000000000001","000000000
00010","00000000000100","00000000000101","00000000000110","00000000001000",
"00000000001001","00000000001010","00000000001010","00000000001010","000000
00001010","00000000001010","00000000001001","00000000001000","0000000000011
0","00000000000101","00000000000100","00000000000010","00000000000001","000
00000000000","11111111111111","11111111111110","11111111111110","1111111111
1110","11111111111110","11111111111110","11111111111111","11111111111111","
00000000000000","00000000000000","00000000000001","00000000000001","0000000
0000001","00000000000001","00000000000001");
signal Xout: std_logic_vector(n-1 downto 0);
signal Ytin,Ytout: std_logic_vector(n-1 downto 0);
signal X: a_cof;
signal Y: Y_cof;
begin
X(0) <= Xin;
Y(0) <= (others => '0');
PE_for:
for i in 0 to m-2 generate
-- Concurrent Statement(s)
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PE1: PE port map (X(i),Ain(i),Y(i),clk,reset,X(i+1),Y(i+1));

end generate;
PE2: PE port map (X(49),Ain(49),Y(49),clk,reset,Xout,Yout);
end arch_FIR;
------------
Library ieee;
Entity PE is
Port (
);
end PE;
architecture arch_PE of PE is
Component adder
PORT
(
dataa
datab
result
);
END Component;
Component mult
PORT
(
dataa
datab
result
);
END Component;
-- Declarations (optional)
Component FF_D
Port (
);
end Component;
signal S1,S2,S3: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
signal rmul: STD_LOGIC_VECTOR (n-1 DOWNTO 0);
begin
REGX: FF_D
generic map (n => 14)
port map (Xin,clk,reset,Xout);
Multi: mult port map (xout,ain,rmul);
--REGS0: FF_D port map (s1,clk,reset,rmul);
adderS: adder port map (rmul,Yin,S2);
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REGS1: FF_D port map (S2,clk,reset,S3);

REGS2: FF_D port map (S3,clk,reset,Yout);
end arch_PE;
Entity FF_D is
Port (
);
end FF_D;
architecture arch_FFD of FF_D is
Begin
Process (clk,reset)
begin
if clk'event and clk = '1' then
--if enable = '1' then
if reset = '0' then
Q <= (others =>'0');
else
Q <= D;
end if;
--end if;
end if;
end process;
end arch_FFD;
-------------------------------library IEEE;
entity mult is
PORT
(
dataa
datab
result
);
END mult;
begin
end run_mult;
------------------------------------------------------------library IEEE;
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entity adder is
PORT
(
dataa
datab
result
);
END adder;
Kho lun tt nghip


begin
end run_add;
-------------------------------------------library ieee;
entity chiatan is
port( clk_i :
in
std_logic;
sochia
:
in
integer;
clk_o :
out std_logic
);
end chiatan;
begin
process(clk_i)
variable i
variable j
variable temp
: std_logic:='1';
begin
j:=sochia/2;
i:=i+1;
end if;
end if;
--end if;
clk_o<=temp;
end process;
end run_chia;
----------------------------------------------------
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3. Chng trnh thit k b lc FIR thch nghi dng thut ton LMS
library IEEE;
entity Toplevel is
port (
CLK1_FB
: in std_logic;
RESETl
: in std_logic;
DAC1_D
DAC2_D
ADC1_D
ADC2_D
-- dac setup
DAC1_MOD0
: out std_logic;
DAC1_MOD1
: out std_logic;
DAC2_MOD0
: out std_logic;
DAC2_MOD1
: out std_logic;
DAC1_DIV0
: out std_logic;
DAC1_DIV1
: out std_logic;
DAC2_DIV0
: out std_logic;
DAC2_DIV1
: out std_logic;
LED1_Red
: out std_logic;
LED2_Red
: out std_logic;
);
end Toplevel;
-- clock components
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
component DCM
generic (
DLL_FREQUENCY_MODE
: string := "LOW";
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DUTY_CYCLE_CORRECTION : string := "TRUE";

STARTUP_WAIT
: string := "FALSE"
);
port (
CLKIN
: in std_logic;
CLKFB
: in std_logic;
DSSEN
: in std_logic;
PSEN
: in std_logic;
PSCLK
: in std_logic;
RST
: in std_logic;
CLK0
: out std_logic;
CLK90
: out std_logic;
CLK180
: out std_logic;
CLK270
: out std_logic;
CLK2X
: out std_logic;
CLKDV
: out std_logic;
CLKFX
: out std_logic;
LOCKED
: out std_logic;
PSDONE
: out std_logic;
STATUS
: out std_logic_vector(7 downto 0)
);
end component;
component fir_lms IS ------> Interface
GENERIC (W1 : INTEGER := 8; -- Input bit width
W2 : INTEGER := 16; -- Multiplier bit width 2*W1
L : INTEGER := 2 -- Filter length
);
PORT ( clk : IN STD_LOGIC;
x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
d_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
e_out : OUT STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
y_out :OUT STD_LOGIC_VECTOR(W2-1 DOWNTO 0)
);
END component;
component chiatan
port( clk_i
sochia
clk_o
);
:
:
:
in
std_logic;
in
integer;
out std_logic
end component;
signal DAC1
signal DAC2
signal data
-- common ground
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signal e,y:
Kho lun tt nghip
std_logic_vector(15 downto 0);
begin
GND <= '0';
U0_IBUFG : IBUFG
port map (
I => CLK1_FB,
O => CLKIN_OSC
);
U0_BUFG : BUFG
port map (
I => CLKFB_OSC,
O => CLK_OSC
);
U0_DCM : DCM
port map (
CLKIN
=> CLKIN_OSC,
CLKFB
=> CLK_OSC,
DSSEN
=> GND,
PSINCDEC => GND,
PSEN
=> GND,
PSCLK
=> GND,
RST
=> RESET,
CLK0
=> CLKFB_OSC,
LOCKED
=> RSTl
);
CONFIG_DONE <= '0';
DAC1_MOD0 <= '0';
DAC1_MOD1 <= '1';
DAC2_MOD0 <= '0';
DAC2_MOD1 <= '0';
DAC1_RESET <= '0';
DAC2_RESET <= '0';
DAC1_DIV0 <= '0';
DAC1_DIV1 <= '1';
DAC2_DIV0 <= '1';
DAC2_DIV1 <= '0';
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U0:
Kho lun tt nghip
chiatan port map(CLK_OSC,5000,clk);

begin
if RSTl = '0' then
--e
<= "0000000000000000";
--y
<= "0000000000000000";
DAC1_D <= "00000000000000";
DAC2_D <= "00000000000000";
ADC1<=ADC1_D(13 downto 6);--tin hieu+nhieu

ADC2<=ADC2_D(13 downto 6);--nhieu
DAC1_D <= e(15) &not(e(14 downto 2));--loc
DAC2_D <= ADC1_D(13) & not (ADC1_D(12 downto 0));--tin hieu +nhieu
end if;
end process;
thuchien:FIR_LMS port map (clk,ADC2,ADC1,e,y);

begin
if RSTl = '0' then
COUNT
:= (others => '0');
-- led assignments
LED1_Red
<= '0';
LED2_Red
<= '0';
LED1_Green <= '0';
LED2_Green <= '0';
COUNT
:= COUNT + 1;
-- led assignments
LED1_Red
<= COUNT(26);
LED2_Red
<= COUNT(25);
end if;
end process;
end Behavioral;
-----------------------------end of led flasher----------------------------- This is a generic LMS FIR filter generator
-- It uses W1 bit data/coefficients bits
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY fir_lms IS ------> Interface
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GENERIC (W1 : INTEGER := 8; -- Input bit width

W2 : INTEGER := 16; -- Multiplier bit width 2*W1
L : INTEGER := 2 -- Filter length
);
PORT ( clk : IN STD_LOGIC;
x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
d_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);
e_out : OUT STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
y_out :OUT STD_LOGIC_VECTOR(W2-1 DOWNTO 0)
);
END fir_lms;
ARCHITECTURE fpga OF fir_lms IS
component mult is
PORT
(
dataa
datab
result
);
END component;

SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0);

SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0);
TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT;
TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT;
SIGNAL d : N1BIT;
SIGNAL emu : N1BIT;
SIGNAL y, sxty : N2BIT;
SIGNAL e, sxtd : N2BIT;
SIGNAL x, f : ARRAY_N1BIT; -- Coeff/Data arrays
SIGNAL p, xemu : ARRAY_N2BIT; -- Product arrays
BEGIN
dsxt: PROCESS (d) -- 16 bit signed extension for input d
BEGIN
sxtd(7 DOWNTO 0) <= d;
FOR k IN 15 DOWNTO 8 LOOP
sxtd(k) <= d(d'high);
END LOOP;
END PROCESS;
Store: PROCESS ------> Store these data or coefficients
BEGIN
WAIT UNTIL clk = '1';
d <= d_in;
x(0) <= x_in;
x(1)<=x(0);
f(0) <= f(0) + xemu(0)(15 DOWNTO 8);
f(1) <= f(1) + xemu(1)(15 DOWNTO 8);
END PROCESS Store;

MulGen1: FOR I IN 0 TO L-1 GENERATE
FIR: mult PORT MAP ( x(I), f(I),p(I));
END GENERATE;
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y <=p(0)+p(1);
ysxt: PROCESS (y) -- Scale y by 128 because x is fraction

BEGIN
sxty(8 DOWNTO 0) <= y(15 DOWNTO 7);
FOR k IN 15 DOWNTO 9 LOOP
sxty(k) <= y(y'high);
END LOOP;
END PROCESS;
e <= sxtd - sxty;
emu <= e(8 DOWNTO 1); -- e*mu divide by 2 and
-- 2 from xemu makes mu=1/4
MulGen2: FOR I IN 0 TO L-1 GENERATE
FUPDATE: mult PORT MAP (x(I), emu,xemu(I));
END GENERATE;
y_out <= sxty; -- Monitor some test signals
e_out <= e;
END fpga;
library IEEE;
entity mult is
PORT
(
dataa
datab
result
);
END mult;
begin
end run_mult;
------------------------------------------------------------library IEEE;
entity adder is
PORT
(
dataa
datab
result
);
END adder;


begin
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end run_add;
-------------------------------------------library ieee;
entity chiatan is
port( clk_i :
in
std_logic;
sochia
:
in
integer;
clk_o :
out std_logic
);
end chiatan;
begin
process(clk_i)
variable i
variable j
variable temp
: std_logic:='1';
begin
j:=sochia/2;
i:=i+1;
end if;
end if;
--end if;
clk_o<=temp;
end process;
end run_chia;
65
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Thuc Hien Bo Loc FIR Thich Nghi Dung Thuat Toan LMS

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Thuc Hien Bo Loc FIR Thich Nghi Dung Thuat Toan LMS

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BNG K HIU VIT TT

Application Specific Integrated Circuit

Analog to Digital Converter

Arithmetic Logic Unit

Auto Senquencing Memory

Complex Programmable Logic Device

Central Processing Unit

Digital Signal Processing

Digital to Analog Converter

Data Processing Unit

Finite Impulse Response

Field Programmable Gate Array

Hardware Description Language

Institute of Electrical and Electronics Engineers

Joint Test Action Group

Light Emitting Diode

Least Mean Square

Programmable Array Logic

Programmable Logic Array

Peripheral Component Interconnect

Random Access Memory

Read Only Memory

Recommended Standard 232

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Static Random Access Memory

Simple Programable Logic Device

Universal Serial Bus

Very High Speed Itergrated Circuit

Very High Speed Itergrated Circuit

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1.1.2. Khi nim c bn v cu trc ca FPGA

Hnh 1: Kin trc tng quan ca FPGA

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Vi mch FPGA c cu thnh t cc b phn:

Hnh 2: Khi logic lp trnh c ca FPGA

Trong ti liu hng dn ca cc dng FPGA ca Xilinx cn s dng khi nim

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hiu s trong FPGA c tch hp cc DSP Slice l b nhn, cng tc cao,

1.2. TNG QUAN V NGN NG VHDL

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IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v

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