B CNG NGHIP TRNG I HC CNG NGHIP TP HCM KHOA CNG NGH IN T

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Ti:

LP TRNH C CHO H VI IU KHIN 8051

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PHN I

TNG QUAN v TI
I. T VN : Ngy nay, nhng ng dng ca Vi iu khin i su vo i sng sinh hot v sn xut ca con ngi. Thc t hin nay l hu ht cc thit b in dn dng hin nay u c s gp mt ca Vi iu Khin v vi x l . ng dng vi iu khin trong thit k h thng lm gim chi ph thit k v h gi thnh sn phm ng thi nng cao tnh n nh ca thit b v h thng.Trn th trng c rt nhiu h vi iu khin: h 8051 ca Intel, 68HC11 ca Motorola, Z80 ca hng Zilog, PIC ca hng Microchip, H8 ca Hitachi,vv Vic pht trin ng dng cc h vi x l i hi nhng hiu bit c v phn cng cng nh phn mm, nhng cng chnh v vy m cc h vi x l c s dng gii quyt nhng bi ton rt khc nhau. Tnh a dng ca cc ng dng ph thuc vo vic la chn cc h vi x l c th cng nh vo k thut lp trnh. Ngy nay cc b vi x l c mt trong rt nhiu thit b in t hin i: t u a CD, my thu hnh, my ghi hnh, dn m thanh HiFi, b iu khin l si cho n cc thit b iu khin dng trong cng nghip. Lnh vc ng dng ca cc h vi x l cng rt rng ln: t nguyn cu khoa hc, truyn d liu, n cng nghip, nng lng, giao thng v y t Ty theo kinh nghim v mc thng tho m chng ta c th s dng cc ngn ng khc ngoi hp ng nh: C, C++, Visual basic c nhng chng trnh cht lng cao hn.

II. NI DUNG CA TI:

S lc v vi iu khin AT89C51. Kho st vi iu khin AT89C2051 ca hng ATMEL. Gm s chn linh kin. S khi ca AT89C2051. Cc ni dng ng dng ca AT89C2051. Gii thiu phn mm Keil Software ViSion 2 ng dng ngn ng C v Assembly iu khin lp trnh led. ng dng cho led n, led 7 on, led ma trn Kt lun v hng pht trin ca ti.

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PHN II

NI DUNG TI
CHNG 1: GII THIU B VI IU KHIN 89C2051 v 89C51
I.GII THIU B VI IU KHIN 89C2051 I.1 CC C IM Tng thch vi cc sn phm ca h MSC-51. 2K byte b nh Flash lp trnh c. Kh nng :1000 chu k ghi/xa. Tm in p hot ng t 2,7 V n 6V Tm tn s hot ng t 0 Hz n 21 MHz 2 mc kha b nh chng trnh (program memory). RAM bn trong (internal RAM) c dung lng 128 x 8 bit. 15 ng I/O lp trnh c. 2 b nh thi /m 16 bit. 6 ngun (nguyn nhn ) ngt. Knh ni tip UART lp trnh c. Cc ng ra kch LED trc tip. Mch so snh tng t trn chip (on-chip analog comparator). Cc ch ngh cng sut thp v ch gim cng sut. I.2 M T Chip AT89C2051 l chip vi iu khin CMOS 8 bit in p thp, hiu sut cao c 2K byte b nh Flash ch c, xa c v lp trnh c PEROM (Flash programmable and erasable readonly memory). Linh kin ny c sn xut bng cch s dng cng ngh b nh khng thay i mt cao ca Atmel v tng thch vi tp tp ca MCS-51 chun cng nghip. Bng cch kt hp mt CPU 8-bit a nng v linh hot vi Flash trn chip n tinh th , Atmel AT89C2051 l chip vi iu khin mnh cung cp gii php linh ng cao v mang li hiu qu v gi thnh cho nhiu ng dng iu khin nhng (embedded control application). AT89C2051 cung cp cc c tnh chun sau y : b nh Flash 2K byte , 128 byte RAM , 15 ng I/O, 2 b nh thi/m 16-bit , kin trc ngt hai mc 5 vector, port ni tip hon ton song cng , mch so snh tng t chnh xc, mch dao ng v to xung clock trn chip . Ngoi ra AT89C2051 c thit k c mch logic tnh cho hot ng gim n tn s 0 Hz v h tr 2 ch tit kim cng sut la chn c bng phn mm. Ch d ngh ( idle mode ) s dng CPU nhng vn cho php RAM, cc b nh thi/m, port ni tip v h thng ngt tip tc hot ng. Ch gim cng sut duy tr ni dung ca RAM nhng lm dng mch dao ng, khng cho php mi chc nng khc ca chip hot ng cho n ln reset cng k tip (ngha l ta thit lp li trng thi ban u [reset] cho chiop bng mch in bn ngoi).

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I.3 CU HNH CHN

Hnh 1.1

I.4 S KHI

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Hnh 1.2 RAM ADDR. REGISTER: thanh ghi a ch RAM . RAM: vng nh truy cp ngu nhin (RAM). FLASH: vng nh FLASH. B REGISTER:thanh ghi B. ACC: thanh cha. STACK POINTER: con tr vng nh xp chng. PROGRAM ADDRESS REGISTER: thanh ghi a ch chng trnh. TMP1: thanh ghi tm 1 TMP2: thanh ghi tm 2 ALU: n v s hc/logic. BUFFER: b m. PC INCREMENTER: b tng thanh ghi m chng trnh PC. INTERRUPT, SERIAL PORT AND TIMER BLOCKS: cc khi ngt, port ni tip v nh thi. PROGRAM COUNTER: b m chng trnh PC. PSW: t trng thi chng trnh . TIMING AND CONTROL:mch logic iu khin v nh thi. INSTRUCTION REGISTERED: thanh ghi lnh. DPTR: con tr d liu . PORT1 LATCH: b cht port 1. PORT3 LATCH: b cht port 3. ANALOG COMPARTOR:b so snh tng t . OSC:mch dao ng. PORT 1 DRIVERS: cc mch kch port 1. PORT 3 DRIVERS: cc mch kch port 3. I.5 M T CHN VCC Chn cp in p Vcc cho chip. GND Chn ni t. Port 1 Port 1 l port I/O (port nhp/xut: input/output port) hai chiu 8-bit. Cc chn ca port t P1.2 n P1.7 cung cp cc mch ko ln bn trong (internal pull-ups). Cc chn P1.0 v P1.1 yu cu cc mch ko ln bn ngoi . P1.0 v P1.1 cng cn c s dng lm ng vo dng (AIN0) v ng vo m (IN), theo th t, ca mch so snh tng t chnh xc trn chip (on chip precision analog comparator). Cc mch m ng ra (output buffer) ca port 1 c th ht dng 20mA v kch trc tip cc b hin th LED. Khi cc logic 1 c ghi n cc chn ca port 1, cc chn ny c th c s dng lm cc ng vo. Khi cc chn t P1.2 n P1.7 c s dng lm cc ng vo v c ko xung mc thp t bn ngoi, chng s cung cp dng (IIL) do cc mch ko ln bn trong. Port 1 cng nhn d liu chng trnh hay d kiu m (code data) trong thi gian lp trnh v kim tra b nh Flash. Port 3 Cc chn ca port 3 t P3.0 n P3.5, P3.7 l chn I/O hai chiu vi cc mch ko ln bn trong. P3.6 c ni dy cng lm ng vo ni n ng ra ca mch so snh trn chip v khng th truy cp nh mt chn I/O c mc ch tng qut. Cc mch m ng ra ca port 3 c th ht dng 20mA.Khi cc logc c ghi n cc chn ca port 3, cc chn ny c ko ln mc cao bi cc mch ko ln bn trong v c th c s dng lm cc ng vo. Khi l cc ng vo, cc chn no ca port 3 c ko xung mc thp bi mch bn ngoi s cung cp dng (IIL) do cc

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mch ko ln. Cc chn ca port 3 cn c s dng cho cc chc nng c bit khc ca AT89C2051 nh c lit k di y ( bng 11,1). Port 3 cng nhn mt s tn hiu iu khin lp trnh v kim tra b nh Flash.

Bng 1.1 RST Ng vo reset (thit lp li trng thi ban u). Tt c cc chn I/O c reset n mc logc ngay sau khi RST ln mc cao. Vic duy tr chn RST mc cao trong 2 chu k my trong khi mch dao ng ang hot ng s reset chip. XTAL 1 Ng vo n mch khuch i dao ng o v ng vo n mch to xung clock bn trong. XTAL 2 Ng ra t mch khuch i dao ng o. I.6 CC C TNH CA MCH DAO NG. XTAL 1 v XTAL 2 l ng vo v ng ra, theo th t, ca mch khuch i o c th c cu hnh tr thnh mch dao ng trn chip nh c trnh by hnh 1.3. Mt tinh th thch anh hoc mch cng hng gm u c th s dng c. kch chip t ngunxung clock bn ngoi, chn XTAL 2 s khng kt ni trong khi chn ATAL 1 c kch nh c trnh by hnh 1.4. Khng c yu cu no v chu k nhim v (duty cycle) ca tn hiu xung clock bn ngoi v ng vo n mch v ng vo n mch to xung clock bn trong s i qua mt flipflop lm nhim v chia 2 tn s, nhng cc c tnh v in p ti thiu v ti a ca mc cao v mc thp phi c xem xt. Hnh 1.3 cc kt ni ca mch dao ng. Lu : C1,C2=30pF 10pF i vi cc thch anh ; C1,C2=40pF 10pF i vi cc b cng hng gm.

Hnh 1.4: Cu hnh kch xung clock bn ngoi.

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I.7CC THANH GHI CHC NNG C BIT SFR

Bng 1.2 Cc gi tr khi reset v bn cc SFR ca AT89C2051 Mt bn vng nh trn chip c gi l khng gian thanh ghi chc nng c bit SFR (special function registor) c trnh by bn trn y (bng 1.2). Lu rng khng phi tt c a ch u b chim bi cc thanh ghi ny, cc a ch khng b chim c th khng c thc hin trn chip. Cc truy cp c n cc a ch ny trong trng hp tng qut, s tr v d liu ngu nhin v cc truy cp ghi s c tc ng khng r rng. Phn mm ca ngi s dng khng nn ghi cc logic 1 n cc v tr nh khng c lit k v chng c th c s dng trong cc sn phm tng lai p ng cc t tnh mi. Trong trng hp , cc gi tr do reset hoc cc gi tr khng tch cc ca cc bit mi s lun lun bng 0. I.8 CC GII HN TRN MT S LNH AT89C2051 l mt thnh vin tit kim v c hiu qu v gi thnh ca h vi iu khin ang pht trin ca Atmel. Chip ny cha 2K b nh chng trnh Flash. Chip ny hon ton tng thch vi kin trc MCS-51v c th c lp trnh bng cch s dng tp lnh MCS-51. tuy nhin, c vi cn nhc m ta ohi ch khi s dng mt s lp trnh ca chip ny. Tt c cc lnh lin quan n cc hot ng nhy v r nhnh s b gii hn, chn hn nh a ch h ri vo trong khng gian nh ca chip, khng gian ny l 2K byte vi AT89C2051. Vn ny l trch nhim ca nguowif lp trnh phn mm. Th d, lnh LJMP 7E0H s l lnh hp l i vi AT89C2051 (c 2K byte b nh chng trnh)trong khi lnh LJMP 900H l lnh khng hp l.

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Cc lnh r nhnh LCALL,LMJP, ACALL, AJMP,SJMP ,JMP@A+DPTR- Cc lnh r nhnh khng iu kin ny s thc thi ng min l ngi lp trnh lu rng a ch ch r nhnh phi nm trong gii hn vt l ca kch thc b nh chng trnh (cc v tr nh t 00H n 7FFH i vi AT89C2051). Vic vi phm cc gii hn khong gian vt l c th gy ra hnh vi khng bit c ca chng trnh CJNE [. . . ], DJNZ [. . . ], JB, JNB, JC, JNC, JBC, JZ, JNZ - Vi cc lnh r nhnh c iu kin ny, cc quy lut ging nh trn cng c p dng. Mt ln na, vic vi phm cc giis hn b nh vt l s lm cho chng trnh thc hti khng ng. i vi cc ng dng bao gm cc cch ngt, cc v tr a ch ca chng trnh phc v ngt (interrupt service rountine) bnh thng ca cu trc h 89C2051 c bo ton. Cc lnh lin quan n MOVX, b nh d liu AT89C2051 cha 128 byte b nh d liu bn trong (intenal data memory). Nh vy trong AT89C2051,kch thc ca b xp chng (stack depth) c gii hn ti 128 byte, ay l dung lng ca RAM c sn. Vic truy cp b nh bn ngoi khng c h tr trong chip ny v vic thc thi chng trnh bn ngoi cng khng c h tr. Nh vy khng c lnh MOVX [. . . ] no cha trong chng trnh. Mt trnh dch hp ng (assembler) in hnh ca 89C51 vn dch cc lnh ny,ngay c khi chng c vit di dng vi phm cc gii hn cp trn. Ngi s dng b vi iu khin phi c trch nhim phi bit cc tnh cht vt l v gii hn ca linh kin ang c s dng v iu chnh cc lnh c s dng mt cch thch hp. Cc gii hn trn y cho ta thy cc khuyt im ca At89C2051. I.9 CC BIT KHO B NH CHNG TRNH Vi chip AT89C2051 ta c 2 bit kho (lock bit), cc bit ny c th li khng lp trnh (U) hoc c th lp trnh (P) nhn thm c cc tnh cht c lit k bng 11.3. Cc bit kho chng trnh LB1 LB2 1 U U 2 P U 3 U U Loi bo v Khng c tnh cht kho chng trnh. Vic lp trnh thm na cho b nh Flash b cm. Tng t ch 2, vic kim tra cng b cm.

Lu : cc bit kho ch c th b xo bng thao tc xo chip Bng 1.3:Cc ch bo v ca bit kho. I.10 CH NGH Trong ch ngh CPU s t ng, trong khi tt c cc ngoi vi khc trn chip iu hot ng v iu duy tr trng thi ch tch cc. Ch ny c yu cu bi phn mm. Ni dung ca RAM trn chip v tt c tren cc thanh ghi chc nng c bit iu gi nguyn khng thay i trong thi gian ch ny. Ch ngh c th c kt thc bi cch ngt bt k c php hoc bng cch reset phn cng. Cc chn P1.0 v P1.1 s c thit lp bng 0 nu khng s dng cc mch ko ln bn ngoi hoc c thit lp bng 1 nu c mch ko ln bn ngoi. Cng cn lu rng khi ch ngh c kt thc bi mt reset cng, chip s tip tc thc thi chng trnh bnh thng t ni chng trnh b ri b, n 2 chu k my trc gii thut reset bn trong ly quyn iu khin. Phn cng trn chip ngm cn vic truy cp n RAM bn trong ch ny nhng khng cm vic truy cp n c chn ca port. lai b kh nng c mt thao tc khng mong i n mt chn ca port khi ch ngh c kt thc bng reset, lnh theo sau lnh yu cu ch ngh s khng th l lnh ghi n mt chn port hoc b nh ngoi.

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I.11 CH GIM CNG SUT Trong ch gim cng sut, mch dao ng b dng v lnh yu cu ch gim cng sut l lnh sau cng c thc thi. RAM trn chip v cc thanh ghi chc nng c bit gi li cc gi tr ca chng cho n khi cc ch gim cng sut c kt thc.Li thot duy nht ra khi ch gim cng sut l s dng reset cng. Reset s nh ngha li cc thanh ghi chua\c nng c bit nhng khng lm thay i Ram trn chip. Reset khng nn c kch hot trc khi in p VCC c khi phc n mc hot ng bnh thng v reset phi duy tr tch cc lu cho php mch hot ng tr li v tr nn n nh. Cc chn P1.0 v P1.1 s c thit lp bng 0 nu khng s dng cc mch ko ln bn ngoi hoc c thit lp bng 1 nu c mch ko ln bn ngoi. I.12 LP TRNH FLASH AT89C2051 trn th trng c di nh chng trnh PEROM trn chip la 2K byte trng thi c xa (ngha l ton b ni dung ca cc byte l FFH) v sn sng c lp trnh. Di nh chng trnh c lp trnh mt byte cho mi thi im. Mt khi di ny c lp trnh, lp trnh li bt k byte no khng trng, ton b di nh c xa bng in. B im a ch bn trong AT89C2051 c mt b m a ch PEROM bn trong, b m ny lun lun c thit lp l 00H cnh ln ca RST v c tng ln bng cch p dng xung ang tr thnh mc dng (positve going pluse) n chn XTAL1. Gii thut chng trnh lp trnh AT89C2051, theo trnh t sau y. 1. Trnh t cp in: Cp in gia cc chn VCC v GND Thit lp RST v XTLA1 n mc thp (GND) 2. Thit lp RST ln mc cao (H) Thit lp chn P3.2 ln mc cao (H) 3. p dng t hp cc mc logic H v L thch hp n cc chn P3.3, P3.4, P3.5 v P3.7 chn 1 trong cc thao tc lp trnh c trnh by trong bng cc ch lp trnh PEROM (PEROM proramming modes table). lp trnh v kim tra di nh chng trnh: 4. t d liu ca byte chhng trnh ( hay cn gi l byte m) v tr 00h n cc chn t P1.0 n P1.7. 5. Tng RST ln 12V cho php lp trnh. 6. a mt xung n chn P3.2 lp trnh mt byte trong di PEROM hoc cc bit kha. Chu k ghi byte c t nh thi v in hnh chim 1.2ms. 7. kim tra d liu lp trnh, gim thp RST t 12V xung mc logic cao H v thit lp cc chn t P3.3 n P3.7 n cc mc logic thch hp. D liu xut c th c c cc chn ca port 1. 8. lp trnh mt byte v tr a ch k tip, a mt xung n XTAL1 tng b m a ch bn trong (internal address counter). t d liu mi n cc chn ca port 1. 9. Lp li cc bc t 6 n 8, thay i d liu v tng b m a ch cho ton b di byte hoc cho n khi kt thc tp tin i tng (object file). 10.Trnh t ngt ngun in. Thit lp XTLA1 n mc thp (L) Thit lp RST n mc thp (L) Tt ngun cp in cho VCC.

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Data Polling: AT89C2051 c Data Polling ch ra vic kt thc mt chu k ghi. Trong thi gian ca mt chu k ghi, vic th c byte sau cng c ghi s dn n vic ly b d liu c ghi trn chn P1.7. Mt khi chu k ghi kt thc, d liu s c hiu lc trn tt c cc ng ra v chu k k tip c th bt u. Data Polling c th bt u bt c lc no sau khki mt chu k ghi c khi ng. Ready/ Busy : Tin trnh lp trnh byte cng c th gim st bng tn hiu ng ra RDY/ BSY . Chn P3.1 c ko xung mc thp sau khi chn P3.2 tr thnh mc cao trong thi gian lp trnh s ch ra trng thi bn (BUSY). Chn P3.1 c ko ln mc cao ln na khi vic lp trnh kt thc s chh ra trng thi sn sng (READY). Program verify ( kim tra chong trnh ): Nu cc bit kha LB1 v LB2 khng c lp trnh, d liu chng trnh c th c ngc v thng qua cc ng d liu kim tra: 1. Reset b m a ch bn trong v 00H mang RST t L ln H. 2. t cc tn hiu thch hp c d liu chng trnh v c d liu ng ra cc chn ca port 1. 3. a mt xung n chn XTAL 1 tng b m a ch bn trong. 4. c byte d liu k tip cc chn ca port 1. 5. Lp li cc bc 3 v 4 cho n khi ton b di nh chng trnh c c. Cc bit kha khong th c kim tra trc tip. Vic kim tra cc bit kha s nhn c bng cch tun theo cc tnh cht c cho php ca chng. Chip erase (xa chip): Ton b di PEROM (2K byte) v hai bit kha c xa bng in bng s dng t hp thch hp cc tn hiu iu khin v bng cch gi cho chn P3.2 mc thp trong 10ms. Di nh chng trinhd c ghi vi tt c cc bit iu l 1 trong thao tc xa chip va phi c thc hin trc khi bt k byte nh khng trng no c th c lp trnh li. Reading the signature bytes (c cc byte ch k ): Cc byte ch k c c vi cng th tc nh vic kim tra bnh thng cc v tr nh 000H, 001H, 002H, ngoi tr cc chn P3.3 v chn P3.5 phi c ko xung mc logic thp. Cc gi tr c tr v nh sau: (000H) = 1EH ch ra c sn xut bi Atmel. (001H) = 21H ch ra 89C2051.
I.13CC CH LP TRNH FLASH Cc ch lp trnh Flash c tm tt bng 1.4.

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Lu : 1. B m a ch PEROM bn trong c reset v 000H cnh ln ca RST v c tng bi xung dng chn XTAL 1. 2. vic xa chip yu cu xung PROG ko di 10ms. 3. Chn P3.1 c ko xung mc thp trong thi gian lp trnh ch ra RDY/BSY Write code data: ghi d liu chng trnh. Read code data: c d liu chng trnh. Write lock : ghi cc bit kha. Chip erase : xa chip. Read signature byte : c byte ch k

SEE FLASH PROGRAMMING MODE TABLE:xem bng ch lp trnh Flash. PGM DATA: d liu chng trnh. TO INCREMENT ADDRESS COUTER: tng b m a ch.

I.14 CC C IM LP TRNH FLASH

K hiu VPP IPP tDVGL tGHDX t EHSH tSHGL tGHSL tGLGH tELQV

Thng s in p cho php lp trnh. Dng in cho php lp trnh. Thi gian t lc d liu n khi PROG mc thp. Thi gian gi d liu sau khi PROG tch cc. Thi gian P3.4 ( NABLE ) t H ln VPP. Thi gian t lc thit lp VPP n khi PROG mc thp. Thi gian gia VPP sau khi PROG tch cc. rng ca PROG. Thi gian t lc ENABLE mc thp cho n khi d liu c

Min 11.5 1.0 1.0 1.0 10 10 1

Max 12.5 250

110 1.0

n v V A s s s s s s s

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tEHQZ tGHBL tWC tBHIH tHIL hiu lc. Thi gian th ni d liu sau khi ENABLE tch cc. Thi gian t khi PROG mc cao cho n khi BUSY o mc thp. Thi gian ca chu k ghi byte. Tr hon t RDY/BSY n khi clock tng. Thi gian c0lock mc cao. 0 1.0 50 2.0 1.0 200 s ns ms s ns

Bng 11.5 Cc t im lp trnh v kim tra Flash. TA = 00C n 700 C, VCC = 5.0 10%. Ch s dng ch lp trnh 12 V. I.15 CC C LNG CC I TUYT I Tm nhit hot ng: Tm nhit tch tr: in p trn bt k chn no so vi t (GND): in p cp in cc i: Dng DC ng ra: t -550C n +1250C. t -660C n +1500C. -1.0 V n +7 V. 6.6 V. 25.0 mA.

CC DNG SNG LP TRNH V KIM TRA FLASH

Hnh 1.5 Cc dng sng lp trnh v kim tra Flash.

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DNG SNG MCH KCH XUNG CLOCK BN NGOI

Hnh 1.6:Dng sng mch kch xung clock bn ngoi. MCH KCH XUNG CLOCK BN NGOI K hiu 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Thng s Tn s dao ng. Chu k xung clock. Thi gian mc cao. Thi gian mc thp. Thi gian tng (cnh ln). Thi gian gim (cnh xung). VCC=2.7V n 6.0V Min Max 0 12 83.3 30 30 20 20 VCC=4.0V n 6.0V Min Max 0 24 41.6 15 15 20 20 n v MHZ ns ns ns ns ns

Bng 1.5 Cc thng s ca mch kch xung clock bn ngoi. NH THI PORT NI TIP: IU KIN KIM TRA CH THANH GHI DCH VCC = 5.0 20%; in dung ti = 80 pF. K Thng s hiu Thi gian chu k xung clock port ni tip. Thi gian t lc thit lp d liu xut n cnh ln ca xung clock Thi gian gi d liu xut sau cnh ln ca xung clock. Thi gian gi d liu nhp sau cnh ln ca xung clock Thi gian t cnh ln xung clock n khi d liu nhpc hiu lc. Dao ng 12 MHZ Min Max 1.0 700 50 0 700 Dao ng thay i Min Max 12tCLCL 10tCLCL 133 2tCLCL 177 0 10tCLCL 133 n v s ns ns ns ns

Bng 1.6 Cc iu kin kim tra ch nh thi thanh ghi dch

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CC DNG SNG NH THI CH THANH GHI DCH

Hnh 1.7 Dng sng nh thi ch thanh ghi dch.

DNG SNG NG VO/NG RA KIM TRA AC1

Hnh 1.8:Dng sng ng vo/ng ra kim tra AC. Lu : 1. Cc ng vo AC trong thi gian kim tra c kch (VCC 0.5) V i vi logic 1 v 0.45 V i vi logic 0. Cc php o nh thi c thc hin VIHmin i vi logic 1v VILmax i vi logic 0. DNG SNG TH NI1

Hnh 1.9 Dng sng th ni. Timing reference points: cc im tham chiu nh thi. Lu : 1. i vi mc ch nh thi, mt chn port s khng cn th ni kho c s thay i 100mV t in p trn ti. Mt chn port bt u th ni khi c s thay i 100mV t mc VOH/VOL (c ti).

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ICC CH TCH CC

Hnh 1.10: ICC ch tch cc. ICC CH NGH V CH GIM CNG SUT

Hnh 1.11: (a) ICC ch ngh ,(b) ICC ch gim cng sut.

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II.Gii thiu v Vi iu Khin AT89C51

MSC51 l mt h Vi iu Khin (Microcontroller) do hng Intel sn xut.Cc IC ca h MSC51 tiu biu l 8051 v 8031. c bit, vi iu khin 89C51 sn xut gn y mang cc c im sau: 4Kbytes EEPROM. 128 bytes RAM. 4 Port I/O (Input/Output). 2 b nh thi Timer 16 bits. Giao tip ni tip. 64Kbytes khng gian b nh chng trnh m rng. 64Kbytes khng gian b nh d liu m rng. Mt b x l lun l (thao tc trn cc bits n). 210 bits c a ch ha. B nhn chia 4s.

H THNG GIAO TIP PORT. Port 0: port 0 l mt port hai chc nng trn cc chn 32-39. Hy nh rng : trn cc chn ny cha c in tr ko dng, do khi cn chng ta cn nh n c im ny. Port 1: port 1 l mt port I/O trn cc chn 1-8. Port 2: port 2 l mt port cng dng kp trn cc chn 21-28. Port 3: port 3 l mt port cng dng kp trn cc chn 10-17. Cc chn ny u c nhiu chc nng, cc cng dng chuyn i c lin h ti cc c tnh c bit ca 8051 bng sau:

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CC TN HIU IU KHIN: Chip AT89C51 c cc tn hiu iu khin cn phi lu nh sau: Tn hiu vo EA\ trn chn 31 thng t ln mc cao ( +5V) hoc mc thp (GND) Nu mc cao, 8951 thi hnh chng trnh t ROM ni trong khong a ch thp (4K hoc ti a 8k i vi 89C52). Nu mc thp, chng trnh c thi hnh t b nh m rng (ti a n 64Kbyte). Ngoi ra ngi ta cn dng EA\ lm chn cp in p 12V khi lp trnh EEPROM trong 8051. CHN PSEN (Program store enable): PSEN l chn tn hiu ra trn chn 29. N l tn hiu iu khin cho php chng trnh m rng, PSEN thng c ni n chn OE\ (Output Enable) ca mt EPROM hoc ROM cho php c cc bytes m lnh. Hy nh rng : bnh thng chn PSEN\ s c th trng ( No Connect).Ch khi no cho EA\ mc thp th lc : PSEN\ s mc thp trong thi gian ly lnh. Cc m nh phn ca chng trnh c ly t EPROM qua bus d liu v c cht vo thanh ghi lnh ca 8951 gii m lnh. PSEN\ mc th ng (mc cao) nu thi hnh chng trnh trong ROM ni ca 8951. CC CHN NGUN: AT8951 hot ng ngun n +5V.Vcc c ni vo chn 40, v Vss (GND) c ni vo chn 20.

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Chng 2: Gii thiu chung v phn mm Keil Software

Phn mm Keil SoftWare 8051 cng c pht trin c lit k di l nhng chng trnh m bin tp m C, tp hp nhng tp tin assembly, lin kt v nh v nhng on chng trnh hng i tng, nhng th vin , khi to file HEX, v trnh g li. Vision l mt mi trng pht trin tch hp m kt hp qun l project ,son tho m ngun v trnh g li trong mi trng mnh. Cx51 ANSI ti u b bin dch C v to ra nhng on chng trnh hng i tng nh v li t m ngun C. Ax51 Macro Assembler to ra nhng an chng trnh hng i tng nh v li 8051 m ngun assembly. BL51 b kt ni / d tm nh v li nhng on chng trnh hng i tng c to ra t C51 v A51 vo nhng on chng rnh hng i tng tuyt i. LX51 m rng b kt ni / b d tm h tr nhng phng n thit b m rng v cung cp nhng c tnh b sung.LX51 h tr tt c cc phng n ca Cx51 v Ax51. LIBx51 trnh qun l th vin kt hp nhng on chng trnh hng i tng vo trong nhng th vin m c th c s dng bi b kt ni. OHx51 b bin i sang file HEX . to ra nhng file HEX t nhng on chng trnh hng i tng tuyt i. RTX51 Tiny h thng thi gian thc RTX51 , thit k n gin nhng d n phn mm phc tp, nh thi.

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II.1 CHU TRNH PHT TRIN PHN MM

Khi chng ta s dng phn mm Keil Vision , chu trnh pht trin phn mm cng ging nh chu trnh pht trin bao phn mm khc. 1. Khi to project , la chn chip t c s d liu thit b , thit t nhng cng c nh hnh. 2. To ra nhng tp tin ngun C hoc assembly. 3. Xy dng nhng ng dng vi Project Manager. 4. Kim tra li tp tin ngun. 5. Kim tra nhng ng dng c lin kt. S khi sau y minh ha chu trnh pht trin phn mm Vision/ARM y .Mi phn c m t bn di.

II.2 Vision IDE

Vision IDE kt hp qun l d n , trnh bin tp vi s sa cha li, ci t ty chn, phng tin, v gip trc tuyn. S dng Vision to ra nhng tp tin ngun v t chc chng vo trong nhng d n ng dng. Vision IDE t dng bin tp, lp rp, v lin kt nhng ng dng nhng. C51 Compiler & A51 Macro Assembler (Trnh bin tp C51 v trnh hp ng A51 ) Nhng tp tin ngun c to ra bi Vision IDE v c a qua C51 hoc A51.Trnh bin tp v trnh lp rp x l nhng tp tin ngun v to ra nhng tp tin i tng nh v li c.

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 n Tt Nghip Trnh bin dich Keil C51 l mt s thi hnh m ANSI y ca ngn ng lp trnh m h tr tt c cc c tnh chun ca ngn ng C. Ngoi ra , nhiu c tnh h tr trc tip kin trc 8051 c thm. Chng trnh Keil A51 h tr tp lnh y ca 8051. LIB51 Library Manager (trnh qun l th vin LIB51) LIB51 cho php chng ta to ra th vin mc tiu t nhng tp tin i tng c to ra t trnh bin tp v trnh lp rp. Nhng th vin c nh dng c bit, sp t cho chng trnh nhng tp hp ca nhng on chng trnh hng i tng m c th c kt ni nhng ln sau.Khi b kt ni x l mt th vin , ch nhng on chng trnh hng i tng cn thit to ra chng trnh mi c s dng. BL51 Linker/Locator ( B kt ni BL51/d tm) B kt ni BL51/d tm to ra file LF/DWARF tuyt i s dng nhng on chng trnh hng i tng t nhng th vin v c to ra t trnh bin tp v trnh lp rp.Mt tp tin i tng tuyt i hoc moun cha ng nhng m v d liu khng xc nh, Tt c cc on m v d liu hin c ti nhng v tr b nh c nh. ELF/DWARF c th c s dng Lp trnh mt Flash Rom hoc nhng thit b b nh khc Vi trnh g li Chng trnh chy th Vision Debugger (Trnh g li ) Trnh g li c tnh cht tng trng, mc mc ngun g li l tng ph hp v tin cy.Trnh g li bao gm mt simulator high-speed chng ta m phng 8051. Nhng thuc tnh ca chip m chng` ta s dng th t ng nh hnh khi chng ta la chn t Device Database. Trnh sa li cung cp vi phng php cho chng ta kim tra cc thit b phn cng Thit t MON51 trn h thng v ti chng trnh ca bn s dng giao din Monitor-51 ti trnh g li. S dng giao din GDI km theo trnh g li ti h thng Bn di y lit k nhng th mc cng c pht trin phn mm Keil .

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 n Tt Nghip Assembler Source Template and Include files for the Macro Assembler.( file ngun assembly v nhng file cho trnh dch Macro Assembler) Executable files of the Vision/C51 tool chain.( nhng tp tin chy ca Vision/C51) Example programs ( nhng chng trnh v d) Configuration files for Flash Monitor and pre-configured versions.( Cu hnh cho Flash Monitor v nhng phin bn nh hnh On-Line documentation for Vision/C51.(ti liu trc tuyn cho Vision/C51) Include files for the C compiler.(nhng tp tin cho trnh bin tp C) Files for ISD51 In-System Debugger and pre-configured versions.(nhng file h tr ISD51 trnh g li Run-time libraries and CPU startup files.(th vin v CPU khi ng sp xp nhng file) Configuration files for Monitor-51 (for Classic 8051 Devices).(cu hnh cho Monitor51) Configuration files for Monitor-390 (for Dallas Contiguous Mode) .(cu hnh cho monitor-390) RTX51 Tiny Version 2 Real-Time Operation System.(h thng b nh thi)

Th mc Vision

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II.3 GIAO DIN NGI DNG

II.4 Create a Procject (To mt Procject )

Vision l mt ng dng Windows v chng trnh c kch hot khi click ln biu tng (icon) Create a Project File (to ra mt d n) to mt h s mi ta la chn t Vision menu Project New Projectmt hi thoi Windows hin ra v hi bn t tn cho cho Project mi va khi to.Chng gi rng ta nn s dng mt Folder ring cho mi Project.n gin hn to mt Project mi chn biu tng to ra mt Procject mi . Vision to ra mt Procject mi vi tn PROCJECT1.UV2 cha ng mt tn nhm v h s mc nh. Ta c th thy tn ny trong Project Workspace Files . Khi ta to ra mt Procject mi uVision hi ta la chn CPU cho Procject .hp thoi la chn thit b xut hin cho ta thy c s d liu thit b uVision , ch cn la chn b iu khin m ta s dng . V d nh ta chn B iu khin Philips 80C51RD+ .Nhng ty chn cng c ny cho Philips 80C51RD+ c rt gn bn cu hnh cng c.

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Ch : Ta c th la chn B kt ni m rng (LX51) v trnh Assembler m rng (AX51) trong hp thoi.Linker v Assembler m rng sn sng trong the Keil Professional Developer's Kit v a cho chng ta nhng c tnh b sung . Khi ta to ra mt Procject mi , uVision c th t ng thm m khi ng CPU Trn mt vi thit b , mi trng uVision cn nhng tham s b sung m ta phi thit lp.c nhng thng tin ny mt cch cn thn c cung cp di s m t ca hp thoi ny, t c th c nhng ch dn b sung cho cu hnh thit b.

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Ta c th to ra mt tp tin ngun mi vi menu option File New. iu ny m mt ca s bin tp, ni m ta c th bin son m ngun. uVision nhng c php mu khi ta lu file vi hp thoi (File Save As) di tn *.C. V d chng ta lu di tn Main.C

Khi ta to tp tin ngun , ta c th thm file ti Procject . Nhng xut uVision vi cch thm tp tin ngunvo mt Procject. V d nh ta c th la chn nhm Procject Workspace-Files v click chut phi m menu. Ty chn Add files c m ra. Chn file MAIN.C m ta to ra.

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 n Tt Nghip Thm v nh hnh m khi ng ( Add and Configure the Starup Code) File STARUP.A51 l m khi ng cho a s CPU 8051. M khi ng lm sch b nh d liu v to nhng con tr ngn xp. Ngoi ra mt vi dn xut 8051 yu cu mt m khi to CPU ph hp vi vi cu hnh phn cng. V d Philips 8051RD+ ngh ta chn on-chip xdata RAM m cn c thm vo trong m khi ng. Khi ta cn sa i file ton hc cho ph hp vi phn cng, ta phi copy file STARUP.A51 t C:\KEIL\C51\LIB n ngn Procject To nhm Procject Nhm h s cho php chng ta t chc nhng Procject ln. Cho m khi ng CPU v nhng cu hnh h thng m ta c th to ra mt Procject nhng thnh phn, mi trng , hng dn trong hp thoi.Chn mt group mi to ra mt h thng c tn nhm h s ngn xp. trong Procject mi c th ko th file STARTUP.A51 ln nhm file mi ny.

By gi , Project Workspace Files lit k tt c trong Project . m mt Project son tho, nhn double ln file Project Workspace .Ta c th cn nh hnh STARTUP.A51 trong trnh bin tp.

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Thit t nhng ty chn cho nhng mc tiu. uVision cho chng ta thit t nhng ty chn cho mc tiu phn cng .Hp thoi nhng ty chn cho nhng mc tiu c m qua biu tng thanh cng c hoc qua menu ty chn Project. Trong bng mc tiu ch r nhng tham s thch ng phn cng v thnh phn chip m bn la chn. Sau y l v d nhng thit t :

Sau y l bn m t nhng ty chn ca hp thoi Target

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Xtal ch tn s clock m CPU ca bn hot ng. Trong a s trng hp gi tr ny ng nht vi tn s XTAL.( Specifies the CPU clock of your device. In most cases this value is identical with the XTAL frequency) Memory Model ch r b nh C51, bt u nhng ng dng mc nh l mt s la chn tt. Allocate On-Chip... Use multiple DPTR registers ch r cch dng nhng thnh phn ca chip cho php m khi ng CPU , nu ta ang s dng b nh xdata RAM ta cng phi cho php s truy nhp XRAM trong STARTUP.A51 sp xp. Off-chip...Memory ch r tt c cc vng b nh ngoi Ch r nhng tham s cho m v xdata. Tham chiu ti Code Banking bit thm chi tit hn Specifies the parameters for code and xdata banking. Refer to the "Code Banking" section for more information Vi ty chn trong hp thoi ch c nu ta ang s dng LX51 Linker/Locater. LX51 Linker/Locater ch c trong gi PK51 Xy dng Project v khi to file HEX Nhng thit t cng c di nhng ty chn-mc tiu m ta cn khi ng mt ng dng mi. Ta c th dch tt c cc tp tin ngun v k nhng ng dng vi mt ci click trn biu tng Build Target . Khi ta xy dng vi nhng li c php, uVision s trnh by nhng thng bo li v cnh bo vi nhng li c th xy ra. Nhn double trn hng thng bo li m file ngun nh v trong trnh bin tp uVision

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 n Tt Nghip By gi ta c th sa li m ngun hoc thm nhng tp tin ngun mi vo d n. Nt thanh cng c Build Target dch nhng file ngun ch c sa i, hoc file ngun mi v file thc thi. uVision lu gi mt danh sch v nhng file c s dng trong file ngun. Thm ch nhng ty chn cng c c lu tr trong danh sch ph thuc, uVision xy dng li nu cn thit, vi lnh Rebuild Target , tt c nhng file ngun c dch bt chp nhng ci bin. Sau khi kim tra ng dng ca bn, n c th yu cu to ra file HEX v ti xung phn mm ng dng vo trong thit b s dng mt tin ch lp trnh Flash. uVision to file HEX vi mi ln xy dng di nhng ty chn cho Target-Outout dc cho php. Ty chn Merge32K Hexfile sn sng cho nhng ng dng Code Applocations khi ta la chn Extended Linker LX51. Ta c th khi ng tin ch lp trnh Flash sau khi trnh dch lm qu trnh khi bn ch r nhng chng trnh Run Program#1.

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 n Tt Nghip Chng trnh mu Mc ny m t nhng chng trnh mu chy trn Keil C51. Nhng chng trnh mu ny sn sng cho bn chy th. Nhng chng trnh ny gip ta hc cch s dng cc cng c ca Keil C51. ng thi, ta cng c th sao chp cc an m ca chng vo chng trnh ca chng ta. Cc chng trnh mu ca Keil C51 c lu trong thu mc C:\KEIL\C51\EXAMPLES\ . Mi chng trnh c lu trong mt th mc ring cng vi mt tp tin d kin gip bn c th nhanh chng xy dng v nh gi chng trnh. Ngoi ra, cc chng trnh nh ring bit cho RTX 51 cng c cung cp trong mc RTX 51. Bng sau l danh sch cc chng trnh mu trong C51 v tn th mc ca chng. Kiu mu M t Cc chng trnh dng cho cc thit b tng t ADuC83x v ADI 83x ADuC84x m n ch ra cc thit b m rng v cch dng ADI MONITOR DRIVER Mt chogn trnh hp ng n gin m ta c th vit mt on ASM text cho cc port tun t Vi chng trnh ring bit: Dhrystone, Whetstone, Sieve. Benchmarks\... Loi 8051 Blinky lm sng LED trn board Keil MCBx51 BLINKY Kiu m Banking ch ra vic lp trnh trn b nh 64K CodeBanking\... B cng v tr n gin m cho thy lm sao xy dng mt CSAMPLE chng trnh vi nhiu module trn Vision Vi v d s dng Dallas Contigious Addressing Mode m n c Dallas 390 sn mt vi thit b khc nhau nh DS80C390, DS80C400, DS80C41x, DS5240, and DS5250. Lm sao m rng nh tr6n 64K FarMemory Chng trnh hin ch Hello world. Chy th n trc khi s Hello dng Vision. Cho thy cch dng Infineon m rn cc thit b: MDU v b Infineon C517 giao in ni tip. Nhng chng trnh mu cho bo mch Keil MCBXC866 h tr Infineon XC866 c thit b Infineon XC800 Cc chng trnh mu cho Mentor M8051EW M8051EW L h thng thu thp v tp hp nhng d liu s v tng t. L MEASURE chng trnh iu khin h thng o lng nhit t xa. L chng trnh mu cho h Philips 80C51MX h tr ti 16MB Philips 80C51MX vng a ch Chng trnh cho bo mch Keil MCB900 Evaluation m h tr Philips LPC9xx cc thit b Philips LPC900 - LPC94x Chng trnh cho bo mch Keil MCB9xx Evaluation m h tr Philips LPC95x cc thit b Philips LPC950 - LPC99x Chng trnh mu cho dng ST uPSD cho thy cu hnh h ST uPSD thng Keil ULINK USB-JTAG Adapter Chng trnh cho cc thit b TI MSC121x ch ra cch dng h TI MSC121x thng gii m ISD51 In-System Debugger Chng trnh cho cc thit b TI MSC1200 ch ra cch dng h TI MSC1200 thng gii m ISD51 In-System Debugger SVTH:L Vn Long & ng c Trung CDDT6K Trang 30

 n Tt Nghip bt u s dng mt trong cc chng trnh mu, ta m menu Project Open Project trong Vision ri m tp tin chng trnh. Cc mc trong chng ny m t lm sao s dng cc cng c xy dng cc chng trnh sau: HELLO : chng trnh C vit cho 8051 MEASURE: h thng o lng t xa. HELLO Chng trnh HELLO c lu trong th mc C:\KEIL\C51\EXAMPLES\HELLO\ . chng trnh ny khng lm g hn l xut on text HELLO WORLD ra port. Ton b chng trnh c lu trong tp tin ngun l HELLO.C ng dng nh ny gip bn c th bin tp, lin kt v g li mt ng dng. Bn c th thc hin thao tc ny t dng lnh trn DOS, s dng tp tin dng batch hoc dng Vison trn windown vi cc tp tin chng trnh. Phn cng cho ch HELLO da vo CPU 8051 chun. Mt con chip ngoi vi c s dng cho cc dy port. Tuy nhin, vi Vision bn khng cn phi c 1 CPU v chng trnh ng vai tr phn cng yu cu cho chng trnh ny. Tp tin chng trnh HELLO Trong Vision, nhng ng dng c lu trong tp tin chng trnh. Mt chng trnh c vit cho ch HELLO. m chng trnh ny ta chn Open Project t menu Project v m tp tin HELLO.UV2 t th mc \C51\EXEMPLES\HELLO.

Son tho chng trnh HELLO.C By gi bn c th son tho chng trnh HELLO.C bng cch nhp p chut vo ca s project file. Vision s ti v hin th ni dung file HELLO.C trn ca s lm vic.

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Bin dch v kt ni HELLO Khi bn sn sng bin dch v lin kt chng trnh ca mnh, s dng lnh Build Target t menu Project hot thanh cng c Build. Vision bt u bin dch v lin kt to ra mt on chng trnh m bn c th ti vo Vision cho vic th li. Qu trnh xy dng c lit k trong ca s ng ra.

Ch Bn cn phi khng gp li khi chy cc chng trnh mu chy th HELLO Khi chng trnh HELLO c bin dch v kt ni ta c th kim tra n vi trnh tm li ca Vision. Trong Vision, s dng lnh Start/Stop Debug Session t menu Debug hoc thanh cng c. Vision khi to trnh bo li v khi ng cc chng trnh con n cc chng trnh chnh. Sau y l mn hnh hin th:

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M ca s Serial Window #1 cho ta thy cc hin th ng ra vi lnh m ca s Serial Window #1 t menu VIEW hoc thanh cng c Debug. Chy chng trnh HELLO vi lnh GO t thanh cng c Debug. Chng trnh li cho c thc hin v hin th on vn bn HELLO WORLD trong ca s serial window. Sau khi ng ra hin th HELLO WORLD n s chy vi vng lp v tn. Dng vic chy chng trnh HELLO vi lnh Halt t menu Debug hoc thanh cng c. Bn cng c th nh lnh ESC trong trang lnh ca ca s OUTPUT. Trong sut qu trnh kim tra li ca Vision s c hin th nh sau:

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Chy tng bc v ngt ngang S dng lnh Insert/Remove Breakpoints t thanh cng c hoc t trnh n trn menu lp trnh. Ta dng chut phi t im dng trn im bt u ca hin chnh. S dng lnh Reset CPU t menu DEBUG hoc thanh cng c. Nu bn dng chng trnh ang chy bi lnh RUN. Vision s dng chng trnh ti im dng m bn t. Bn c th chy tng bc chng trnh HELLO bng cch n nt STEP trn thanh cng c DEBUG. Nhng cu lnh s c ch ra vi mt tn mu vng. Mi tn s di chuyn theo tng bc thc hin. t con tr chut trn cc bin xem gi tr ca chng. Bn c th chy hoc dng chng trnh bt k kc no vi lnh START/STOP DEBUG. MEASURE: h thng iu khin thit b t xa Chng trnh iu khin (MEASURE) c lu trong th mc ..\C51\Examples\Measure. Chng trnh ny s dng cc d liu s v tng t thng c dng trong cc i kh tng v iu khin trong cng nghip. Chng trnh ny chy trn P89LPC935 CPU v ghi d liu t hai port k thut s v bn ng vo chuyn i A/D. Mt b nh thi (Timer) iu khin qu trnh ly d liu. Mu d liu c th nh hnh t 1 mili giy n 60 pht. Mi d liu o c trong sut thi gian hoc t cc knh ng vo c lu vo RAM.

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 n Tt Nghip Tp tin lnh ca chng trnh o lng Tp tin ny c tn l MEASURE.UV2. m tp tin ta dng lnh Open Project t menu Project v chc file MEASURE.UV2 trong th mc C:\Keil\C51\Examples\Measure. Trang tp tin trong ca s Project cho ta thy nhng tp tin ngun dng bin son chng trnh trc lng. Chng trnh o lng mu gm c 3 tp tin ngun l: Getline.c, Mcommand.c, v Measure.c m ta c th tm thy trong nhm file ngun. Ngoi ra bn cn c th tm thy m khi ng CPU v tp tin d liu. m mt file ta nhp p vo tn tp tin trong Project Workpage

Cc chng trnh c chc nng nhm vo cc mc ch khc nhau cho nhng mi trng th nghim khc nhau. d li chy chng trnh m phng ta chn mc m phng SIMULATOR trong thanh cng c BUILD. Khi s dng phin bn c lng Evaluation Version bn cn phi chn Demo - Simulator.

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 n Tt Nghip M t cc chc nng ca tp tin ngun Measure.c Chc cc hm chnh ca C cho h thng o lng v iu kin ngt cho timer0. cc hm chnh khi to tt c cc thit b ngoi vi ca P89LPC935 v x l cc lnh h thng. iu kin ngt timer,timer0, qun l ng h thi gian thc v ly d liu t php o ca h thng. Nhng qu trnh hin th, thi gian v khong cch gia cc lnh. Nhng hm ny c gi t chng trnh chnh. Cc lnh hin th gi tr tng t t im giao ng s cho tn hiu in t 0.00V n 3.30V Gm cc dng lnh c son tho cho nhng d kin nhn t cc port

Mcommand.c

Getline.c

Yu cu phn cng Cc ng dng o lng ch c th chy trn bo mch Keil MCB900 hoc cc phn cng c bn khc dng P89LBC935. B vi iu khin PL89LBC935 cung cp kh nng nhp vo c tn hiu s v tng t. Port 1 v Port2 c dng nhp tn hiu s v t AD00 n AD03 nhp tn hiu tng t. Tuy nhin, chng ta s khng cn mt bo mch no ht v Vision tch hp chc nng ny. bin dch v lin kt chng trnh MEASURE Khi sn sng bin dch v lin kt chng trnh, s dng lnh Buil Target t menu Project hoc thanh cng c. Vision s thc hin ton b qu trnh v s thng bo cho bn khi hon tt.

chy th chng trnh MEASURE Chng trnh mu iu khin o lng c lp trnh chp nhn cc lnh trn chip ca cc port tun t. Nu bn c phn cng thc t, bn c th d dng phn m phng cui cng kt ni vi CPU P89LPC935. nu bn khng c phn cng th c th s dng phn cng m phng trn Vision. Bn c th s dng ca s Serial Windown cung cp tn hiu c nhp vo. SVTH:L Vn Long & ng c Trung CDDT6K Trang 36

 n Tt Nghip Mi ln chng trnh Measure c xy dng bn c th chy th. S dng lnh START/STOP trong menu DEBUG chy chng trnh kim tra li. Nhng lnh ca h thng iu khin o lng t xa Chui cc lnh dng cho chng trnh c lit k trong bng. Nhng lnh ny bao gm bng m ASCII v tt c cc lnh iu phi c hon tt bng mt s quay vng. Lnh clear Dislay time Interval C D T hh:mm:ss I mm:ss.ttt Cu trc Chc nng Xa tt c cc d liu o c trc Hin th thi gian lm vic v gi tr ng vo t thi gian theo chun 24h t nhng khong thi gian cho mi php o khong thi gian ny t 0:00.001(1ms) v 60:00.000 (60 pht) Khi ng qu trnh ghi d liu o c. Khi nhn lnh start, chng trnh o ly mu tt c cc tn hiu ng vo ti cc khong thi gian nh. Hin th cc gi tr o c, bn c th ch r s ca t1t c cc mu m mnh mun c. Nu khng ch ra th t no, lnh c s hin th tt c cc gi tr o. Bn ch c th c cc gi tr ny trong 1 giy. Nu mun hn th phi dng chng trnh. Thot khi qu trnh ghi gi tr o

start

Read

R[count]

quit

Khi bn chy mt ln chng trnh m phng trn Vision, bn c th vo cc lnh ny trong ca s Serial Windown#1 bn di:

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 n Tt Nghip

Hin th cc on m ca chng trnh Vision cho php bn hin th cc on m ca chng trnh trong ca s Disassembly Window bng cch m menu View hoc dng cc nt trn thanh cng c. Ca s Disassembly Window cho thy s trn ln cc ngun v cc on assembly. Bn c th thay i cch hin th bng cch nhp chut phi vo menu ng cnh.

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 n Tt Nghip hin th ni dung cc nh Vision c th hin th cc nh cc nh dng khc nhau. Ca s nh Memory Window c m t menu View hoc t thanh cng c. Bn c th nhp a ch ca 4 vng nh trang ny. Menu ng cnh cho php bn sa i ni dung nh hoc la chn nhng kiu ng ra khc nhau.

cc bin thay i ng h thi gian Bn c th lin tc nhn ni dung ca cc bin, cu trc v cc mng. Ta c th m ca s Watch Window t menu View hoc thanh cng c. Mt trang ng cnh hin ra cho thy taa61t c cc k t ng cnh ca hm hin thi. Cc trang Watch#1 v Watch#2 cho php ta vo bt k bin no ca chng trnh nh trang sau: Vo cc bin thi gian trong ca s Watch Window La chn vn bn < n F2 chnh sa > cng vi 1 ci click chut v i trong mt giy. Mt ci click chut khc cng qu trnh chnh sa gip ta thm vog a tr ca cc bin. Vi cng cch nh trn ta c th thay i nhiu gi tr. Cch khc l bn c th dng phm F2.

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 n Tt Nghi n ip

xa i mt bin, nhn chn v n phm delete. n v u mng s hin ra khi n k hiu [+]. Cc dng b tht vo n k . Nhng c trc v m phn c chiu s ln nhau. ng Ch Watch Windo cp nhp bt c khi no chn trnh th hin dng Khi ow p i ng c g. Ca s W bn m ch View - Perio m V odic Windo Update cc gi tr cp nht s ly lin tc trong ow e sut q trnh ch chng trnh m ph qu hy hng. Vo bin thi gian t ca s so tho t on t ng h Watch Wind t dow Chc mt bin trong vng son tho v dn cu lnh Add to W menu ng cnh b bng cch c click phi ch hut.

b ian ng t Vo cc bin thi gi t tran lnh ng ra (output window) S dng lnh Watch hSet thm gi tr bi vo ca s Watch W m n s Window

 n Tt Nghip Thc hin chng trnh trc khi bt u m phng chng trnh MEASURE, m ca s Serial Window#1 hin th chui gi tr ng ra bng cch vo menu View hoc thanh Debug. Bn c th thu nh cc ca s khc nu mn hnh khng ln. Bn c th chy tng bc bng lnh Step cc cu lnh Essembler hoc cc on m gc. Nu ca s Assembly Window ang m, bn nn chc chy tng bc cc lnh essembly c bn. Nu ca s son tho vi cc m gc c m, bn chy tng bc vi tng m ngun.

nt lnh chy tng bc n (stepinto) cho php bn thc hin mt bc nhy n cc chng trnh c gi thc hin vic gi mt hm v s khng t ng ngt cho n khi gp im ngt. trn nguyn tc ta c th ngu nhin nhy vo mt hm cha hon tt. Bn c th dng lnh StepOut hon tt hm v tr li gi tr cho n ngay lp tc khi c lnh gi. mi tn vng nh du cu lnh hin thi v hoc cc lnh cp cao. Bn c th ngu nhin bc vo mt hm cha hon tt. lnh chy ngay hng ca con tr (Run till Cursor Line) lnh t v b im ngt Insert/Remove BreakPoint Hp thoi BreakPoint vision cng h tr cc im ngt phc tp. Chng hn bn mun ngt mt chng trnh khi mt bin t gi tr nht nh. Ci t bn di khi no gi tr 3 c vit cho current.time.sec

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 n Tt Nghip

nh ngha im dng ny ta m hp thoi BreakPoint t menu Debug. nh du chn vo Write ( du chn ny ch ra l lnh ngt ch c kim tra khi c vit ti ). Tip tc click vo nt Define chn im dng. kim tra vic thc hin im dng lm cc bc sau: Reset CPU Nu s thc hin chng trnh dng th bt u chy chng trnh o Sau mt t thi gian, Vision dng s thc hin. Chng trnh m hng nh du v tr hng m trong im ngt c t. S ghi vt tin Qu trnh ny thc hin trong sut thi gian kim li cho n im dng ni bn yu cu thng tin cho gi tr thanh ghi v nhng nguyn nhn khc dn ti d ngt. Nu Debug - Enable/Disable Trace Recording c t bn c th nhn thy cc lnh lin quan ti CPU thc hin trc im dng.

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 n Tt Nghip

Bng gi tr cc thanh ghi

Gi ngn xp Cc ngn xp trong ca Vision s c lp y khi chng trnh hon tt. Trang CallStack ca ca s Watch Window cho thy s lng nhau gia cc hm hin thi. Nhp p ln mt hng hin th m gc thc hin chc nng ca n.

On-Chip ngoi vi Vision cung cp mt s cch hin th v sa di cc chip ngoi vi s dng trong chng trnh ca bn. Bn c th thy kt qu ca v d khi thc hin cc bc sau: Reset CPU v xa tt c cc im ngt Nu chng trnh b dng khi bt u o lng. M ca s Serial Window #1 v vo lnh d cho ng dng MEASURE. Chng trnh o lng cho thy gi tr t ng vo port1 v port2 v b chuyn i A/D 1-3. Ca s Serial Window #1 c biu din hnh sau:

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 n Tt Nghip

Nhng hp thoi thit b ngoi vi Vision cung cp cc hp thoi cho: I/O port, thit b ngt, b nh thi, chuyn i A/D, v mt s chip ngoi vi c bit. Cc hp thoi ny c th m t menu Peripheral. Mi hp thoi cho thy cc k hiu SFR lin quan v tnh trng cc thit b ngoi vi. Cho ng dng o c bn c th m Peripherals - I/O Ports - Port2 v Peripherals - A/D Converter - ADC0/DAC0. nhng hp thoi ny cho thy tnh trng ca cc thit b ngoi vi v bn c th thay i gi tr ng vo.

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 n Tt Nghip Bn c th s dng Virtual Simulator Registers (VTREGs) thay i gi tr ng vo. Trong ca s Output Window Command Page bn c th t cc n nh cho cc k hiu VTREG ging nh ngng bin v cc thanh ghi. V D:
PORT2=0xDA AD01=2.3 ; set digital input PORT2 to 0xDA. ; set analog input AD01 to 2.3 volts.

Cc user v tn hiu chc nng ( Signal Function ) Bn c th kt hp cc k hiu VTREG vi chc nng tm li ca Vision to ra mt phng thc phc tp ca vic cung cp d liu ngoi c nhp vo ti cc chng trnh ca bn. Chng trnh mu Measure s dng b gii m khi to file MEASURE.INI nh ngha cc tn hiu hm cho: Xut hin xung rng ca trn ng vo A/D AD01. Xut hin sng sine trn ng vo A/D AD02. Xut hin tn hiu nhiu trn ng vo A/D AD03. Tp tin MEASURE.INI c lu di dng Options for Target Debug Initialization File v c ni dung nh sau:
/*-------------------------------------------*/ /* Function MyRegs() shows Registers R0...R3 */ /*-------------------------------------------*/ FUNC void MyRegs (void) { printf ("---------- MyRegs() ----------\n"); printf (" R0 R1 R2 R3\n"); printf (" %02X %02X %02X %02X\n"); printf ("------------------------------\n"); }

// // Generate Saw Tooth Signal on A/D input AD01 //

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 n Tt Nghip
signal void AD01_Saw (void) { float volts; // peak-to-peak volatage float frequency; // output frequency in Hz float offset; // volatge offset float duration; // duration in Seconds float delay; float val; long i, end, steps; volts offset frequency duration = = = = 2.0; 0.2; 140; 8.0;

printf ("Saw Tooth Signal on A/D input AD01\n"); steps = 100; delay = (0.01/frequency); printf ("Saw Steps = %d\n", steps); end = (duration * 10000); for (i = 0 ; i < end; i++) { val = (i % steps) / ((float) steps); AD01 = (val * volts) + offset; swatch (delay); } }

// // Generate Sine Wave // signal void AD02_Sine float volts; float frequency; float offset; float duration; float val; long i, end; volts offset frequency duration = = = = 1.4; 1.6; 180; 5.0;

Signal on A/D input AD02 (void) { // peak-to-peak volatage // output frequency in Hz // volatge offset // duration in Seconds

printf ("Sine Wave Signal on A/D input AD02\n"); end = (duration * 10000); for (i = 0 ; i < end; i++) { val = __sin (frequency * (((float) STATES) / CLOCK) * 2 * 3.1415926); AD02 = (val * volts) + offset; swatch (0.0001); // in 100 uSec steps

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} }

// // Generate Noise Signal on A/D input AD03 // signal void AD03_Noise (void) { float volts; // peak-to-peak volatage float frequency; // output frequency in Hz float offset; // volatge offset float duration; // duration in Seconds float val; long i, end; volts offset duration = 1.4; = 1.6; = 0.5;

printf ("Noise Signal on A/D input AD03\n"); end = (duration * 100000); for (i = 0 ; i < end; i++) { val = ((float) rand (0)) / 32767.0; AD03 = (val * volts) + offset; swatch (0.00001); // in 10 uSec steps } } // // Run Signal Functions at // signal void Startup (void) swatch (1.0); // wait AD01_Saw (); swatch (0.3); // wait AD02_Sine (); swatch (0.6); // wait AD03_Noise (); } Startup ();

Startup { 1.0 seconds 0.3 seconds 0.6 seconds

// Start the Signals

define button "AD01 Saw Tooth", "AD01_Saw ()" define button "AD02 Sine Wave", "AD02_Sine ()" define button "AD03 Noise Signal", "AD03_Noise ()"

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 n Tt Nghip Bn c th km theo chc nng d li cho nhng hm trong ca s Output Window Command Page.
>MyRegs () ---------- MyRegs() ---------R0 R1 R2 R3 00 00 00 00

Cho nhiu tn hiu chc nng ta c th dng hp cng c ToolBox cho cc yu cu khn cp.

Thc hin phn tch (Performance Analyzer) Vision cho php bn thc hin vin phn tch tnh ton thi gian ca nhng ng dng tch hp Performance Analyzer. chun b cho s phn tch tnh ton thi gian, ta dng vic thc thi chng trnh v m menu Debug - Performance Analyzer m hp thoi Setup Performance Analyzer. Bn c th chn cc k hiu hm hay nh tn hm hoc mt dy a ch khi dng hp thoi Setup Performance Analyzer .

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 n Tt Nghip Thc hin cc bc thy vic thc hin phn tch: m hp thoi Performance Analyzer reset CPU v xa cc im ngt nu chng trnh b dng khi bt u vic o c m ca s Serial Window#1 v g lnh S , g D.

Performance Analyzer cho ta thy biu dng ct trong mi phm vi.biu hnh ct cho thy phn trm thi gian thc hin on m trong mi phm vi. Click vo mt ct thy thng tin thng k chi tit. Phn tch tn hiu logic Vi Logic Analyzer, Vision Debugger/Simulator cung cp mt mn hnh th cho gi tr thay i ca bin hoc VTREGs. Thc hin cc bc sau thy vic phn tch gi tr Logic hot ng: M hp thoi Logic Analyzer S dng hp thoi biu din cc tn hiu bn mun. Mt v d l AD01, AD02, AD03 v mt cu trc nh l current.time.sec. Bn c th chn gia nhiu kiu mu. Chy chng trnh v hin th mc logic ng ra Logic Analyzer cung cp mt mn hnh tnh ton thi gian chi tit ca cc tan hiu chn.

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 n Tt Nghip

S dng cc chip ngoi vi y l cc thng s k thut m bn phi bit to nhng chng trnh dng cc chip ngoi vi v nhng t tnh ca h 8051. nhng thng s c cp trong chng ny. Bn c th s dng cc on m c gii thiu c th nhanh chng lm vic vi 8051. y khng c cc ch n t thit b ngoi vi trong 8051. thay vo chip 8051 cung cp mt s s dng a dng cc chip ngoi vi phn bit gia chng vi nhau. cc on m mu trong chng ny cho ta bit cch s dng cc h chip ngoi vi c bit. Ch rng c nhiu ty chn cu hnh hn c gii thiu trong phn ny. Start up code Special function Register Register bank Interrupt service Rountine Interrupt Enable Registors Parallel Port I/O Timer/counter Serial Interface Watchdog Timer D/A Coverter A/D Coverter Power Redution Modes

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 n Tt Nghip M khi ng ( startup code ) M khi ng c thc hin ngay lp tc khi ta reset ton b h thng v n thc hin cc thao tc sau: Ph thuc vo s khc nhau ca thit b, nhng c tnh c bit ca thit b. Xa ton b cc d liu (ty chn) Thit lp trng thi ban u gi tr cc ngn xp v con tr ngn xp(ty chn) Thit lp trng thi ban u ca con tr ngn xp phn cng 8051 Chuyn i iu khin ti cc bin c thit lp hoc cc hm chnh ca C. Trnh bin dch Keil 51 cc thit b c bit c cc m khi ng khc nhau cht t. Mt m khi ng chung c cung cp trong tp tin ..\C51\LIB\STARTUP.A51. Chc nng cc thanh ghi c bit (Special Function Registers) Cc chip thit b ngoi vi ca 8051 c truy nhp s dng cc thanh ghi c chc nng c bit hoc SFRs. SRFs c nh v tr bn trong chip mt cch trc tip c a ch t 80H n 0FFH. Nh pht trin Keil cung cp cc cng c gm cc tp tin hoc cc file tiu c th nh ngha cc thanh ghi n cho bn. Bn c th s dng cc file tiu c cung cp sn hoc t to cho mnh mt file nh a ch cc chip ngoi vi. Ki bn to mt chng trnh vi Vision bn c th chn vic nh ngha cc thanh ghi c bit ca thit b bng cch dng menu trong ca s lm vic.

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 n Tt Nghip Nhiu chng trnh mu trong chng ny u s dng on m bt u nh sau:

#include <reg51.h>

Cc tp tin nh ngha thanh ghi c lu trong th mc C:\KEIL\C51\INC. on m sau y c trch t mt tp tin nh ngha thanh ghi cho cc port song song I/O .
sfr sfr sfr sfr P0 P1 P2 P3 = = = = 0x80; 0x90; 0xA0; 0xB0; // // // // 8-bit 8-bit 8-bit 8-bit I/O I/O I/O I/O Port Port Port Port P0 P1 P2 P3

Bn c th nh cc gi tr SFRs mt cch trc tip bng cc m ngun C cc tiu flie.

sfr IE = 0xA8; sbit EA = IE^7; // Interrupt Enable register at SFR address 0xA8 // global Interrupt Enable Flag (bit 7 of SFR IE)

Ch : Khi bn ly hoc ghi gi tr cc thanh ghi c bit bn cn phi khai bo SFR trong tp tin ngun. Bit k hiu SFR ch c th nh ngha cho bit a ch ca thanh ghi SFR, m n c nh v theo a ch 0x80, 0x88, 0x90 0xF8. Register Banks ( cc thanh ghi lu tr ) Vi iu khin 8051 c xy dng da vo cc vng nh cn bn vi tm thanh ghi thng dng (R0 R70). Mi thanh ghi l mt thanh ghi byte n. Tm thanh ghi a dng ny c th qun l vic lu tr v cc thanh ghi lu tr. 8051 cung cp 4 thanh ghi lu tr m bn c th s dng. Qu trnh lm vic c bn ca cc thanh ghi d dng c nhn thy khi bn thc hin ngt. Dng cho chng trnh C trn 8051 th ta khng cn chn hoc m thanh ghi v chng trnh mc inh chn thanh ghi lu tr 0. Cc thanh ghi lu tr 1, 2, 3 trong qu cc qu trnh ngt v trnh vic lu tr v khi phc cc ngn xp. Cc iu kin ngt ( Interrupt Service Routines ) Trnh bin dch C51 cho php vit nhng iu kin ngt trong C. trnh bin dch c s dng mt cch hiu qu bng m khi u v m kt thc v iu tit m cc thanh ghi lu tr. Cc iu kin ngt c khai bo nh sau:
void function_name (void) interrupt interrupt_number [using register_bank]

Ch s ngt (interrupt number) gip xc nh a ch vc t ngt ca hm ngt. S dng bng sau xc nh ch s ngt:
Interrupt Number 0 (EXTERNAL INT 0) 1 (TIMER/COUNTER 0) 2 (EXTERNAL INT 1) 3 (TIMER/COUNTER 1) 4 (SERIAL PORT) 5 (TIMER/COUNTER 2) 6 (PCA) 7 Address 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 003Bh Interrupt Number 16 17 18 19 20 21 22 23 Address 0083h 008Bh 0093h 009Bh 00A3h 00ABh 00B3h 00BBh

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 n Tt Nghip
8 9 10 11 12 13 14 15 0043h 004Bh 0053h 005Bh 0063h 006Bh 0073h 007Bh 24 25 26 27 28 29 30 31 00C3h 00CBh 00D3h 00DBh 00E3h 00EBh 00F3h 00FBh

Vic s dng cc thuc tnh cho ta c th ch r mt thanh ghi lu tr trong sutt thi gian thc hin hm ngt. Nhng iu ngt khong ngn c th hiu qu hn khng s dng thuc tnh, khi chng s dng thanh ghi lu tr 0. bn c th kim chng bng hai on m essembler xem hiu qu ca chng. Ch : Cc hm km theo iu kin ngt cn phi c bin tp vi ch th NOAREGS. Vic ny bo m rng vic bin dch khng pht sinh vic thay i cc thanh ghi tuyt i. V d sau cho ta thy mt hm ngt tiu biu:
#include <reg51.h> // Special Function Registers of 80C51 CPU #pragma NOAREGS // do not use absolute register symbols (ARx) // for functions called from interrupt routines. static void HandleTransmitInterrupt (void) { : : } static void HandleReceiveInterrupt (void) { : : } #pragma AREGS // for other code it is save to use ARx symbols static void com_isr (void) interrupt 4 using 1 { if (TI) HandleTransmitInterrupt (); if (RI) HandleReceiveInterrupt ();

} Trong v d trn iu kin ngt chi ch s ngt 4 c thit lp. Tn ca hm ngt l com_isr. Khi lnh ngt c thc hin s ko theo, cc m mc c lu vo thanh ghi CPU v chn thanh ghi lu tr 1. Khi th tc ngt kt thc th gi tr cc thanh ghi c khi phc. Sau y l on m sinh ra bi lnh ngt k trn. Ch rng ni dung thanh ghi lu tr s c hon i v c khi phc li sau khi thot.
; FUNCTION com_isr (BEGIN) 0000 C0E0 PUSH ACC ; Save the Accumulator and Data Pointer 0002 C083 PUSH DPH 0004 C082 PUSH DPL 0006 C0D0 PUSH PSW ; Save PSW (and the current Register Bank) 0008 75D008 MOV PSW,#08H ; This selects Register Bank 1

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 n Tt Nghip
: : 0052 0054 0056 0058 005A

D0D0 D082 D083 D0E0 32

POP PSW ; Restore PSW (and prior reg bank) POP DPL POP DPH POP ACC ; Restore the Accumulatorand DPTR RETI ; FUNCTION com_isr (END)

Cc thanh ghi cho php ngt (Interrupt Enable Registers) 8051 cung cp iu kin ngt cho nhiu chip ngoi vi. Qu trnh ngt hon ton ph thuc vo bit EA ca Interrupt Enable (IE) SFR. Khi bit EA ln mc 1 th qu trnh ngt c thc hin. Khi bit EA xung mc 0 th qu trnh ngt b v hiu. Mi qu trnh ngt th c kim sot bi than ghi IE SFR. Tn mt s chip 8051 c th c hn 1 thanh ghi IE. Kim tra ti liu v chip tn dng cc qu trnh ngt. Cc port song song vo/ra (Parallel Port I/O) Mt chip 8051 bnh thng c 4 port vo ra song song m bn c th kt ni vi cc thit b ngoi vi. Chng l Port 0, Port 1, Port 2, Port 3. Mt s IC 8051 m rng c ti 8 Port xut nhp.
Port P0 P1 P2 P3 Direction I/O I/O I/O I/O Width 8 bits 8 bits 8 bits 8 bits Alternate use Mux'd. 8-bit bus: P1.0-P1.7: Mux'd. 8-bit bus: P3.0: P3.1: P3.2: P3.3: P3.4: P3.5: P3.6: P3.7: A0-A7 & D0-D7 Available for user I/O A8-A15 RXD (Serial Port Receive) TXD (Serial Port Transmit) /INT0 (Interrupt 0 input) /INT1 (Interrupt 1 input) T0 (Timer/Counter 0 Input) T1 (Timer/Counter 1 Input) /WR (Write Data Control) /RD (Read Data Control)

Cc Port trn IC 8051 bnh thng th khng c cc d liu trn thanh ghi iu khin. Thay vo , cc chn ca Port 1, Port 2, Port 3 mi chn c th tng ln m chng c th l u nhp hay u xut. ghi gi tr vo mt Port bn ch n gin ghi gi tr tng chn ca Port . ly gi tr t Port trc ht gi tr ca chn phi c ghi l 1 ( y cng l gi tr ban u sau khi RESET ). V d sau l chng trnh ghi v xut gi tr cc Port I/O:
sfr P1 = 0x90; sfr P3 = 0xB0; sbit DIPswitch = P1^4; sbit greenLED = P1^5; void main (void) { unsigned char inval; // SFR definition for Port 1 // SFR definition for Port 3 // DIP switch input on Port 1 bit 4 // green LED output on Port 1 bit 5

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inval = 0; // initial value for inval while (1) { if (DIPswitch == 1) { // check if input P1.4 is high inval = P1 & 0x0F; // read bit 0 .. 3 from P1 greenLED = 0; // set output P1.5 to low } else { // if input P1.4 is low greenLED = 1; // set output P1.5 to high } P3 = (P3 & 0xF0) | inval; // output inval to P3.0 .. P3.3 } }

Timer/Counter ( b nh thi v b m ) IC 80C52 c ba b Timer/Counter (Timer 0, Timer 1, v Timer 2). Timer 1 v Timer 0 c cc chc nng thng thng nh nhau trong khi Timer 2 c kh nng ng dng cao hn. Cc timer c th hot ng c lp vi nhau vi cc kiu nh thi, kiu m, kiu pht tc baud (cho cc Port tun t). Chng trnh sau l mt v d dng Timer 1 to mt xung vung c tn s 10KHz.
#include <reg52.h> /* * Timer 1 Interrupt Service Routine: executes every 100 clock cycles */ static unsigned long overflow_count = 0; void timer1_ISR (void) interrupt 3 { overflow_count++; }

// Increment the overflow count

/* * MAIN C function: sets Timer1 for 8-bit timer w/reload (mode 2). * The timer counts to 255, overflows, is reloaded with 156, and * generates an interrupt. */ void main (void) { TMOD = (TMOD & 0x0F) | 0x20; reload) TH1 TL1 ET1 TR1 EA = = = = = 256 - 100; TH1; 1; 1; 1; // Set Mode (8-bit timer with

// Reload TL1 to count 100 clocks // Enable Timer 1 Interrupts // Start Timer 1 Running // Global Interrupt Enable // Do Nothing (endless-loop): the

while (1); timer 1 ISR will

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 n Tt Nghip
// occur every 100 clocks. Since the 80C51 CPU runs // at 12 MHz, the interrupt happens 10 KHz. }

B bin i tng t s Cc b bin i tng t s A/D l cc linh kin ch c trn mt s thnh vin ca h 8051 nhng kh ph bin. Cc b bin i A/D thng c iu khin thng qua thanh ghi ch ADCON, thanh ghi ny c gn cho mt v tr cn trng no trong on nh dnh cho cc SFR, thanh chi ADCON cho php ngi s dng chn la knh cn c bin i A/D, b u mt bin i mi v kim tra trng thi ca ln bin i hin ti. Cc b bin i A/D in hnh cn 40 chu k lnh hoc t hn hon tt vic bin i v chng c cu hnh to ra ngt vo lc hon tt vic bin i, vic ny lm cho b vi iu khin nh hng n mt vector ngt c th dnh cho vic bin i A/D. thng thng khuyt im ca b bin i A/D l b ny yu cu b vi iu khin phi mc tnh cc thay v i vo ngh ch ngt do vic bin i hon tt. Kt qu ca vic bin i c c t mt SFR khc hoc mt cp SFR, ph thuc vo phn gii ca b bin i. Chng trnh sau l v d chuyn i tng t t tn hiu ng vo sang s:
#include <ADUC812.H> #include <stdio.h> void main (void) { unsigned char chan_2_convert; SCON = 0x50; TMOD |= 0x20; TH1 = 0xA0; TR1 = 1; TI = 1; // Configure the serial port.

// Configure A/D to sequentially convert each input channel. ADCCON1 = 0x7C; while (1) { unsigned int conv_val; unsigned char channel; // 0111 1100

// Start a conversion and wait for it to complete. chan_2_convert = (chan_2_convert + 1) % 8; ADCCON2 = (ADCCON2 & 0xF0) | chan_2_convert; SCONV = 1; while (ADCCON3 & 0x80); // Read A/D data and print it out. channel = ADCDATAH >> 4;

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 n Tt Nghip
conv_val = ADCDATAL | ((ADCDATAH & 0x0F) << 8); printf ("ADC Channel %bu = 0x%4.4X\r\n", channel, conv_val); } }

B bin i s sang tng t ( D/A coverter) B bin i nychuye63n i tan hiu s i vo thnh tn hiu dng in ng ra. IC Philips 87LPC769 l mt trong cc IC c tch hp b chuyn i s tng t. IC Philips 87LPC769 gm 2 knh, v b chuyn i 8bit D/A d dng thc hin vi chng trnh. V d sau cho ta thy cch dng b chuyn i s dng D/A SFRs.
/* * This program generates sawtooth waveforms on the DAC * of the Philips 87LPC769. */ #include <REG769.H> void main (void) { // Disable the A/D Converter (this is required for DAC0) ADCI = 0; ADCS = 0; ENADC = 0; // Clear A/D conversion complete flag // Clear A/D conversion start flag // Disable the A/D Converter // Set P1.6 and P1.7 to Input Only (Hi Z). P1M2 &= ~0xC0; P1M1 |= 0xC0; ENDAC0 = 1; ENDAC1 = 1; while (1) { unsigned int i;

// Enable the D/A Converters

// Create a sawtooth wave on DAC0 and the // opposite sawtooth wave on DAC1. for (i = 0; i < 0x100; i++) { DAC0 = i; DAC1 = 0xFF - i; } } }

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 n Tt Nghip iu khin cp in (Power Reduction Modes) Ch ngh (Idle mode) c kch hot bng cch thit lp bit IDLE bng 1. ch ngh lm dng mi vic thc thi chng trnh. Cc ni dung trn RAM c bo ton v mch dao ng tip tc hot ng nhng xung clock b kh khng n c CPU. Cc b nh thi v UART tip tc thc hin bn thng cc chc nng ca chng. Ch ngh c kt thc bng cch kch hot mt im ngt bt k. Khi vic thc thile65nh ngt ISR kt thc th h thng s lm vic li t lnh set bit IDLE ln 1. Sau y l chng trnh thc hin ch ngh:
sfr PCON = 0x87; void main (void) { while (1) { task_a (); task_b (); task_c (); PCON |= 0x01; /* Enter IDLE Mode - Wait for enabled interrupt */ } }

Ch gim cp in ( power down mode) c thit lp bng cch set bit PDWN ln 1. trong ch nyma5ch dao ng trong chip b dng. Nh vy cc b nh thi v UART cng nh vic thc hin phn mm u tm ngng. Min l c in p ti thiu 2V t vo chip th cc ni dung lu trn RAM vn c bo ton. Cch duy nht buc b vi iu khin ra khi ch gim cng sut l p t thit lp li (RESET) b vi iu khin ny khi cp in. Sau y l chng trnh th hin qu trnh gim cp in:
sfr PCON = 0x87; void main (void) { while (1) { task_a (); task_b (); task_c (); PCON |= 0x02; /* Enter Power Down Mode */ } }

B nh thi WATCHDOG B nh thi Watchdog c sn trn nhm m rng ca cc thnh vin h 8051. mc ch ca b nh thi Watchdog l thit lp li (reset) li b vi iu khin nu b nh thi khng c cung cp mt trnh t thao tc c th trong mt khong thi gian xc nh. iu ny ngn nga vic np li Wachdog mt cch trng khp ngu nhin bi cc phn mm khc. Trong h 8051, watchdog thng c thc hin di dng mt b nh thi khc trn chip, b nh thi ny lp t l gim tn s mch dao ng h thng v k n m xung clock c chia t l. Khi b nh thi quay vng, h thng thit lp li t u (reset). Watchdog c th c cu hnh i vi tc quay vng v thng c th c s dng lm b nh thi khc mc d y l b nh thi c phn gii thp. SVTH:L Vn Long & ng c Trung CDDT6K Trang 58

 n Tt Nghip Chng trnh sau y cho thy cch thit lp gi tr ban u v reset watchdog:
#include <reg51f.h> /* This function adjusts the watchdog timer compare value to the current * PCA timer value + 0xFF00. Note that you must write to CCAP4L first, * then write to CCAP4H. */ void watchdog_reset (void) { unsigned char newval; newval = CH + 0xFF; CCAP4L = 0; CCAP4H = newval; } void main (void) { unsigned int i; /* Configure PCA Module 4 as the watchdog and make sure it doesn't time-out immediately. */ watchdog_reset (); CCAPM4 = 0x48; /* Configure the PCA for watchdog timer. */ CMOD = (CMOD & 0x01) | 0x40; /* Start the PCA Timer: From this point on, we must reset the watchdog timer every 0xFF00 clock cycles. If we don't, the watchdog timer will reset the MCU. */ CR = 1; /* Do something for a while and make sure that we don't get reset by the watchdog. */ for (i = 0; i < 1000; i++) { watchdog_reset (); } /* Stop updating the watchdog and we should get reset. */ while (1); }

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 n Tt Nghip

PHN III

THI CNG MCH V NG DNG LP TRNH C TRONG AT89C2051

I.iu khin led n S nguyn l:

Code C:
#include < at892051.h > char const num[ ] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; void wait (void) {; } void main( void ) { unsigned int i; unsigned char j; P1 = 0; while(1){ for( j = 0; j < 8; j++ ) { P1 = num[ j ]; for ( i = 0; i < 10000; i++ ) { wait(); } } } } SVTH:L Vn Long & ng c Trung CDDT6K Trang 60

 n Tt Nghi n ip

II. NG DNG C CHO 2 LE 7 O VI N ED N NT NH N S nguyn l:

Code C:
#include < at892051 > 1.h char num ] = {0x3f m[ 3f,0x06,0x5b b,0x4f,0x66 6,0x6d,0x7d d,0x07,0x7f,0x6f}; f void wa (void) ait {;} ain { void ma ( void ){ unsig gned char cn right; nt, unsig gned int i; P1 = 0; P3 = 0; for( ;; ){ right=0;rig ght<3;right+ ++) for (r { P3 = right; for (cnt=0;cn r nt<10;cnt++ +) { [cnt]; P1 = num[ for (i = 0; i < 10000; i++) ; { wait(); } } } } }

 n Tt Nghi n ip

III.NG D I DNG CH LED MATRIX 5x7. HO X S Nguyn L: n

Code C:
#include < at892051. > .h char const pat[5]= 0x3f, 0x02, 0x04, 0x0 0x3f }; c ={ 02, void wait (void) t {; } void main( void ) { ned t, unsign char cnt col; unsign int i; ned P3 = 0; P1 = 0; for( ;; ) { col = 1; for (cnt=0;cnt< <5;cnt++) { fo or(col = 0;co < 32;col<<=1) ol { P1 = pat[cn nt]; P3 = col; ++) for (i = 0; i < 10000; i+ { wait();

 n Tt Nghip
} } } } }

SON THO V BIN DCH CHNG TRNH CHO H VI IU KHIN 8051 1. Son tho chng trnh Dng chc nng Edit ca NC (Norton Commander) hoc bt c phn mm son tho vn bn no khc. Lu di dng file .A51 hoc .ASM, hoc .C v.v.. 2. Chuyn thnh file object (.obj) bng chng trnh A51.exe, hoc ASM51.exe. A51 baitap.a51 [enter] ASM51 baitap.a51 [enter] Chng trnh dch s to ra file baitap.obj v baitap.lsl. File.obj l file c s cho vic lin kt thnh chng trnh thc thi c. Cn file .lsl l file vn bn cha cc lnh, m lnh v a ch tng ng. File .lsl cn cha cc thng bo ca chng trnh bin dch v nhng li c php (nu c). Sau khi thc hin bin dch xong s nhn c thng bo: ASSEMBLY COMPLETE, NO ERRORS FOUND Hoc ASSEMBLY COMPLETE, x ERRORS FOUND (y) Vi x l s li c php v y l s th t ca hng lnh b li cui cng trong chng trnh. M file baitap.lsl xem cc li. Sau , m file baitap.a51, hoc file baitap.asm sa cc li ri tin hnh bin dch li. 3. Chuyn file object thnh file hex (.HEX) bng chng trnh OHS51.EXE hoc OH.EXE. Ohs51.exe baitap.obj [enter] Oh.exe baitap.obj [enter]

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 n Tt Nghip

PHN IV

KT LUN V HNG PHT TRIN TI

KT LUN Trong ti ny chng ti tm hiu v nghin cu lp trnh C cho h vi iu khin 8051 v mi ch i vo mt s ng dng nh nh l iu khin led n , led by on, v led ma trn . Ti cha khai thc ht tm hn ca phn mm Keil C cng nh chip AT89C2051. Kho st qua phn mm Keil C. Thc hin bin dch m ngun C cho led n, led 7 on, led matrix 5x7. HNG PHT TRIN Hng pht trin ca n l: dng ngn ng lp trnh C ng dng vo h thng nhng ca h vi iu khin 8051 hoc cc h vi iu khin khc nh l Philips P89C51Rx2/P89V51 Rx2 m khng ch xut n thun l led n , m l led matrix 5x7, matrix 8x8 , hoc LCD 1 line, LCD 2 line, LCD 4 lineV ng dng ngn ng lp trnh C thit k nhng ng dng thc tin phc v cho i sng ca con ngi.

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 n Tt Nghip

TI LIU THAM KHO

Datasheet AT8051/AT89C51/AT89C2051 Preliminary (Complete) ca hng Atmel Corporation. Users Guide for Keil Vision. Phm Quang Tr, Gio trnh Vi x l ca trng HCN TP.HCM. Gio trnh Vi x l ca trng HBKTPHCM. Website : http://www.keil.com / Sch embedded C Sch Ngn ng C ca cc tc gi Quch Tun Ngc . Handel-C Language Reference Manual.

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MC LC
1. Phn I tng quan ti ............................................................ t vn ................................................................ Ni dung ti 2. Phn II Ni dung ti ............................................................... Chng 1: Gii thiu b vi iu khin T9C2051 v 89C51 Gii thiu b vi iu khin AT89C2051 ................ Gii thiu s lc v vi iu khin AT89C51 ........ Chng 2: Gii thiu phn mm Keil Vision ............ 3. Phn III Thi cng mch v ng dng lp trnh C trong AT89C2051 4. Phn IV Kt lun v Hng pht trin ti .............................. 5. Ti liu tham kho ............................................................... 6. Mc lc ............................................................................... trang 4 trang 4 trang 5 trang 5 trang 19 trang 21 trang 62 trang 67 trang 68 trang 69

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