A TWO OP-AMPS THIRD-ORDER MODULATOR

WITH COMPLEX CONJUGATE NTF ZEROS

Aldo Pera Perez, Oscar Belotti, Edoardo Bonizzoni, and Frnco Maloberti
University of Pavia
Department of Electronics
Via Ferrata, 1 - 27100 Pavia - ITALY
E-mail: [aIdo.perez.oscar.belotti.edoardo.bonizzoni.franco.maloberti]@unipv.it
ABSTRACT
This paper presents a third-order Sigma-Delta modula
tor that uses only two operational amplifers. A fully digi
tal solution reduces both amplifers output swings. This de
sign achieves complex conjugate zeros that allows obtaining
a signal-to-noise ratio of about 8 dB better than having all the
zeros placed at < ~ 1. Behavioral level simulations demon
strate the efectiveness of the approach.
Index Terms- Sigma-Delta modulation, Analog-to
Digital conversion, Operational amplifer output swing re
duction
1. INTRODUCTION
Today portable communications market demands for high
speed and high resolution analog-to-digital converters (ADCs)
with severe requirements on power consumption, in order to
maintain a longer battery life. Sigma-Delta () modula
tors, used for high resolution in audio applications, are more
and more addressed when medium resolutions (12-14 bits)
and signal bandwidth in the MHz or tens of MHz range are
required. To meet specifcations multi-bit third-order mod
ulators are good architectural choice. Low oversampling
ratio (OSR) and the use of low voltage swing operational
amplifers (op-amps) keep low the power consumption.
A third-oder modulator typically uses three integra
tors. However, lower power consumption results by architec
tures that obtain third-order noise shaping with only two inte
grators. Suitable topological modifcations of a conventional
third-order scheme, [1], can obtain the result. An alternative
solution is the noise coupling technique, [2], which, however,
requires an additional active block.
Low op-amps swings enable relaxed slew-rate require
ments, better linearity, lower power consumption, and allows
operation at lower power supply voltages. Various meth
ods for reducing the op-amps output voltage swings have
been proposed, [3], [4], [5]. A further beneft for high order
schemes is to have complex conjugate zeros, [6]. For medium
resolutions, the signal-to-noise (SNR) ratio can be about 8 dB
978-1-4244-8157-6/10/$26.00 201O IEEE 683
A
Fig. 1. Block diagram of a third-order modulator with
complex conjugate zeros.
better than having all the zeros at < ~ I. This project ob
tains all the above features. It realizes with two op-amps a
third-order modulator; a fully digital solution reduces
the amplifers output swings and achieves complex conjugate
zeros.
2. THIRD-ORDER MODULATOR WITH TWO
OP-AMPS AND COMPLEX CONJUGATE ZEROS
Suitable topological changes of a third-order architecture ob
tains a scheme with two integrators, [1]. This paper obtains
the result with complex conjugate zeros in the noise transfer
function (NTF) by the direct cascade of two blocks, shown in
Fig. 1, that realizes a zero at < ~ 1 and two complex ones with
imaginary part o2.
The block !before DACI serves to avoid denominator in
the signal and noise transfer functions. By inspection of the
scheme, the denominator is
where
is the expected noise transfer function. The denominator be
comes one if
ICECS 2010
y
Fig. 2. Block diagram of the second block of Fig. 1.
!(2c) z

(3)
Thus, we achieve the NTF and the signal transfer function
(STF) becomes z.
The scheme of Fig. 2 implements the second block of the
architecture of Fig. 1. Its transfer function is obtained by
that results in
(J 1)z
1

Y
z
z
H (z)
(1 z ) 1 z
Therefore, it is necessary to have
1 z(1 c)
(4)
(5)
(6)
that requires to use an analog delay, obtainable with two ca
pacitors working in interleaved fashion. Fig. 3 shows a pos
sible single-ended SC implementation.
>- VOu!
JIMEEVENJ
0
1

"2

'1b
'2b
Fig. 3. Possible single-ended SC implementation of the block
diagram of Fig. 2.
684
K
y
Fig. 4. Swing reduction of the frst integrator output.
3. SWING REDUCTION
Several methods, [3], [4], [5], obtain op-amps output ranges
reduction in multi-bit architectures. This design uses digital
methods to avoid extra branches at the input of the op-amps.
Fig. 4 shows the technique used to reduce the swing at
the frst integrator. An additional ADC converts the input sig
nal and obtains an input feed forward toward the input of the
second block.
By inspection of the circuit, the output of FLASH-l is
(7)
where L_ is the quantization error and f is the quantized ver
sion of the input signal, J. Therefore, we can eliminate in the
digital domain the term I

(z)7 fz

(1z),as shown
in Fig. 4, to obtain the original response.
For the swing reduction of the second block, we observe
that its output is
With a suitable number of bits in FLASH-l and FLASH-
2, the dominant part of O2 is
1-(2-a)z-1 +z-2
Pl(Z) = z-
1
(1-z-
1
)
P2(z) = z- 1(2-z-
1
)
(9)
y
Fig. 5. Swing reduction at the output of the second amplifer.
P
1
(Z) = Z
1
(1-Z
1
)
P
2
(Z) = z
1
(2-z
1
)
X
1-(2a)z
1
+Z-
2
y
Fig. 6. Third-order I modulator with fully digital swing
reduction.
Suppose to add and subtract that term to O_,as shown in
Fig. 6. This operation does not change O_. Then, we move
the addition in the digital section to obtain (_I_) . The
fnal step is to move the subtraction to the input of the second
block, as depicted in Fig. 5. The output of the block becomes
(_I_) .
Obviously, moving I_(z) at the input of the block re
quires to divide I_(z)by the block transfer function. Thus,
the reduction of the swing of the second block requires a sec
ond extra injection at its input (Fig. 6)
Suitable combinations of digital terms lead to the scheme
of Fig. 7. The term (1c) is distinguished from the rest
because it can be realized using the capacitor (1c)C of
Fig. 3 that obtains the second term of (6). Moreover, to im
plement DAC3, we can use C, of Fig. 3, whose lef terminal
is available during <

.
FLASH-1

= __
FLASH-2
I
Fig. 7. Proposed third-order modulator scheme.
y
685
.31 ,-
.3 .
I
Uo .-aO- -
UZ
U1
U1
.
H UU


U
'g ~UU,
E
-U1
-U1
-UZ

-UZ

'
,[ .236
O
'
.
0
"3 . 3 . 36.3
He| |rl
b0 runS
LaaClIO| |5maIChva|laIlOn = U2
1 1U11 11
B8 8O
Fig. 8. NTF zeros placement.
4. SIMULATION RESULTS
The proposed third-order I modulator with reduced ampli
fers output swing and complex conjugate zeros has been sim
ulated at the behavioral level in Matlab-Simulink . With 4-
bit fash and OSR ~ 8, the SNR with all NTF zeros at z~ 1 is
64.9 dB. Making complex conjugate two zeros with c~ 1111
optimizes the SNR that becomes 72.8 dB.
The zeros placement depends on the accuracy of the ca
pacitor that realizes this coefcient. Typical modern CMOS
technologies ensure capacitors matching within OO2/.
Montecarlo simulations (50 runs) obtain the root locus of (2),
shown in Fig. 8. The mismatch minimally afects the position
of the complex conjugate zeros.
Fig. 9 shows the output voltage swing of the frst integra
tor and the following block when applying an input signal at
-3 dB F S at the upper limit of the bandwidth with and without
swings reduction. The frst and second output swings are re
duced by about 43% and 56 /, respectively, thus demonstrat
ing the efectiveness of the approach. Notice that the circuit
implementation grants z

_
delay for FLASH-2 operation.
Moreover, since the swing of the second block is 53% of the
full scale, the number of comparators of FLASH -1 goes down
from 15 to 8.
The overall consumed power is reduced despite the need
of 8 more comparators. The architecture spares the third op
amp (whose power need is about 50% of the frst op-amp)
and does not need more power on the second block. Simula
tion results show that the use of op-amp with bandwidth and
slew-rate equal to the ones of the frst and second op-amps
of a conventional counterpart obtains the noise spectrum of
Fig. 10. The SNR is 72.2, just 0.6 dB less than the ideal case.
The simulation supposes a signal bandwidth of 2 MHz and
300
250
200
O
C

: 150
O
O
L
100
50
|I|5 LOlBIORBP0IIO|
- With swing reduction
- Without swing reduction
4-b|l |lSh ConVerler
OSR=8@Fs=64MHz
Fin = 1.99 MHz @ -3 dB,s
1L-L-_ 0.2- 0 --0 .2 0 -0 . 8
Voltage [V)
CO0ORU LO|BIOHBPPIIO|
- With swing reduction
200
- Without swing reduction
w
f150
C

:
g 100
L
50
4-b|l ||Sh ConVerler
OSR=8@Fs=64MHz
Fin= 1.99 MHz @ -3 dB,s
Fig. 9. Simulated frst and second amplifer outputs with and without swing reduction.
amplifer unity gain frequency itl ~ it2 ~ 64 MHz.
5. CONCLUSION
This paper has shown a third-order modulator that uses
two operational amplifers and realizes two complex conju
gate zeros to enhance the signal-to-noise ratio. The design
includes a fully digital swing reduction of both amplifers out
put. Simulation results show that the frst and second output
swings are reduced by about 43% and 56%, respectively, with
respect to the conventional counterpart. The obtained SNR is
about 8 dB higher than what can be achieved with all the zeros
placed at < ~ 1.
ii

c
e

-
1
_160 t
1if 1 1 1
Frequency [Hz]
Fig. 10. Simulated output spectrum.
686
6. ACKNOWLEDGMENTS
This work is partially supported by FIRB, Italian National
Program, Project RBAP06L4S5.
7. REFERENCES
[1] E. Bonizzoni, A. Pena Perez, F Maloberti and M.
A. Garcia-Andrade "Two Op-amps Third-Order Sigma
Delta Modulator with 61 dB SNDR, 6 MHz Bandwidth
and 6 mW Power Consumption", Proc. of IEEE Eu
rpean Solid-State Circuits Conference (ESSCIRC), pp.
218-221, Sept. 2008.
[2] K. Lee, M. R. Miller, and G. C. Teres, "An 8.1 mW,
82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB
THD", IEEE Joural of Solid-State Circuits, pp. 2202-
2211, Aug. 2009.
[3] K. Y Nam, S.-M. Lee, D.K. Su, and B. A. Wooley,
"A Low-Voltage Low-Power Sigma-Delta Modulators for
Broadband Analog-to-Digital Conversion", IEEE Jour
nal of Solid-State Circuits, vol. 40, pp. 1855-1864, Sept.
2005.
[4] A. A. Hamoui, M.Sukhon, and F Maloberti, "Digitally
Enhanced High-Order Modulators", Prc. of IEEE
Interational Conference on Electrnics, Circuits, and
Systems (ICECS), pp. 1115-1118, Aug. 2008.
[5] H. Caracciolo, E. Bonizzoni, F. Maloberti, and G. S.
La Rue, "Digitally Assisted Multi-Bit Modulator",
Prc. of IEEE Interational Symposium on Circuits and
Systems (ISCAS), pp. 3993-3996, May 2010.
[6] R. Zanbaghi, T.S. Fiez, and G. Teres, "A New Zero
Optimization Scheme for Noise-Coupled ADCs",
Prc. of IEEE Interational Symposium on Circuits and
Systems (ISCAS), pp. 2163-2166, May 2010.