Professional Documents
Culture Documents
VLSI Design
Curriculum
(2009 - 10 onwards)
University Core
Course Code Course 1|t|e L 1 C
LLL 609 CompuLaLlonal 1echnlques 3 1 0 4
LnC
-
601
-
rofesslonal and CommunlcaLlon Skllls (or)
lorelgn Language
0
2
0
0
4
0
2
2
LLL 698 Semlnar - - - 1
Total credits 07
University Elective
Course Code Course 1|t|e L 1 C
unlverslLy LlecLlve 3 0 0 3
Total credits 03
Programme Core
Course Code Course 1|t|e L 1 C
LLL 387 hyslcs and Modellng of SemlconducLor uevlces 3 0 0 3
LLL 388 ulglLal lC ueslgn 3 0 0 3
LLL 389 Analog lC ueslgn 3 0 0 3
LLL 391 vLSl ulglLal Slgnal rocesslng 3 0 0 3
LLL 396 ASlC ueslgn 3 0 0 3
LLL 600 vLSl ueslgn verlflcaLlon and 1esLlng 3 0 0 3
LLL 340 Lmbedded SysLem ueslgn 3 0 0 3
LLL 398 CompuLer Alded ueslgn for vLSl 3 0 0 3
LLL 610 CusLom lC ueslgn Lab 0 0 2 1
LLL 611 ASlC ueslgn Lab 0 0 2 1
LLL 612 vLSl ulglLal Slgnal rocesslng Lab 0 0 2 1
LLL 613 Lmbedded SysLem ueslgn Lab 0 0 2 1
LLL 699 SLudenL ro[ecL - - - 20
Total credits 48
Programme Elective
Credits to be taken: 15
Course Code Course 1|t|e L 1 C
LLL 397 Low ower lC ueslgn 3 0 0 3
LLL 399 Mlxed Slgnal lC ueslgn 3 0 0 3
LLL 601 Memory ueslgn and 1esLlng 3 0 0 3
LLL 602 Pardware / SofLware Co-ueslgn 3 0 0 3
LLL 603 Advanced CompuLer ArchlLecLure 3 0 0 3
LLL 604 ScrlpLlng Languages for vLSl ueslgn AuLomaLlon 3 0 0 3
LLL 603 laulL-1oleranL and uependable SysLems 3 0 0 3
LLL 390 lC 1echnology 3 0 0 3
ackaglng and lnLerconnecL Analysls 3 0 0 3
8llC ueslgn 3 0 0 3
8econflgurable CompuLlng 3 0 0 3
uS ArchlLecLures 3 0 0 3
LlecLromagneLlc lnLerference and CompaLlblllLy ln LlecLronlc SysLem ueslgn 3 0 0 3
nanoelecLronlcs 3 0 0 3
lmage rocesslng and Compresslon 1echnlques 3 0 0 3
Mlcro LlecLro Mechanlcal SysLem 3 0 0 3
Slngle LlecLronlcs uevlce AppllcaLlons and Modellng 3 0 0 3
SysLem-Cn Chlp ueslgn 3 0 0 3
rogramme LlecLlve lnsLead of University LlecLlve can be Laken
Credit Summary
Mlnlmum Cuallfylng credlLs
73
1oLal credlLs Cffered (uC+C+L) 73
unlverslLy Core 7
unlverslLy LlecLlve 3
rogramme Core Cffered 48
rogramme L lecLlve 13
uC - unlverslLy Core
C - rogramme Core
L - rogramme LlecLlve
uL - unlverslLy LlecLlve
M.Tech. VLSI Design Courses Offered 200809 onwards
No. Course Code Course 1|t|e L 1 C Course
Cffered by
Sy||abus
Vers|on
AC approva|
Date
Course 1ype
397 LLL 609 CompuLaLlonal 1echnlques 3 1 0 4 SSP 1.00 18AC uC
368 LLL 387 hyslcs and Modellng of SemlconducLor uevlces 3 0 0 3 SLS 1.10 18AC C
369 LLL 388 ulglLal lC ueslgn 3 0 0 3 SLS 1.10 18AC C
370 LLL 389 Analog lC ueslgn 3 0 0 3 SLS 1.00 16AC C
371 LLL 390 lC 1echnology 3 0 0 3 SLS 1.00 16AC L
372 LLL 391 vLSl ulglLal Slgnal rocesslng 3 0 0 3 SLS 1.10 18AC C
398 LLL 610 CusLom lC ueslgn Lab 0 0 2 1 SLS 1.00 18AC C
399 LLL 611 ASlC ueslgn Lab 0 0 2 1 SLS 1.00 18AC C
400 LLL 612 vLSl ulglLal Slgnal rocesslng Lab 0 0 2 1 SLS 1.00 18AC C
401 LLL 613 Lmbedded SysLem ueslgn Lab 0 0 2 1 SLS 1.00 18AC C
46 LnC 601 rofesslonal and CommunlcaLlon Skllls 0 0 4 2 SSP 1.00 13AC uC
232 LLL 698 Semlnar - - - 1 SLS 1.00 16AC uC
233 LLL 699 SLudenL ro[ecL - - - 20 SLS 1.00 16AC uC
383 LLL 396 ASlC ueslgn 3 0 0 3 SLS 1.10 18AC C
384 LLL 397 Low ower lC ueslgn 3 0 0 3 SLS 1.00 16AC L
38S LLL 398 CompuLer Alded ueslgn for vLSl 3 0 0 3 SLS 1.10 18AC C
386 LLL 399 Mlxed Slgnal lC ueslgn 3 0 0 3 SLS 1.00 16AC L
387 LLL 600 vLSl ueslgn verlflcaLlon and 1esLlng 3 0 0 3 SLS 1.10 18AC C
388 LLL 601 Memory ueslgn and 1esLlng 3 0 0 3 SLS 1.00 16AC L
389 LLL 602 Pardware / SofLware Co-ueslgn 3 0 0 3 SLS 1.00 16AC L
390 LLL 603 Advanced CompuLer ArchlLecLure 3 0 0 3 SLS 1.00 16AC L
391 LLL 604 ScrlpLlng Languages for vLSl ueslgn AuLomaLlon 3 0 0 3 SLS 1.10 18AC L
392 LLL 603 laulL-1oleranL and uependable SysLems 3 0 0 3 SLS 1.00 16AC L
261 LLL 340 Lmbedded SysLem ueslgn 3 0 0 3 SLS 1.00 16AC L
ackaglng and lnLerconnecL Analysls 3 0 0 3 SLS 1.00 16AC L
8llC ueslgn 3 0 0 3 SLS 1.00 16AC L
8econflgurable CompuLlng 3 0 0 3 SLS 1.00 16AC L
uS ArchlLecLures 3 0 0 3 SLS 1.10 18AC L
LlecLromagneLlc lnLerference and CompaLlblllLy
ln LlecLronlc SysLem ueslgn
3 0 0 3 SLS 1.00 16AC L
nanoelecLronlcs 3 0 0 3 SLS 1.00 16AC L
lmage rocesslng and Compresslon 1echnlques 3 0 0 3 SLS 1.00 16AC L
Mlcro LlecLro Mechanlcal SysLem 3 0 0 3 SLS 1.00 16AC L
Slngle LlecLronlcs uevlce AppllcaLlons and Model
lng
3 0 0 3 SLS 1.00 16AC L
SysLem-Cn-Chlp ueslgn 3 0 0 3 SLS 1.00 L
Credit Summary
Mlnlmum Cuallfylng credlLs 73
1oLal credlLs Cffered (uC+C+L+uL) 73
uC 07
C Cffered 48
L needed 13
uL 3
uC - unlverslLy Core
C - rogramme Core
L - rogramme LlecLlve
uL -unlverslLy LlecLlve
Students admitted during 2009-2010
PHYSICS AND MODELING OF SEMICONDUCTOR DEVICES
L T P C
3 0 0 3
Course Objectives:
This course will help the students acquire a deep understanding of modeling FET devices which
plays an important role in fabrication of integrated circuits. This is likely the most advanced course
on this topic that students will encounter. It should prepare students for research or development of
device technology or digital or analog circuits for many years to come.
Course Outcomes:
A student completing this course will be able to
Explain and apply the semiconductor concepts of drift, diffusion, donors and acceptors,
majority and minority carriers, excess carriers, low level injection, minority carrier lifetime,
quasi-neutrality, and quasi-statics;
Explain the underlying physics and principles of operation of p-n junction diodes, metal-
oxide-semiconductor (MOS) capacitors, bipolar junction transistors (BJTs), and MOS field
effect transistors (MOSFETs), and describe and apply simple large signal circuit models for
these devices which include charge storage elements.
Semiconductor Physics:
Metals, insulator, semiconductors, intrinsic and extrinsic semiconductors, direct and indirect band
gap, free carrier densities, Fermi distribution, density of states, Boltzmann statistics, thermal
equilibrium, current flow mechanisms, drift current, diffusion current, mobility, band gap narrowing,
resistance, generation and recombination, lifetime, internal electro-static fields and potentials,
Poissons equation, continuity equations, drift-diffusion equations.
PN-Junction Diodes:
Thermal equilibrium physics, energy band diagrams, space charge layers, internal electro-static fields
and potentials, reverse biased diode physics, junction capacitance, wide and narrow diodes, transient
behavior, transit time, diffusion capacitance, small signal model.
Bipolar Transistors:
Basic theory and operation, heavy doping effects, double diffused transistors, Ebers-Moll model,
low forward bias, junction and diffusion capacitance, transit times, parasitic, small-signal models,
Early effect, saturation and inverse operation, breakdown mechanisms, punch-through.
MOS Transistors
MOS capacitor, accumulation, depletion, strong inversion, threshold voltage, contact potential, oxide
and interface charges, body effect, drain current, saturation voltage, gate work function, channel
mobility, sub-threshold conduction, short channel effects, effective channel length, effects of
channel length and width on threshold voltage, Compact models for MOSFET and their
implementation in SPICE. Level 1, 2 and 3, MOS model parameters in SPICE.
UDSM Transistor Design Issues
Short channel and ultra short channel effects; Effect t
ox
, effect of high k and low k dielectrics on
the gate leakage and Source drain leakage; tunneling effects; different gate structures in UDSM -
impact and reliability challenges in UDSM.
Text Books:
1. Y.P. Tsividis, The MOS Transistor, McGraw-Hill, international edition ed., 1988.
2. S.M.Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons Inc, (2/e).
References:
1. Getreu, Modeling the bipolar transistor, New York, NY: Elselvier, 1978.
2. D. Roulston, Bipolar Semiconductor Devices, McGraw Hill, 1990.
3. N. Arora, MOSFET Models for VLSI Circuit Simulation, Springer-Verlag, 1993.
4. P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, 1988.
5. D.W. Greve, Field Effect Devices and Applications, Prentice Hall Series in Electronics and VLSI, 1998
Students admitted during 2009-2010
DIGITAL IC DESIGN
L T P C
3 0 0 3
Course Objective:
This course is preparatory for study in the field of Very Large Scale Integrated (VLSI) digital circuits and
engineering practice. The course focuses upon the systematic analysis and design of basic digital integrated
circuits in CMOS technology. Problem solving and creative circuit design techniques are emphasized
throughout. This course provides the foundation for subsequent courses in the design of digital integrated
circuits and systems. Basic principles, methodologies, and ad-hoc analysis and design techniques are
emphasized.
Course Outcomes:
After completion of this course the students will be familiar with modern VLSI circuits and will be able to
design most of them.
Introduction
Issues in Digital IC Design. Quality Metrics of a Digital Design. MOS Transistor. Manufacturing
CMOS Integrated Circuits. Design Rules. Layouts.
The CMOS inverter
Static CMOS Inverter: Static and Dynamic Behavior Practices of CMOS Inverter. Components of
Energy and Power: Switching, Short-Circuit and Leakage Components. Technology scaling and its
impact on the inverter metrics.
CMOS Combinational Logic Circuit Design
Static CMOS Design: Complementary CMOS, Ratioed Logic, Pass Transistor Logic. Dynamic
CMOS Design: Dynamic Logic Design Considerations. Speed and Power Dissipation of Dynamic
logic, Signal integrity issues, Cascading Dynamic gates.
CMOS Sequential Logic Circuit Design
Introduction. Static Latches and Registers. Dynamic Latches and Registers. Pulse Based Registers.
Sense Amplifier based registers. Latch vs. Register- based pipelines structures.
Interconnect and Timing Issues
Interconnects: Resistive, Capacitive and Inductive Parasitics. Computation of R, L and C for given
inter-connects. Buffer Chains.
Timing Issues: Timing classification of digital systems. Synchronous Design - Origins of Clock
Skew/Jitter and Impact on Performance. Clock Distribution Techniques. Latch based clocking.
Synchronizers and Arbiters. Clock Synthesis and Synchronization using a Phase-Locked Loop.
Text Books:
1. Jan M.Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective, (2/e), PHI.2005
2. Neil.H.E.Weste, David Harris, Ayan Banerjee, CMOS VLSI Design: A Circuit and Systems
Perspective, (3/e). Pearson Education. 2006.
References:
1. David A Hodges, Horace G Jackson and Resve A Saleh, Analysis and Design of Digital
Integrated Circuits in Deep Submicron Technology TMH.2005
2. Sung-Mo Kang, Yusuf Leblebicii, CMOS Digital Integrated Circuits- Analysis and Design
McGraw-Hill International Edition.
Students admitted during 2009-2010
ANALOG IC DESIGN
L T P C
3 0 0 3
Objective:
To design analog IC components and building blocks in CMOS technology. To understand the relationships
between devices, circuits and systems. Emphasize the design of practical amplifiers, small systems and their
design parameter trade-offs.
Course outcomes:
A student who successfully fulfills the course requirements will have demonstrated:
an ability to analyze bias circuit using CMOS current mirror.
an ability to design feedback and differential operational amplifier.
an ability to analyze stability of operational amplifiers
an ability to apply frequency compensation techniques for Amplifiers
an ability to analyze basic operation of PLL.
Current source and Amplifier design:
MOS Device models, MOS Current Sources and Sinks, Current Mirror: Basic Current Mirrors,
Cascode current Mirrors. Current and Voltage Reference circuits. Single stage Amplifies: Basic
concepts, Common source stage, Common gate stage, Cascode stage. Differential stage: Single
ended and differential operation. Basic Differential Pair.
Feedback Amplifiers
Ideal feedback equation, Gain sensitivity, Effect of Negative Feedback on Distortion, Types of
Amplifiers. Feedback configurations: voltage-voltage, current-voltage, current-current, voltage-
current feedback. Practical configurations and Effect of loading.
Frequency response of Amplifiers
Miller effect, Frequency response of Common source stage, Common gate stage, Cascode stage and
Differential pair. Noise in single stage Amplifiers: Common source stage, Common gate stage,
Cascode stage. Differential pair, Noise Bandwidth.
Operational Amplifier
Differential and common mode circuits, Op Amp CMRR requirements, Need for single and
multistage amplifiers, Effect of loading in differential stage. Performance Analysis: dc gain,
frequency response, noise, mismatch, slew rate of cascode and two stage OP Amps, Fully
Differential Op Amps- Common-Mode feedback, loop stability.
Stability analysis and Frequency compensation
Stability of Feedback: Basic Concepts, Instability and the Nyquist Criterion, Stability Study for a
Frequency-Selective Feedback Network, Root Locus: Effect of Pole Locations on Stability,
multipole systems.
Frequency Compensation: Concepts and Techniques for Frequency Compensation Dominant pole,
Miller Compensation, Compensation of Miller RHP Zero, Nested Miller, Compensation of two stage
OP Amps.
Phase Locked Loops
Problem of Lock acquisition, Phase Detector, Basic PLL and its dynamics, Charge-pump PLL, Non-
ideal effects in PLL: PFD/CL non idealities, Jitter, Delay Locked Loop, Applications.
Text Books:
1. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.
2. Gray, Hurst, Lewis, and Meyer: Analysis and design of Analog Integrated Circuits, (4/e), John
Wiley and Sons
References:
1. Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, (Second Edition) Oxford
University Press, February 2002.
2. David Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997
Students admitted during 2009-2010
ASIC DESIGN
L T P C
3 0 0 3
Objective of the Course:
To study the issues relating to the design of application-specific integrated circuits (ASICS) for
digital systems.
Course Outcomes
After completion of this course
Students will be able to design and synthesize a complex digital functional block using
Verilog HDL.
Students will demonstrate an understanding of how to optimize the performance, area, and
power of a complex digital functional block, and the tradeoffs between these.
Students will demonstrate an understanding of issues involved in ASIC design, including
technology choice, Timing analysis, tool-flow, testability.
Introduction
Implementation Strategies for Digital ICs: Custom IC Design, Cell-based Design Methodology.
Array based implementation approaches. Traditional and Physical Compiler based ASIC Flow.
Digital ASIC Design using Verilog HDL
Verilog HDL: Levels of Abstraction, Hierarchical modeling and Delay modeling, Verilog constructs,
FSM, Memory modeling. Complex Digital System Design Examples.
RTL Simulation and Synthesis
Functional Simulation: Testbench Wrappers. Event-based Simulation: Event-based Simulation.
Cycle-based Simulation.
RTL Synthesis: An overview of the synthesis based ASIC design flow. Synthesis Environment.
technology library: technology libraries, logic library basics, delay calculations.
Partitioning and Coding Styles: Partitioning for synthesis, Coding guideline for synthesis. Logic
Inference: Order dependence. Optimization and mapping constraints (clock, delay, area, design).
Instantiating special operators and black boxes. FSM synthesis, Performance-driven synthesis.
Static Timing Analysis
Overview of timing verification and static timing analysis. Critical path. Timing exceptions.
Multicycle paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width).
Practical usage of timing analysis.
Design for Testability
Types of DFT. Scan Insertion. Design Rules, DFT guidelines. Built-in-Self-Test(BIST):Test pattern
Generation Exhaustive , Pseudo Random , Pseudo Exhaustive , Output Response Analysis , Logic
BIST architectures With and without scan chains , Register Reconfiguration , Boundary Scan and
core testing.
Text Books:
1. T.R.Padmanabhan, B.Bala Tripura Sundari, Design through Verilog HDL Wiley Interscience, 2004.
2. Himanshu. Bhatnagar, Advanced ASIC Chip Synthesis (2/e).KAP.2002
3. Farzad Nekoogar, Timing Verification of Application-Specific Integrated Circuits Farzad
Nekoogar, Prentice-Hall. 1999
4. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and Mixed-
Signal VLSI Circuits", KAP, 2000
References:
1. Donald E. Thomas, Philip R. Moorby, The Verilog Hardware Description Language (5/e) KAP.
2002
2. Maheshwari, Naresh, Sapatnekar, S Timing Analysis and Optimization of Sequential Circuits.
1998, Springer. ISBN: 978-0-7923-8321-5
3. Prime Time user guide
Students admitted during 2009-2010
VLSI DIGITAL SIGNAL PROCESSING
L T P C
3 0 0 3
Objective of the Course:
The objective of this course is to provide students, reviews of various DSP algorithms and addresses
their representation, and high-level architectural transformations and design of algorithm structures
for various DSP algorithms based on algorithm transformations.
Course Ourcomes:
Students understand the issues and methods associated with the sampling of continuous time
signals
Students can able to understand the finite world length effects and design redundant arithmatic
structures.
Students can able to understand the the algoithmic-architecture transoformation at higher level.
Able to understand the pipelines techniques and programable DSP Processors.
Introduction TO Digital Signal Processing
Introduction, A Digital signal-processing system, The sampling process, Discrete time sequences.
Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear time-invariant systems,
Digital filters : Realization of FIR and IIR systems, finite word length effects Scaling and Round off
noise.
Implementation of Arithmetic architectures
Bit Level Arithmetic Architectures: Parallel Multipliers, Interleaved Floor-plan and Bit-plan based
Digital Filters, Bit-Serial Multipliers, Bit Serial Filter Design and Implementation, Canonic Signed
Digit Arithmetic, Distributed Arithmetic.
Redundant Arithmetic: Redundant Number Representations, Carry-Free Radix-2 Addition and
Subtraction. Hybrid Radix-4 Addition, Radix-2 Hybrid Redundant Multiplication Architectures, Data
Format Conversion-Redundant to Non-Redundant Converter
Numerical Strength Reduction : Sub-Expression Elimination, Multiple Constant Multiplication, Sub-
Expression Sharing in Digital Filters, Additive and Multiplicative Number Splitting.
Architecture and Algorithm Transformations
Data flow graph representation, Iteration bounds Algorithms for computing Iteration bound,
Retiming. Unfolding. Folding. Algorithmic strength reduction in filters and transforms. Fast
convolution.
Reference Books:
1. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing-A practical approach,
Second edition, Pearson education, Asia 2001.
2. Keshab K.Parhi, VLSI Digital Signal Processing Systems: Design and
Implementation,Wiley, Inter Science, 1999.
3. J. Proakis and D. Manolakis, Digital Signal Processing PHI
4. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998.
5. Mohammed Ismail and Terri Fiez, Analog VLSI Signal and Information Processing Mc
Graw-Hill, 1994.
6. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing, PHI
Students admitted during 2009-2010
COMPUTER AIDED DESIGN FOR VLSI
L T P C
3 0 0 3
Course Objectives:
This course reviews the major components of the modern computer-aided circuit design flow. An important
motivation for the course is to explore the directions in which computer-aided circuit design evolves as it
copes with the challenges brought about by the increased complexity of deep submicron silicon technology.
Course Outcomes:
After the completion this course the students shall be able to
Understand the techniques and algorithms for physical and logic-level design automation.
Explain the optimization methods contemplate various performances such as silicon area, timing,
power consumption, and crosstalk.
Prerequisite to study the course:
Digital Design, Basic graph theory concepts, Data structure.
Introduction
Y Chart, Physical design top-down flow. Design styles: Full Custom, Standard Cell, Gate Arrays, Field
Programmable Gate Arrays, Sea of Gates.
Logic Synthesis and Technology Mapping
Computer-aided synthesis and optimization, Introduction to Combinational logic synthesis Binary decision
diagrams (BDD): Principles, Implementations and Construction, Manipulation, Variable ordering. Two-level
and multi-level logic optimizations. Sequential logic optimization.
Algorithms for Physical Design Automation
Partitioning: Problem formulation, Group Migration Algorithms Kernighan-Lin, Fiduccia-Mattheyses
algorithm, Performance driven Partitioning.
Floor Planning: Problem Formulation, Integer Programming, Rectangular dualization, Simulated Annealing
based floorplanning.
Placement: Breuers algorithm, Cluster Growth approach, Sequence pair technique.
Pin Assignment: General pin assignment, Channel pin assignment.
Routing: Global routing: Problem formulation, Maze routing, Line Probe algorithms, Weighted Steiner tree
approach.
Detailed routing: Problem formulation, Two layer channel routing Left Edge algorithm, Dogleg router, Net
Merge channel router, Three-layer channel routing HVH, VHV router. Introduction to switch box routing.
Over the Cell Routing: Two layer Over-the-cell routers.
Clock routing: Clocking schemes, Exact Zero skew algorithm.
Power and Ground routing
Compaction:
Problem formulation, One dimensional Compaction Constraint graph based, Virtual Grid based compaction,
Two dimensional compaction, Hierarchical compaction.
Timing Analysis
Static and Dynamic timing analysis for single and multiple path data flows. Compensation techniques. Critical
path delays. Back annotation.
Text Books:
1. Naveed Sherwani , Algorithms for VLSI Physical design automation, 3e, Springer International
edition, 2005.
2. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, 1
st
edition, McGraw-Hill, 1994
3. H. Yosuff and S.M. Sait, VLSI Physical Design Automation Theory and Practice, McGraw Hill
publication, 1995.
Reference Books:
1. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation Springer. 2008
2. Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson Education Asia,
2001.
3. Sabih. H. Gerez , Algorithms for VLSI design Automation, John Wiley & sons Ltd.,2004.
4. M.Sarrafzadeh, C.K.Wong, An introduction to VLSI physical design ,McGraw-Hill international
editions,1996.
Students admitted during 2009-2010
EMBEDDED SYSTEM DESIGN
L T P C
3 0 0 3
Introduction to Embedded System: An embedded system, processor, hardware unit, soft ware
embedded into a system, Example of an embedded system, OS services, Embedded Design life
cycle; Modeling embedded systems
Processor and Memory Organization: Structural unit in as processor, processor selection for an
embedded systems. Memory devices, memory selection for an embedded system, allocation of
memory to program statements and blocks and memory map of a system. Direct memory accesses.
Devices and Buses for Device Networks: I/O devices, serial communication using FC, CAN
devices, device drivers, parallel port device driver in a system, serial port device driver in a system,
device driver for internal programmable timing devices, interrupt servicing mechanism, V context
and periods for switching networked I/O devices using ISA, PCI deadline and interrupt latency and
advanced buses.
Programming Concepts and embedded programming in C: Languages, Firmware development
environment, Start up code or Boot loader, Abstraction Layers, Application Layer, build download
debug process of firmware.
Program Modeling Concepts in Single and Multiprocessor Systems: software development
process, modeling process for software analysis before software implementation, programming
model for the event controlled or response time constrained real time programs, modeling of
multiprocessor system.
Inter-Process Communication and Synchronization of Processors: Tasks and threads; multiple
process in an application, problems of sharing data by multiple tasks and routines, inter process
communications. RTOS task scheduling models interrupt literacy and response times, performance
metric in scheduling models, standardization of RTOS, list of basic functions, synchronization.
Reference Books:
1. Frank Vahid and Tony Givargis,Embedded System Design: A Unified Hardware/ Software
Approach, John Wiley ,2002.
2. Steve Heath , Embedded Systems Design, EDN Series ,2003.
3. David E simon, An Embedded Software Primer, 1st edition, Addison Wesley 1999.
4. Wayne Wolf Computers as components: Principles of Embedded Computing System
Design The Morgan Kaufmann Series in Computer Architecture and Design, 2008
5. Jane W. S., Liu, Real time systems, Pearson Education, 2000.
6. Raj Kamal, Embedded systems Architecture, Programming and design, Second Edition,
2008.
Students admitted during 2009-2010
VLSI DESIGN VERIFICATION AND TESTING
L T P C
3 0 0 3
Course Objective:
The objective of this course is to involve the students in the theory and practice of VLSI test and
verifications.
Course Outcome :
After the course the students will be familiar with the testing and verification methodology of
VLSI circuits.
Prerequisite:
Undergraduate level Digital Logic Design Course
Digital IC Design
Introduction
Scope of testing and verification in VLSI design process. Issues in test and verification of complex
chips, embedded cores and SOCs.
Design Verification Techniques
Design verification techniques based on simulation, analytical and formal approaches. Functional
verification: Timing verification. Formal verification. Physical Verification and Analysis. Basics of
equivalence checking and model checking. Hardware emulation.
Fault modeling and Test Generation
Defects, Errors, and Faults. Functional Versus Structural Testing. Levels of Fault Models. Single
Stuck-at Fault. Testability measures: Controllability and Observability. Fault Simulation: Serial,
Parallel, deductive, Concurrent, Differential Simulation. Combinational Test Generations: Random
Test generation, Redundancy Identification (RID). ATPG for Combinational Circuits: D-Algorithm,
PODEM. Sequential Circuit Test Generations: ATPG for single-clock synchronous circuits, Time-
frame expansion model, Designing a Sequential ATPG.
Advanced Testing
Analog and Mixed-Signal Circuit Trends. Functional DSP-Based Testing. Static ADC and DAC
Testing Methods. Analog Fault Models. Types of Analog Testing. Analog Fault Simulation. IDDQ
Test.
Text Books:
1. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and
Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000
2. Masahiro Fujita, Indradeep Ghosh, Mukul Prasad Verification Techniques for System-Level
Design Elsevier.
3. Prakash Rashinkar, Peter Paterson, Leena Singh, System-On-a-ChipVerification
Methodology and Techniques KLUWER ACADEMIC PUBLISHERS. 2002.
References
1. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable
Design", IEEE Press.
2. Michael Keating and Pierre Bricaud, Reusable Methodology Manual for System-on-a-chip
Designs, 2nd Edition, Kluwer Academic Publishers, 1999.
3. Parag K.Lala, Fault Tolerant and Fault Testable Hardware Design BS Publications, 2002
4. Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen , VLSI Test Principles and
Architectures: Design for Testability, Elsevier's Science & Technology publishing.
Students admitted during 2009-2010
CUSTOM IC DESIGN LAB
L T P C
0 0 2 1
Study of VLSI CAD Tools (Working environment, Introduction to Linux and vi editor,
Cadence Virtuoso ADE with Spectre simuulator/Mentor graphics Design Architect with Eldo
simulator)
Applying MOS I-V equations and small-signal models to MOS circuits
Analyzing switching characteristics and power consumption of the inverter
Analyzing and designing complex CMOS gates for speed
Designing an inverter chain to drive off-chip loads
Design and characterization of various digital blocks (combinational and sequential elements)
Physical Design of Analog and Digital cells (layout, DRC,LVS, RCX, Post-layout
simulation)
Designing current sources and analyzing differential amplifiers
Analysis and design of the CMOS 2-stage and folded-cascode op-amps
Mini-project:
Standard cell design
Working on a team to implement a small analog and digital VLSI project
Presenting the team project in front of peers
CAD Tools : Cadence, Mentor Graphics.
Students admitted during 2009-2010
ASIC DESIGN LAB
L T P C
0 0 2 1
Working with VLSI CAD Tools(like Cadence IUC, RTL Compiler, SoC Encounter,
ModelSim etc.)
EDA tools and design kit configuration
Design project organization
HDL examples
Text editing
Design flow steps
Verilog simulation
Digital System Design using Verilog HDL
RTL synthesis
Starting the Design Vision graphical environment
RTL model analysis
Design elaboration
Design environment definition
Design constraint definitions
Design mapping and optimization
Analyze and resolve design problems
Report generation
VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF)
extraction
Design constraints generation for placement and routing
Design optimization with tighter constraints using scripts
Standard cell placement and routing
Starting the Encounter graphical environment
Design import
Global net connections
Operating conditions definition
Floorplan Specification
Power ring/stripe creation and routing
Core cell placement
Timing analysis
Clock tree synthesis (optional)
Design routing
Timing analysis
Design checks
Report generation
Post-route timing data extraction
Post-route netlist generation
GDS2 file generation
Proto-typing of a design using FPGA Design Kit
Working on a team to implement a Digital System design project
Students admitted during 2009-2010
VLSI DIGITAL SIGNAL PROCESSING LAB
L T P C
0 0 2 1
Simulation Experiments using Matlab.(3 sessions)
1) Generation of Periodic signals using Fourier synthesis Equation.
2) Implementation of Fourier Transform for basic finite interval pulses.
3) Spectrum analysis of multi tone sinusoidal signal using Discrete Fourier Transform.
4) Implementation of FFT radix-2 Algorithms.
5) Realization of various structure of FIR and IIR systems using Matlab functions.
Real time experiments using TMS6713 Processor. (3 sessions)
1) Implementation of Digital filters in TMS6713 Processor using C programming in cc-studio
for real time processing of audio signals
2) Study of parallel processing and pipeline processing features of TMS6713 Processor.
Simulation Experiment using VHDL/ Verilog.(3 sessions)
1) Behavioral and Dataflow models for adders and multipliers for 8 bit
signed 2s compliment arithmetic.
2) Structural models for FIR filters using direct form realization and Data Broadcast realization.
Mini Projects:
Titles on focus:
1) Implementation of Optimum multipliers.
2) Implementation of redundant Arithmetic units.
3) Implementation of FFT processor.
4) Implementation of 2D-DCT Processor.
5) Implementation Algorithm for retiming for clock minimization.
6) Implementation of Optimum Digital filters using sub expression sharing and Canonic signed
digit arithmetic.
7) Development of optimum assembly level coding exploiting the parallel processing features of
TMS6713 Processor for signal processing application.
8) Study and implementation of CORDIC algorithm for trigonometry functions.
9) Study and implementation of Systolic Architectures for Bit serial systems.
10) Audio interfacing and basic filtering operation using FPGA.
Note:
The student should do a compulsory mini project on above titles.
Other related topics can also be selected.
The duration for mini project is 3 months from the first day of the laboratory.
As a part of the mini project a detailed project report has to be submitted after ompletion
of the project.
Students admitted during 2009-2010
EMBEDDED SYSTEM DESIGN LAB
L T P C
0 0 2 1
1. Software development tools - Introduction to cross assembler, Linker, Locator and
conversion utility
2. Assembly Language Programming
3. Interface to Switches, LEDs, and 7-segment displays
4. Interface to a Hexadecimal Keypad
5. Writing programs to perform user output to the LCD
6. Interfacing EEPROM/NVRAM to a typical microcontroller
7. Testing EEPROM/NVRAM access and performing user I/O
8. Writing Interrupt Service Routines
9. RS-232, RS-485, I2C Communication
Students admitted during 2009-2010
LOW POWER IC DESIGN
L T P C
3 0 0 3
Course Objectives:
To gain a sound knowledge of the sources of power consumption in UDSM CMOS designs and to
develop a broad insight into the methods used to confront the low power issue from lower level
(circuit level) to higher levels (system level) of abstraction.
Course Learning Outcomes:
Design a power efficient system in reasonable trade off.
Estimate and Analyze the power consumed in the circuit level
Construct a system with multiple supply and multiple threshold voltages.
Optimizing the code to reduce the power in the software level.
Pre-Requisite Courses: i) Digital IC Design, ii) Computational Techniques
Low Power Design Methods
Motivation, Context and Objectives, Sources of Power dissipation in Ultra Deep Submicron CMOS Circuits
Static, Dynamic and Short circuit components. Effects of scaling on power consumption, Low power design
flow, Normalized Figure of Merit (PDP, EDP), Power optimization at Algorithmic level, Architectural level,
Register Transfer level, Logic level and Circuit level. Power Estimation using Static and Dynamic techniques,
Hierarchical sequence compaction for reducing power simulation time.
Algorithmic and Architecture Level Optimization
Hardware/Software co-design, Pipelining and Parallel Processing approaches for low power in DSP filter
structures, Multiple supply voltage and Multiple threshold voltage designs for low power, Optimal drivers of
high speed low power ICs, Computer arithmetic techniques for low power.
Sleep Transistor Design
Design metrics, switch efficiency, area efficiency, IR drop, normal Vs reverse body bias. Layout design of
Area efficiency, Single row Vs double row, Inrush current and current latency.
Register Transfer Level Optimization
Low power clock, Interconnect and layout designs, Reducing power consumption in memory cells, Clock
gating, Deglitching for low power, Bus Encoding techniques.
Logic Level and Circuit Level Optimization
Theoretical background Calculation of Steady state probability, Transition probability, Conditional
probability, Transition density; Estimation and optimization of Switching activity, Power cost computation
model, Transistor variable re-ordering for power reduction, Low power library cell design (GDI).
Low Power Design of Sub-Modules
Circuit techniques for reducing power consumption in Adders, Multipliers. Synthesis of FSM for low power,
Retiming sequential circuits for low power.
IP Design for Low Power
Architecture and partitioning for power gating, power controller design for the USB OTG, Issues in designing
portable power controllers, clocks and resets, Packaging IP for reuse with power intent.
Software Level Power Optimization
Power analysis of embedded software, OS issues, Power management techniques.
Text Books:
1. Kaushik Roy, Sharat Prasad, Low Power CMOS VLSI circuit design, John Wiley and Sons Inc., 2000.
2. Soudris, Dimitrios, Christrian Pignet, Goutis, Costas, Designing CMOS circuits for low power, Springer
International, 2004.
Reference Books:
1. G.K.Yeap, Farid N.Najm, Low Power VLSI design and technology, World Scientific Publishing, 1996.
2. A.P.Chandrakasan, R.W.Broderson, Low Power Digital VLSI Design, IEEE Press, 1998.
3. Gary K.Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Press, 1998.
4. Jan M.Rabaey, Massoud Pedram, Low power Design methodologies, Kluwer Academic Press, 1996
5. Michael Keating, David Flynn Low Power Methodology Manual for System-On-Chip Design Springer
Publication 2007
Students admitted during 2009-2010
MIXED SIGNAL IC DESIGN
L T P C
3 0 0 3
Objective:
This course covers many aspects of the design of dynamic analog circuits and analog-digital interface
electronics in CMOS technology. It covers the specification and design of analog-to-digital and digital-analog
converters and several sample converter implementations in detail.
Course outcomes:
A student who successfully fulfills the course requirements will have:
i. an ability to design Sample and Hold circuits.
ii. an ability to design Switched Capacitor Amplifiers and analysis its non idealities.
iii. an ability to design various types of ADC/DAC for a given specification
iv. an ability to design a oversampling converter considering all the practical issues for the given
specification.
Prerequisite: Analog IC Design.
Sampling
Introduction, sampling, Spectral properties of sampled signals, Oversampling Anti-alias filter design. Time
Interleaved Sampling, Ping-pong Sampling System, Analysis of offset and gain errors in Time Interleaved
Sample and Hold. Sampling circuits- Distortion due to switch, Charge injection, Thermal noise in sample and
holds, Bottom plate sampling, Gate bootstrapped switch, Nakagome charge pump. Characterizing Sample and
hold, Choice of input frequency.
Switched Capacitor Amplifiers
Switched Capacitor (SC) circuits Parasitic Insensitive Switched Capacitor amplifiers, Non idealities in SC
Amplifiers Finite gain, DC offset, Gain- Bandwidth Product. Fully differential SC circuits, DC negative
feedback in SC circuits.
Analog to Digital Converter
Data converter fundamentals: Offset and gain Error, Linearity errors, Dynamic Characteristics, SQNR,
Quantization noise spectrum. Flash ADC, Regenerative latch, Preamp offset correction, Preamp Design,
necessity of up-front sample and hold for good dynamic performance. Folding ADC, Multiple-Bit Pipeline
ADCs.
Digital to Analog Converter
Linearity errors, DAC spectra and pulse shapes. NRZ vs RZ DACs. DAC Architectures: Binary weighted,
Thermometer DAC, Current steering DAC Current cell design in current steering DAC, Charge Scaling
DAC, Pipeline DAC.
Oversampling Converter
Benefits of Oversampling, Oversampling with Noise Shaping, Signal and Noise Transfer Functions, First and
Second Order Delta-Sigma Converters. Signal Dependent Stability of Describing Function Method.
Introduction to Continuous-time Delta Sigma Modulators, time-scaling, inherent anti-aliasing property,
Excess Loop Delay, Time-constant changes, Influence of Op amp nonidealities. Effect of OP Amp
nonidealities - finite gain bandwidth, Effect of ADC and DAC nonidealities. Dynamic Element Matching -
Dynamic Element Matching by Data Weighted Averaging, Effect of Clock jitter.
Text Books:
1. M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converters for Communication Kluwer
Academic Publishers, 2000.
2. Behzad Razavi, Principles of Data Conversion System Design Wiley-IEEE Press, 1994.
3. David A.Johns, Ken Martin, Analog Integrated Circuit Design John Wiley & Sons Inc. 1997
Reference Books:
1. R.Jacob Baker, CMOS Mixed Signal Circuit Design, IEEE Press Series on Microelectronic
Systems, 2002.
2. Andrzej Handkiewicz, Mixed Signal Systems A Guide to CMOS Circuit Design, IEEE Press
Series on Microelectronic Systems, 2003.
3. Van de Plsddvhr, Rudy J, CMOS Integrated A/D and D/A Converters BS Publications,2005
Students admitted during 2009-2010
IC TECHNOLOGY
L T P C
3 0 0 3
Course Objectives:
This course introduces students to the fundamentals of VLSI manufacturing processes and
technology.
Course Outcomes:
After the completion of this course, Students will be able to
Understand physics of the Crystal growth, wafer fabrication and basic properties of silicon
wafers.
Learning lithography techniques and concepts of wafer exposure system, types of resists etc.
Understand Concepts of thermal oxidation and Si/SiO2 interface and its quality
measurements.
Learn concepts of thin film deposition including chemical Vapor Deposition and Physical
vapor deposition.
Understand back-end technology to define contacts, interconnect, gates, source and drain, and
measurements techniques to insure quality of designs.
Understand MOS and Bipolar Process Integration.
Introduction
Introduction to Semiconductor Manufacturing and fabrication. Physics of the Crystal growth, wafer
fabrication and basic properties of silicon wafers.
Lithography, Thermal Oxidation of Silicon
The Photolithographic Process, Etching Techniques, Photomask Fabrication, Exposure Systems,
Exposure sources, The Oxidation Process, Modeling Oxidation, Masking Properties of Silicon
Dioxide, Technology of Oxidation, Si-SiO2 Interface.
Diffusion, Ion Implantation, Film Deposition
The Diffusion Process , Mathematical Model for Diffusion, Constant- ,The Diffusion Coefficient ,
Successive Diffusions, Diffusion Systems, Implantation Technology, Mathematical Model for Ion
Implantation, Selective Implantation, Channeling, Lattice Damage and Annealing, Shallow
Implantations, Chemical Vapor Deposition, Physical Vapor Deposition, Epitaxy.
Interconnections and Contacts, Packaging and Yield
Metal Interconnections and Contact Technology, Diffused Interconnections, Polysilicon
Interconnections and Buried Contacts, Silicides and Multilayer-Contact Technology, Copper
Interconnects and Damascene Processes, Wafer Thinning and Die Separation, Die Attachment, Wire
Bonding, Packages, Yield.
MOS Process Integration, Bipolar Process Integration
Basic MOS Device Considerations, MOS Transistor Layout and Design Rules, Complementary
MOS (CMOS) Technology, The Junction-Isolated Structure, Current Gain, Transit Time, Basewidth,
Breakdown Voltages, Other Elements In SBC Technology, Advanced Bipolar Structures, Other
Bipolar Isolation Techniques. Deep Submicron Processes, Low-Voltage/Low-Power
CMOS/BiCMOS Processes. Future Trends and Directions of CMOS/BiCMOS Processes.
Text Books:
1. J. Plummer, Michael D. Deal and Peter B. Griffin, Silicon VLSI Technology, fundamentals,
practice and modeling Pearson Education, 2009.
2. Richard C. Jaeger , Introduction to Microelectronic Fabrication, Second Edition
Reference Books:
1. C.Y. Chang and S. M. Sze, ULSI Technology, McGraw Hill 1996
2. S.K. Ghandhi, VLSI Fabrication Principles, Wiley. 2nd edition 1994
3. Stanley wolf , Silicon Processing for VLSI era, volume 4, Deep sub-micron process
technology Lattice Press.1990
Students admitted during 2009-2010
PACKAGING AND INTERCONNECT ANALYSIS
Objective of the Course:
To have the students develop a fundamental understanding of the basic principles
used in the packaging of modern electronics so that when faced with a packaging issue they can recognize the
various methods available and perform the tradeoffs necessary to select the appropriate/optimum packaging
solution for the applications.
Prerequisite to study the course: An undergraduate degree in a scientific or engineering area, including
familiarity with computer-aided design and engineering analysis methods for electronic circuits and systems.
Course Outcomes
Students master fundamental knowledge of electronic packaging including package styles, hierarchy, and
methods of package necessary for various environments.
Basic understanding and application of electronic packaging models and electrical performance concepts
such as impedance, loss, time delay, rise time, etc.