Simulation

The Simulation of the VHDL model for the FFT processor can be done with the following software. ModelSim SE 6.2c for timing simulation

4.4.1 ModelSim SE 6.2c The basic steps for simulating a design in Modelsim Creating the working library Compiling the design Running the simulation

Loading and simulating the design directory Step 1: Select File Change Directory and change to the directory.

Step 2: give the path of the directory

Figure 10 choosing the directory Here the library automatically loaded

Figure 11.showing the work library

When the design is loaded, we see a new tab named sim that displays the hierarchical structure of the design (Figure 7). You can navigate within the hierarchy by clicking on any line with a + (expand) or - (contract) icon. You will also see a tab named Files that displays all files included in the design. ModelSim creates a directory called work and writes a specially-formatted file named info into that directory

Figure 12 command in the transcript pane Step 3: in the Main window Transcript pane: following commands will be given dir *do do build.do enter enter

figure 13 modelsim simulation result

Figure the final setup

Figure 14 set up of the final step The host computer with Chipscope Pro software is connected Spartan 3e with cable. By using impact tool is used for device configuration and file generation.

4.5 iMPACT : It is a tool featuring batch and GUI operations, allows you to perform two
basic functions: Device Configuration and File Generation. The Device Configuration enables you to directly configure Xilinx FPGAs or program Xilinx CPLDs and PROMs with the Xilinx cables (MutiPRO Desktop Tool, Parallel Cable IV, or Platform Cable USB) in various modes. In the Boundary-Scan mode, Xilinx FPGAs, CPLDs, and PROMs can be configured or programmed. In the Slave Serial or SelectMAP configuration

modes only FPGAs can be configured directly. In the Desktop Configuration mode Xilinx CPLDs or ROPMs can be programmed. In the Direct SPI Configuration mode select SPI serial flash (STMicro: M25P, M25PE, M45PE or Atmel: AT45DB) can be programmed. File Generation enables you to create the following types of programming files; System ACE CF, PROM, SVF, STAPL, and XSVF files. iMPACT also enables you to do the following:

Readback and verify design configuration data Debug configuration problems Execute SVF and XSVF files

Step 1: start programs Impact Step 2: file menu create new project ok finish

Figure 15 file generation using iMPACT Step 3 : select the bit file location selectopen

Warning appears click ok Step 4: click bypass, click ok, the message appears program succeeded

4 .6 ChipScope After installing ChipScope,: double-click to startChipScope. The main window of ChipScope Pro opens: First, the JTAG connection must be made: JTAG Chain Xilinx platform USB cableok

Figure 16 chipscope pro initializing

chipscope window appears after device detection took place

figure 17 bus plot of chipScope pro analyzer