Clock latency vs. clock uncertainty =================================== Source: http://www.edaboard.com/thread130000.

html Let me try to clear up some of the confusing terminology - clear terminology all ows for clear thinking. The first important point is that there are two phases in the design of a clock signal. At first the clock is in "ideal mode" (e.g.: during RTL design, during s ynthesis and during placement). An "ideal" clock has no physical distribution tr ee, it just shows up magically on time at all the clock pins. The second phase comes when clock tree synthesis (CTS) inserts an actual tree of buffers into the design that carries the clock signal from the clock source pin to the (thousands) of flip-flops that need to get it. CTS is done after placeme nt and before routing. After CTS is finished, the clock is said to be in "propag ated mode". Now we can get to your questions: What is clock latency? Clock latency is an ideal mode term. It refers to the del ay that is specified to exist between the source of the clock signal and the fli p-flop clock pin. This is a delay specified by the user - not a real, measured t hing. (In fact there is 'clock source latency' and 'clock network latency' - the difference is not important for this discussion). When the clock is actually cr eated, then that same delay is now referred to as the "insertion delay". Inserti on delay (ID) is a real, measurable delay path through a tree of buffers. Someti mes the clock latency is interpreted as a desired target value for the insertion delay. What is clock uncertainty? In ideal mode the clock signal can arrive at all cloc k pins simultaneously. But in fact, that perfection is not achievable. So, to an ticipate the fact that the clock will arrive at different times at different clo ck pins, the "ideal mode" clock assumes a clock uncertainty. For example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arriv e in 1 ns plus or minus 50 ps. A deeper question gets into *why* the clock does not always arrive exactly one c lock period later. There are several possible reasons but I will list 3 major on es: (a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through t he clock tree can be longer than another path). This is called clock skew. (b) The clock period is not constant. Some clock cycles are longer or shorter th an others in a random fashion. This is called clock jitter. (c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variatio n. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increase s the clock skew.