SEMICONDUCTOR TECHNICAL DATA

 
   




L SUFFIX
CERAMIC
CASE 632

The MC14016B quad bilateral switch is constructed with MOS Pchannel

and Nchannel enhancement mode devices in a single monolithic structure.
Each MC14016B consists of four independent switches capable of
controlling either digital or analog signals. The quad bilateral switch is used
in signal gating, chopper, modulator, demodulator and CMOS logic
implementation.

P SUFFIX
PLASTIC
CASE 646

Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linearized Transfer Characteristics
Low Noise 12 nV/Cycle, f 1.0 kHz typical
PinforPin Replacements for CD4016B, CD4066B (Note improved
transfer characteristic design causes more parasitic coupling
capacitance than CD4016)
For Lower RON, Use The HC4016 HighSpeed CMOS Device or The
MC14066B
This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken.

D SUFFIX
SOIC
CASE 751A

ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Plastic
Ceramic
SOIC

TA = 55 to 125C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol

VDD
Vin, Vout
lin

Parameter

DC Supply Voltage

Input or Output Voltage (DC or Transient)

Value

Unit

0.5 to + 18.0

0.5 to VDD + 0.5

Input Current (DC or Transient),

per Control Pin

10

mA

Isw
PD

Switch Through Current

25

mA

Tstg
TL

Storage Temperature

Power Dissipation, per Package

500

mW

65 to + 150

_C

260

_C

Lead Temperature (8Second Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM
CONTROL 1
IN 1
CONTROL 2
IN 2
CONTROL 3
IN 3
CONTROL 4
IN 4

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)

13
2
OUT 1

1
5
3

OUT 2

4
6
9

OUT 3

8
12
10

OUT 4

11
VDD = PIN 14
VSS = PIN 7

Control

Switch

0 = VSS

Off

1 = VDD

On

OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS
VSS Vin VDD
VSS Vout VDD

IN

REV 3
1/94

MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA

MC14016B
65

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Input Voltage
Control Input

Min

Typ #

Max

Min

Max

Unit

VIL

5.0
10
15

1.5
1.5
1.5

0.9
0.9
0.9

Vdc

VIH

5.0
10
15

3.0
8.0
13

2.0
6.0
11

Vdc

15

0.1

0.00001

0.1

1.0

Adc

5.0
5.0
5.0
0.2

5.0
10
15

0.25
0.5
1.0

0.0005
0.0010
0.0015

0.25
0.5
1.0

7.5
15
30

5.0

600
600
600

300
300
280

660
660
660

840
840
840

7.5

360
360
360

240
240
180

400
400
400

520
520
520

10

600
600
600

260
310
310

660
660
660

840
840
840

15

360
360
360

260
260
300

400
400
400

520
520
520

Iin

Input Capacitance
Control
Switch Input
Switch Output
Feed Through

Cin

Quiescent Current
(Per Package)

2,3

IDD

4,5,6

RON

(Vin = + 7.5 Vdc)

(Vin = 7.5 Vdc) VSS = 7.5 Vdc
(Vin = 0.25 Vdc)
(Vin = + 10 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 5.6 Vdc)
(Vin = + 15 Vdc)
(Vin = + 0.25 Vdc) VSS = 0 Vdc
(Vin = + 9.3 Vdc)

Input/Output Leakage Current

(VC = VSS)
(Vin = + 7.5, Vout = 7.5 Vdc)
(Vin = 7.5, Vout = + 7.5 Vdc)

125_C

Max

ON Resistance
Between any 2 circuits in a common
package
(VC = VDD)
(Vin = 5.0 Vdc, VSS = 5.0 Vdc)
(Vin = 7.5 Vdc, VSS = 7.5 Vdc)

25_C

Min

Symbol

Input Current Control

ON Resistance
(VC = VDD, RL = 10 k)
(Vin = + 5.0 Vdc)
(Vin = 5.0 Vdc) VSS = 5.0 Vdc
(Vin = 0.25 Vdc)

55_C

VDD
Vdc

Figure

pF

Adc

Ohms

RON

Ohms

5.0
7.5

15
10

Adc

7.5
7.5

0.1
0.1

0.0015
0.0015

0.1
0.1

1.0
1.0

NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
** For voltage drops across the switch (V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.

MC14016B
66

MOTOROLA CMOS LOGIC DATA

ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic

VDD
Vdc

Min

Typ #

Max

Unit

tPLH,
tPHL

5.0
10
15

15
7.0
6.0

45
15
12

ns

tPHZ,
tPLZ,
tPZH,
tPZL

5.0
10
15

34
20
15

90
45
35

5.0
10
15

30
50
100

mV

5.0

80

dB

10,11

5.0
10
15

24
25
30

nV/Cycle

5.0
10
15

12
12
15

0.16

Figure

Symbol

Propagation Delay Time (VSS = 0 Vdc)

Vin to Vout
(VC = VDD, RL = 10 k)

Control to Output
(Vin
10 Vdc, RL = 10 k)

Crosstalk, Control to Output (VSS = 0 Vdc)

(VC = VDD, Rin = 10 k, Rout = 10 k,
f = 1.0 kHz)

Crosstalk between any two switches (VSS = 0 Vdc)

(RL = 1.0 k, f = 1.0 MHz,
V
crosstalk
20 log10 out1)
Vout2
Noise Voltage (VSS = 0 Vdc)
(VC = VDD, f = 100 Hz)
(VC = VDD, f = 100 kHz)

ns

Second Harmonic Distortion (VSS = 5.0 Vdc)

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 k, f = 1.0 kHz)

5.0

Insertion Loss (VC = VDD, Vin = 1.77 Vdc,

VSS = 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
V
Iloss
20 log10 out)
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)

12

5.0

Bandwidth ( 3.0 dB)

(VC = VDD, Vin = 1.77 Vdc, VSS = 5.0 Vdc,
RMS centered @ 0.0 Vdc)
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)

dB

12,13

BW

2.3
0.2
0.1
0.05

5.0

MHz

OFF Channel Feedthrough Attenuation

(VSS = 5.0 Vdc)
Vout
50 dB)
(VC = VSS, 20 log10
Vin
(RL = 1.0 k)
(RL = 10 k)
(RL = 100 k)
(RL = 1.0 M)

54
40
38
37

5.0

kHz

1250
140
18
2.0

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

PIN ASSIGNMENT

MOTOROLA CMOS LOGIC DATA

IN 1

14

VDD

OUT 1

13

CONTROL 1

OUT 2

12

CONTROL 4

IN 2

11

IN 4

CONTROL 2

10

OUT 4

CONTROL 3

OUT 3

VSS

IN 3

MC14016B
67

VC

IS
Vin

Vout

VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 1. Input Voltage Test Circuit

10,000
PD , POWER DISSIPATION (W)

VDD = 15 Vdc
VDD

ID

PULSE
GENERATOR

TO ALL
4 CIRCUITS

VDD

Vout
10 k

CONTROL
INPUT

fc
VSS

TA = 25C

5.0 Vdc

1000

100

10

1.0
5.0 k 10 k

Vin

PD = VDD x ID

10 Vdc

Figure 2. Quiescent Power Dissipation

Test Circuit

100 k
1.0 M
fc, FREQUENCY (Hz)

10 M

50 M

Figure 3. Typical Power Dissipation per Circuit

(1/4 of device shown)

TYPICAL RON versus INPUT VOLTAGE

700
RL = 10 k
TA = 25C

600

R ON, ON RESISTANCE (OHMS)

R ON, ON RESISTANCE (OHMS)

700

500
400

VC = VDD = 5.0 Vdc

VSS = 5.0 Vdc

300
200
100
0
10 8.0

VC = VDD = 7.5 Vdc

VSS = 7.5 Vdc

500
400

VC = VDD = 10 Vdc

300
200

VC = VDD = 15 Vdc

100
0

4.0
0
4.0
Vin, INPUT VOLTAGE (Vdc)

Figure 4. VSS = 5.0 V and 7.5 V

MC14016B
68

VSS = 0 Vdc
RL = 10 k
TA = 25C

600

8.0

10

2.0

6.0
10
14
Vin, INPUT VOLTAGE (Vdc)

18

20

Figure 5. VSS = 0 V

MOTOROLA CMOS LOGIC DATA

Vout
RL

CL

Vin
Vout

20 ns
RL

20 ns
90%
50%

Vin

VC

tPLH

Figure 6. RON Characteristics

Test Circuit

10%

tPHL

VSS

50%

Vout

Vin

VDD

Figure 7. Propagation Delay Test Circuit

and Waveforms

Vout
VC

RL

CL

VX

Vin
20 ns
50%

VC

10%
tPZL

10 k

VC

15 pF

Vin

tPLZ
1k

90%

Vout

Vout

VSS
tPHZ
Vin = VDD
90%
Vx = VSS

tPZH
Vout

VDD

90%
10%

10%

Vin = VSS
Vx = VDD

Figure 8. TurnOn Delay Time Test Circuit

and Waveforms

Figure 9. Crosstalk Test Circuit

35

OUT
VC = VDD
IN

QUANTECH
MODEL
2283
OR EQUIV

NOISE VOLTAGE (nV/ CYCLE)

30

VDD = 15 Vdc

25
10 Vdc
20
5.0 Vdc

15
10
5.0
0
10

Figure 10. Noise Voltage Test Circuit

MOTOROLA CMOS LOGIC DATA

100

1.0 k
f, FREQUENCY (Hz)

10 k

100 k

Figure 11. Typical Noise Characteristics

MC14016B
69

2.0
TYPICAL INSERTION LOSS (dB)

RL = 1 M AND 100 k
0
10 k
2.0
1.0 k
4.0

3.0 dB (RL = 1.0 M )

6.0

3.0 dB (RL = 10 k )

Vout

8.0
10

Vin

12
10 k

100 k
1.0 M
10 M
fin, INPUT FREQUENCY (Hz)

RL

VC

3.0 dB (RL = 1.0 k )

100 M

Figure 12. Typical Insertion Loss/Bandwidth

Characteristics

+ 2.5 Vdc
0.0 Vdc
2.5 Vdc

Figure 13. Frequency Response Test Circuit

ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V

SOURCE

Figure 14. V Across Switch

MC14016B
70

MOTOROLA CMOS LOGIC DATA

APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0to5 V
Digital Control signal is used to directly control a 5 V pp analog signal.
The digital control logic levels are determined by V DD and
V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V logic high at
the control inputs; VSS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and V SS. The analog voltage must not swing higher than
V DD or lower than VSS.

The example shows a 5 V pp signal which allows no

margin at either peak. If voltage transients above V DD and/or
below V SS are anticipated on the analog channels, external
diodes (Dx) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.
The absolute maximum potential difference between V DD
and VSS is 18.0 V. Most parameters are specified up to 15 V
which is the recommended maximum difference between
V DD and V SS.

+5 V

VDD
+5 V

5 Vpp
ANALOG SIGNAL

EXTERNAL
CMOS
DIGITAL
CIRCUITRY

VSS

SWITCH
IN
SWITCH
OUT

+ 5.0 V

5 Vpp
ANALOG SIGNAL

+ 2.5 V

0TO5 V DIGITAL

GND

CONTROL SIGNALS

MC14016B

Figure A. Application Example

VDD

VDD
Dx

Dx
SWITCH
IN

SWITCH
OUT

Dx

VSS

Dx

VSS

Figure B. External Germanium or Schottky Clipping Diodes

MOTOROLA CMOS LOGIC DATA

MC14016B
71

OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 63208
ISSUE Y

A
14

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

SEATING
PLANE

G
D

M
J

14 PL

0.25 (0.010)

T A

14 PL

0.25 (0.010)

T B

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE L
14

A
F

L
C
J

N
H

MC14016B
72

SEATING
PLANE

K
M

DIM
A
B
C
D
F
G
J
K
L
M
N

INCHES
MIN
MAX
0.750
0.785
0.245
0.280
0.155
0.200
0.015
0.020
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15_
0.020
0.040

MILLIMETERS
MIN
MAX
19.05
19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15_
0.51
1.01

NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039

MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

A
14

B
1

P 7 PL
0.25 (0.010)

T
0.25 (0.010)

D 14 PL
M

T B

R X 45 _

SEATING
PLANE

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent
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MOTOROLA CMOS LOGIC DATA

*MC14016B/D*

MC14016B
MC14016B/D
73