VLSI Logic Circuits and Graph Theory

Poorva Waingankar Chandrashekhar V. Joshi Sagar P. Patil

Thakur College of Engineering and Rohidas Patil Institute of Rohidas Patil Institute of Technology Management Studies, Management Studies, Kandivali (East) Bhayandar (East) Bhayandar (East) Mumbai-400101 District Thane, Pin Code-401105 District Thane, Pin Code-401105 Telephone number, +912228461891 Telephone number, +919930829297 Telephone number, +918655132363 poorva.waingankar@thakureducation jchandrashekhar@yahoo.com sappatil_87@yahoo.co.in .org

ABSTRACT
Graph theory is intimately related to many branches of mathematics. It is widely applied in subjects like, Computer Technology, Communication Science, Electrical Engineering, Physics, Architecture, Operations Research, Economics, Sociology, Genetics, etc. In the earlier stages it was called Slum Topology. VLSI technology has made great advances during the last ten years. This progress makes it more and more difficult to design a VLSI within a reasonably short turnaround time. Design automation systems will be indispensable in order to obtain an error free VLSI design within a practical time. Hierarchical and systematic use of well-designed CAD programs currently realizes the high density and high performance VLSI design. This kind of design method includes a man-made interactive phase at various design stages. VLSI logic circuit shall be represented as a graph. Logic gates, input and output terminals are expressed as vertices in the graph. Interconnecting wires are represented as directed edges denoting the signal flow. In this paper we have attempted to show the analogy between VLSI logic circuit viz-a-viz its representation through a directed graph and evaluation of the shortest path.

strong foundations and contributed much to the development of the subject [1]. In the eighteenth century, Knigsberg was the capital of East Prussia. The Pregel River flowed through town and split into two branches around Kneiphof Island, which is labeled A in Figure 1. Seven bridges crossed the river, providing links among the four land masses labeled A, B, C, D in the Figure 1. People wondered if it were possible to start on one of the land masses, walk over each of the seven bridges exactly once, and return to the starting point (without getting wet) [1].

Figure 1: Koneiphof Island For the Konigsberg Bridge Problem, Euler's idea was to realize that the physical layout of land, water and bridges could be modeled by the graph shown in Figure 2. The land masses are represented by small circles (or vertices) and the bridges by lines (or edges) which can be straight or curved. By means of this graph (Figure 2), the physical problem is transformed into this mathematical one.

General Terms
VLSI, Logic Circuit, Minimum Spanning Tree

Keywords
VLSI Logic Circuits, Graph Theory, Propagation Delay, Kruskals Algorithm, QoS

1. INTRODUCTION
Euler, Cayley, Sir William Hamilton, Lewin, and Kirchoff, laid foundations to the graph theory. Graph theory was born in 1736 with Eulers paper on Konigsberg bridge problem. The Konigsberg bridge problem is the best known example in graph theory. It was a long pending problem. Euler solved this problem by means of a graph. Euler became father of graph theory. Kirchoff, Cayley, Mobius, Hamilton and De Morgan have laid Figure 2: Konigsberg Bridge Graph Hence the term "graph" represents objects together with their mutual links was introduced by the famous Hungarian mathematician D. Koenig [1].

The main aim of this paper is to understand the implementation of VLSI Logic Circuits using Graph Theory. The VLSI logic circuit shall be represented as a graph. Logic gates, input and output terminals are expressed as vertices in the graph. Interconnecting wires are represented as directed edges denoting the signal flow. The Boolean algebra logic forms the basis for computation in modern VLSI circuits and is used to understand the methodology of representing any algorithm, or any VLSI circuit, using a system of Boolean equations. The VLSI circuit representation is to be understood as a connected graph and as well as understanding of the Kruskals Algorithm for finding the minimum spanning tree thus the propagation delay for the connected graph shall be developed. The Kruskals Algorithm has been selected because it is simple, even though there are other algorithms about finding the minimum spanning tree on a directed graph.

The graphical representation of the reduced VLSI circuit with representative propagation delays is shown in Figure 4 for original circuit of Figure 3.

2. METHODOLOGY
Chris Chu, Evangeline F k Youngt, Dennis K. X Tongt and Sampath Dechul[2] argued that a sequential circuit can be represented by a directed graph G(v,E), where each node (v) corresponds to a combinational gate, and each directed edge (E) represents a connection from the output of one gate to the input of other gate, through zero or more registers. Without loss of generality, Chris Chu et. al,[2] assumed that the graph G is strongly connected. If not, a source node s can be added and connected to all primary inputs through an added target node f and connecting all primary outputs to it and connecting f to s. Then the resulting graph is strongly connected. Chris Chu et. al [2], first replaced each gate by a wire of the same delay and then solved the problem with only interconnect delay optimally and efficiently. Chris Chu et. al [2] used the basic idea to reduce the size of G by compacting some paths into edges by applying the Bellman-Ford algorithm by representing the VLSI circuit gates by wires as the edges on the graph. The examples in Figure 3 show the VLSI circuits and their corresponding graphs. This VLSI circuit using the Boolean expression [4] and K-Map rules can be simplified as shown in Figure 3. Figure 4: VLSI Circuit Graph 1 The propagation delays in ns have been assumed as edge weights for the representation of Figure 4. Total propagation delay of 15+20+15+20+20+22=112ns. the circuit (Figure 4) is

Figure 5: VLSI Circuit Graph 2 Total propagation delay of the reduced circuit (Figure 5) is 22ns using K-Map theory for Boolean Expressions. Thus it can be seen that a VLSI circuit can be represented as a directed graph (Figure 4 & Figure 5) which is an inverted tree (many inputs - only one output) and the minimum weight on the shortest path shall always be non negative.

3. KRUSKALS ALGORITHM
In Kruskal's algorithm [3][4][5], edges of a graph are considered in ascending order of weights of the edges. The minimum spanning tree is found by choosing the one of least weight that does not form a cycle with already chosen arc of the least weight. The original graph and the spanning tree are shown in Figure 6 and Figure 7, respectively.

Figure 3: VLSI Circuits

an isolated vertex. Two identical columns in an incidence matrix correspond to parallel edges in the graphs G.

. Figure 6: Kruskals algorithm start stage graph The edges of the graph of Figure 6 are joined together and the minimum spanning tree that is found is represented in Figure 7.

Figure 9: A Graph and its Incidence Matrix

4. RESULT AND DISCUSSION

The analogy between VLSI logic circuit viz-a-viz its representation through a directed graph has been shown. Kruskals algorithm has been implemented using C programming language. The nodes or vertices of a graph represent the gates (AND gate or OR gate or other VLSI components). The propagation delay shall be introduced in the graph after the input has passed through the node or the gate and it will be the weight assigned to the edge of the graph. The C program implementing Kruskals algorithm to find a minimum spanning tree is useful to identify the shortest dependency sequence of VLSI components for the optimum design of VLSI circuit. This program has been written and implemented and its efficiency is tested for different combination of nodes, edges and adjacency matrices. The hypothetical data values on number of nodes or vertices, number of edges and the edge weight adjacency matrices are used to run the program and are given in the Table 1. The adjacency matrices of Table 1 are square matrices and the program uses the elements of the matrix in the upper triangular region as the edge weights. The square matrices shown in Table 1 are symmetric matrices. In practice, it is normally seen that any VLSI circuit may have forward as well as reverse signal transmission. Symmetrical coupled lines designed using VLSI components that are onequarter wavelength long can be used as a directional coupler. These lines are assumed to have equal even and odd mode phase velocities [6]. If the weights in the lower triangular section of adjacency matrix of Table 1 are altered in relation to the corresponding weight elements in the upper triangular section of adjacency matrix of Table 1, then it is possible to find the forward and reverse shortest path using the graph theory concept for a VLSI circuit which is used as a bi-directional coupler. A bidirectional coupler is seen as a combination of a unidirectional microstrip coupled line, a directional coupler and a coupled line pair treated as a 4-port as coupling in two parallel transmission lines having VLSI circuits is very common and yet important phenomenon in microwave and optical wave circuits and devices [6][7]. The traversal in the reverse direction using the weights in the lower triangular section of adjacency matrix of Table 1 can help to find the shortest path in the reverse direction thereby improving the coupling intensity. Many methods have been developed to study such coupling among VLSI components [7], but analyzing VLSI circuits using the graph theory can promise a different starting point to researchers working in microwave and optical wave applications as graphical analysis has its mathematical simplicity and objectivity.

Figure 7: Kruskals algorithm final stage graph with MST The minimum spanning tree is the paths F-D-A-B-E-C and F-DA-B-E-G (Figure 7). The total propagation delay is the sum of the edge weights of all edges. A graph can be represented by a matrix. There are two ways of representing a graph by a matrix; namely (i) Adjacency matrix and (ii) Incidence Matrix. The adjacency matrix of a graph is shown in Figure 8; every nonzero element in the matrix represents the connected vertices.

Figure 8: A Graph and its Adjacency Matrix The incidence matrix of a graph is shown in Figure 9; contains only two elements 0 and 1. Each column in the incidence matrix of a graph has exactly two 1s appearing in that column. The sum of 1s in each row represents the degree of a vertex corresponding to the row. A row with all 0s in the incidence matrix represents

Table 1: Input parameters for Kruskal C program

Nodes
6

Edges
15

Adjacency Matrix 0,2,4,1,3,2, 2,0,6,4,5,1, 4,6,0,4,2,1, 1,4,4,0,5,4, 3,5,2,5,0,6, 2,1,1,4,6,0

or the minimum spanning tree, but the execution of Kruskals C program becomes slower. Further, the components identified on the shortest path may turn out to be different when other algorithms are used. Table 2: Time analysis of Kruskal C program Nodes Edges Spanning Tree and Minimum Weight (V0,V3), (V1,V5), (V2,V5), (V0,V1), (V2,V4)=7 8 28 (V0,V3), (V1,V5), (V2,V5), (V4,V7), (V5,V7), (V0,V1), (V0,V6)=9 10 45 (V0,V3), (V0,V8), (V1,V5), (V1,V9), (V2,V5), (V4,V7), (V4,V8), (V5,V7), (V6,V8)=9 12 66 (V0,V3), (V0,V8), (V1,V5), (V1,V9), (V2,V5), (V4,V7), (V4,V8), (V5,V7), (V6,V8), (V0,V10), (V5,V11)=14 0.384615 0.329670 0.219780 Time required in seconds 0.109890

28

0,2,4,1,3,2,2,4, 2,0,6,4,5,1,6,4, 4,6,0,4,2,1,4,6, 1,4,4,0,5,4,3,5, 3,5,2,5,0,6,2,1, 2,1,1,4,6,0,5,1, 2,6,4,3,2,5,0,4, 4,4,6,5,1,1,4,0

15

10

45

0,2,4,1,3,2,2,4,1,3, 2,0,6,4,5,1,6,4,5,1, 4,6,0,4,2,1,4,6,5,4, 1,4,4,0,5,4,3,5,2,5, 3,5,2,5,0,6,2,1,1,4, 2,1,1,4,6,0,5,1,6,4, 2,6,4,3,2,5,0,4,1,3, 4,4,6,5,1,1,4,0,5,1, 1,5,5,2,1,6,1,5,0,4, 3,1,4,5,4,4,3,1,4,0

12

66

0,2,4,1,3,2,2,4,1,3,2,5, 2,0,6,4,5,1,6,4,5,1,5,4, 4,6,0,4,2,1,4,6,5,4,2,4, 1,4,4,0,5,4,3,5,2,5,3,6, 3,5,2,5,0,6,2,1,1,4,6,4, 2,1,1,4,6,0,5,1,6,4,5,3, 2,6,4,3,2,5,0,4,1,3,2,5, 4,4,6,5,1,1,4,0,5,1,5,4, 1,5,5,2,1,6,1,5,0,4,2,4, 3,1,4,5,4,4,3,1,4,0,3,6, 2,5,2,3,6,5,2,5,2,3,0,4, 5,4,4,6,4,3,5,4,4,6,4,0

5. PERFORMANCE EVALUATION
The Kruskals algorithm is implemented for a triplet of nodes, edges and adjacency matrix values and the processor time for program execution is tabulated (Table 2). The mathematical analysis obtained from the performance evaluation of Kruskals algorithm C program shows that as the number of nodes increase time required for executing the code increases and propagation delay also increases (Table 2). It can be seen that with increase in the number of nodes, it is still possible to identify the shortest path

6. CONCLUSION
Through this paper we have proposed the implementation of VLSI logic circuit and finding the minimum propagation delay as the total weight of the minimum spanning tree using the graph theory. We have taken only Kruskals algorithm to find the shortest path due to its simplicity about finding the minimum spanning tree on a directed graph. The performance of Kruskals algorithm C program degrades with an increase in the number of nodes as time required for executing the code increases viz-a-viz the propagation delay, hence simplification of complex VLSI circuit becomes messy there by putting constraints on quality of service and user experience. The evolution of VLSI systems is driven by the emergence of new applications which require better quality of service (QoS) and higher data rates and the need to support a growing number of users. The latter becomes particularly important argument in commercial deployments, where network capacity ultimately affects service costs and thereby influences the success. This limitation creates significant operational challenges to VLSI Logic circuit design and its feasibility using the graph theory on operational paradigm requiring further analysis as in practice variable quality of service (QoS) transmission may be the requirements of VLSI Logic circuits.

[5] Thomas H. Cormen and Charles E. Leiserson and Ronald L. Rivest, Introduction lo Algorithms, McCraw Hill, eighth edition, 1992. [6] David H. Schrader, Microstrip Circuit Analysis, Prentice Hall PTR, New Jearsey 0458, 1995 [7] Ching-Ian Shie, Jui-Chie Cheng, Sheng-Chun Chou and YiChyun Chiang, Transdirectional Coupled Line Couplers Implemented by Periodical Shunt Capacitor, IEEE Transactions on Microwave Theory and Techniques, Vol 57, No. 12, December 2009

7. ACKNOWLEDGEMENT
Our sincere thanks to Thakur educational trust and management to provide all the facilities and infrastructure to carried out the research work.

8. REFERENCES
[1] Shankar Rao G, Discrete Mathematical Structures, New Age International (P) Limited, Publishers, New Delhi, 2003 Page(s):224-224 [2] Chris Chu, Evangeline F k: Youngt, Dennis K. X Tongt and Sampath Dechul, Retiming with Interconnect and Gate Delay, In Proc. DAC, pages 725-730, 1999 [3] Kruskal J.B. On the shortest spanning subtree of a graph and the traveling salesman problem, Proceedings of the American Mathematical Society, Volume 7, pp. 48-50, 1956 [4] Duarte L. Oliveira and Luiz S. Ferreira, Fpga Implementation of Asynchronous Controllers from Generalized Multi-Burst Graph Specification, 978-1-4244-6742-6/10/$26.00 c2010 IEEE, 2010