ChngI: TNGQUANVCHPBTR PPI8255A

PPI 8255A l vi mch ghp ni ngoi vi lp trnh c ( Programmable periferal interface), thng c gi l mch ghp ni vo ra song song lp trnh c. Do kh nng mm do trong cc ng dng thc t, n l mch ghp ni c dng rt ph bin trong cc h vi x l 8 bit, 16 bit v 32 bit.
1.1

S chn:

Vi mch gm 40 chn trong . Gm: PA0 PA7 , PB0 PB7 , PC0 PC7, D0 D7, A0, A1 , , , CS, Reset, Vcc v GND. C 24 ng dn li vo/ra xp thnh 3 cng song song ( portA, portB, portC). Mt na cng C ( PC4 PC7) thuc nhm A gi l PCH, cn na kia thuc nhm B, gi l PCL Chn Reset phi c ni vi tn hiu Reset chung ca ton h thng (khi Reset cc cng c nh ngha l cng vo khng gy ra s c cho cc mch iu khin). Tn hiu CS c ni vi mch to xung chn thit b t mch 8255 vo mt a ch c s no . Cc tn hiu a ch A0, A1 s chn ra 4 thanh ghi bn trong 8255: mt thanh ghi ghi t iu khin (CWR control word register) cho hot ng ca 8255 v 3 thanh ghi khc ng vi cc cng l PA, PB, PC ghi c d liu theo bng:

A1

A0

Lnh (ca VXL)

Hng chuyn s liu vi VXL PortA D0 D7 PortB D0 D7 PortC D0 D7 Khng c gi tr

0 0 1 1 0 0 1 1 x

0 1 0 1 0 1 0 1 x

0 0 0 0 0 0 0 0 1

0 0 0 0 1 1 1 1 x

1 1 1 1 0 0 0 0 x

c PortA c portB c portC

Ghi PortA Ghi PortB Ghi PortC Ghi thanh ghi iu khin Vi mch trng thi tr

D0 D7 PortA D0 D7 PortB D0 D7 PortC D0 D7 thanh ghi iu khin Khng c trao

khng cao

i s liu

Tnh linh hot ca vi mch ny th hin kh nng lp trnh. Ta c th t cc mode hot ng thng qua thanh ghi iu khin. Cc chn D0 n D7 to nn knh d liu 2 hng c rng 8 bit. Tt c d liu khi truy nhp ghi hoc c c dn qua knh d liu ny. Trng thi logic ghi/c c nhn bit qua cc tn hiu iu khin , . Trao i thng tin vi 8255 ch c th c tin hnh khi CS = 0. Khi RD= 0 d liu ca cng c chn c a ra knh d liu v c th c s dng bi cc vi mch khc. Khi WR = 0, th moi vic xy ra ngc li. Cc bit a ch A0 v A1 cng vi cc tn hiu ghi c bo cho bit s truy nhp ln cng no. S khi m t chc nng ca 8255:

1.2-

Cc ch lm vic ca 8255:

xc lp ch lm vic cho 8255 ta ghi t iu khin vo thanh ghi t iu khin CWR ( Control Word Register ). C 2 loi t iu khin cho 8255: - T iu khin nh ngha cu hnh cho cc cng PA, PB, PC. - T iu khin lp/xo tng bit u ra ca PC.

- Tu theo t lnh c ghi vo thanh ghi iu khin khi khi ng ca vi mch m ta c cc PortA,B,C hot ng : + Cc ch 0, 1, 2 khc nhau. + Chiu trao i d liu khc nhau, tc PortA, B, C l cng ra hay vo.

1.2.1-

T iu khin nh ngha cu hnh cho cc cng:

1.2.2- Thanh ghi t iu khin vic thit lp/ xa bit ra PCi:

1.2.3-

Cc ch lm vic:

Chip 8255A c 3 ch lm vic: Ch 0: Vo ra c s (cn gi l vo ra n gin). Trong ch 0, 8255 cho mt kh nng xut v nhp d liu n gin qua 3 cng A,B,C. PA, PB, PC c s dng c lp vi nhau, 3 ng dy u c dng trao i s liu hoc thng tin v iu khin v trng thi mt cch bnh ng vi nhau v tu la chn.

Ch 1: Trong ch ny cc cng A v B c th c dng nh cc cng u vo hoc u ra vi cc kh nng bt tay. Tn hiu bt tay c cp bi cc bit ca cng C.

- Xut d liu ra trong mode 1 Cng PA, PB c tn hiu i thoi tng t nhau. Tn hiu , bo rng b m ra y cho ngoi vi bit CPU ghi d liu vo cng chun b a ra. Tn hiu ny thng ni vi tn hiu ca thit b nhn.

Tn hiu , l tn hiu ca ngoi vi cho bit n nhn c d liu t cc cng PA, PB. Tn hiu INTRA, INTRB l tn hiu yu cu ngt t PA, PB. INTEA, INTEB l tn hiu ca mt mch lt bn trong 8255 cho php hoc cm yu cu ngt INTRA hoc INTRB ca PA hoc PB. INTEA c lp/xo thng qua bit PC6. INTEB c lp/xo thng qua bit PC2. Khi lm vic ch xut thng tin mode 1, thanh ghi trng thi ca 8255 cung cp cc thng tin phn nh trng thi hin hnh ca mnh. S ghp ni ca 8255 mode 1:

(Output Bufer A full): Bo hiu b m cng ra A y (Output Bufer B full): Bo hiu b m cng ra B y INTEA ( Interrupt Enable For PortA): cho php PA chy ch ngt. INTEB ( Interrupt Enable For PortB): cho php PB chy ch ngt. INTRA ( Interrupt PortA ): PA ngt INTRB ( Interrupt PortB ): PB ngt Ni dung thanh ghi trng thi ca 8255 mode 1 cho hung ra:

- Nhn d liu vo trong mode 1

Khi nhn d liu vo trong mode 1 cc cng PA, PB c tn hiu i thoi tng t nhau: STB ( cho php cht d liu). Khi d liu sn sng trn knh PA, PB ngoi vi phi dng STB bo cho 8255 bit cht d liu vo cng PA hoc PB. Sau khi 8255 cht c d liu do thit b ngoi vi a n, n a ra tn hiu IBF (In Buffer full) bo cho ngoi vi bit. Ni dung thanh ghi trng thi ca 8255 mode 1 cho hng vo:

Ch 2: Vo/ra 2 chiu. Trong ch ny ch ring cng PA c th c nh ngha thnh cng vo ra 2 chiu vi cc tn hiu bt tay do cc bit ca cng PC m nhim. Lc ny cng PB c th lm vic ch 0 hoc 1. Ch ny ch dng cho cng PA vi vo/ra 2 chiu v cc bit PC3 PC7 dng lm tn hiu giao tip.

Mch logic ca 8255 mode 2 v cc tn hiu giao tip:

Cng PB c th lm vic mode 1 hoc mode 0 tu theo bit iu khin trong thanh ghi CWR. INTRA: yu cu ngt cho d liu 2 chiu vo/ra. INTE 1, INTE 2: l 2 tn hiu ca 2 mch lt bn trong 8255 cho php hoc cm yu cu ngt ca PA, cc bit ny c lp xo bi PC6 v PC4. Khi dng 8255 trong ch bus 2 chiu trao i d liu theo cch thm d, phi kim tra xem bit IBFA c bng 0 (m vo rng) hay khng trc khi dng lnh IN nhn d liu t cng PA. Khi lm vic ch truyn thng tin 2 chiu ca mode 2, thanh ghi trng thi ca 8255 cung cp cc thng tin phn nh trng thi hin hnh ca mnh. Ni dung thanh ghi trng thi:

Chng II: GHP NI 8255 VI VI X L 2.1-Ghp ni vi 8086: VD: Thit k s ghp ni 8255 vi 8086 v vit chng trnh c t cng PA, a ra PB, ri cng thm 5 v a ra PC Gii:

a ch c s ca 8255 s trn l F00h a ch cc thanh ghi PA: F00h PB: F01h PC: F02h CWR: F03h Chng trnh nh sau: include<dos.h> void main() { Long a; Outport (0xF03, 0x90); a= import(0xF00); outport (0xF01,a); a=a+5;

outport(0xF02,a); } 2.2- Ghp ni vi 8051: 8255 c lp trnh mt trong ba ch va trnh by trn bng cch gi mt t iu khin ti thanh ghi t iu khin ca 8255. Trc ht chng ta phi tm ra cc a ch cng c gn cho mi cng A, B, C v thanh ghi iu khin.

Theo s trn, a ch c s ca 8255 l 4000h tng ng vi a ch ca thanh ghi PA l 4000h, PB l 4001h, PC l 4002h v CWR l 4003h. Xt nhng v d sau: VD1: Hy tm t iu khin ca 8255 cho cc cu hnh sau: a, Tt c cc cng A, B v C u l cc cng u ra (ch 0). b, PA l u vo, PB l u ra, PCL l u vo v PCH l u ra. Gii:

a, cc cng A, B, C u l cc cng u ra, ta phi np vo thanh ghi t iu khin gi tr 1000 0000 = 80h. b, PA, PCL l u vo, PB, PCH l u ra phi np vo thanh ghi t gi tr: 1001 0000h = 90h VD2: Vit mt chng trnh gi 55H v AAH n cng lin tc. MOV A, #80H ; Np gi tr t in khin DPTR, # 4003H @DPTR, A A, # 55H MOV MOVX INC MOVX INC MOVX CPL ACALL SJMP A DELAY AGAIN DPTR @DPTR, A DPTR @DPTR, A DPTR, # 4000H @DPTR, A ; Np a ch cng ca thanh ; Xut t in khin ; Gn A = 55 ; a ch cng PA ; Ly cc bit cng PA ; a ch cng PB ; Ly cc bt cng PB ; a ch cng PC ; Ly cc bt cng PC ; Ly cc bt thanh ghi A ; Ch ; Tip tc

MOV ghi t iu khin MOVX MOV AGAIN:

VD3: iu khin LED n: S nguyn l: Chng trnh: #include<stdio.h>

#include<reg51.h>

int j; unsigned char x,y,k,a; xdata unsigned char PA _at_ 0x00; xdata unsigned char PC _at_ 0x02; xdata unsigned char CREG _at_ 0x03;

void delay() { unsigned long int i; for(i=0;i<=5000;i++); }

void main() { CREG=0x81; while(1) { a=PC ; if(a==1) { x=0x80;

for(j=0;j<8;j++) { PA=x;delay();

x=x>>1; } x=0x01; for(j=0;j<8;j++) { PA=x;delay(); x=x<<1; } }

if(a==2) {

x=0x10;y=0x08; PA=(x|y);delay(); for(j=0;j<=3;j++) { x=x<<1;x=x|0x10; y=y>>1;y=y|0x08; PA=(y|x);delay(); }

if(a==3) { x=0;y=0; PA=(x|y);delay(); for(k=8;k>0;k--) { x=0x80; for(j=0;j<=k-1;j++) { PA=(x|y);delay(); x>>=1; } y<<=1;y=(y|0x01); } } } }

Chng III:
GHP NI 8255 VI THIT B NGOI VI

3.1- Ghp ni vi LCD:

; Ghi cc lnh v d liu ti LCD khng c kim tra c bn. ; Gi s PA ca 8255 c ni ti D0 - D7 ca LCD v ; IB - RS, PB1 = R/W, PB2 = E ni cc chn iu khin LCD MOV MOV MOVX MOV trn 5x7 ACALL ACALL (2ms) MOV ACALL ACALL A, # 0EH ; Bt con tr cho LCD CMDWRT ; Ghi lnh ra LCD DELAY ; Ch n ln xut k tip A, #80H R0, #CNTPORT @R0, A A, #38H ; t tt c cc cng 8255 l u ra ; Np a ch thanh ghi iu khin ; Xut t iu khin ; Cu hnh LCD c hai dng v ma

CMDWRT ; Ghi lnh ny ra LCD DELAY ; Ch ln xut k tip

MOV ACALL ACALL MOV ACALL ACALL ... MOV ACALL ACALL MOV ACALL ACALL ...

A, # 01H

; Xo LCD

CMDWRT ; Ghi lnh ny ra LCD DELAY A, # 06 ; Dch con tr sang phi ; Ghi lnh ny ra LCD

CMDWRT ; Ch ln xut sau DELAY ; Ghi lnh ny ra LCD

; v.v... cho tt c mi lnh LCD A, # 'N' ; Hin th d liu ra (ch N)

DATAWRT ; Gi d liu ra LCD hin th DELAY A, # '0' ; Ch ln xut sau ; Hin th ch "0"

DATAWRT ; Gi ra LCD hin th DELAY ; Ch ln xut sau

; v.v... cho cc d liu khc

; Chng trnh con ghi lnh CMDWRT ra LCD CMDWRT: MOV MOVX liu ca LCD MOV MOV xung thp MOVX E ca LCD NOP ; To xung cho chn E @R0, A ; Kch hot cc chnRS, R/W, R0, # APORT @R0, A R0, # BPORT A, # 00000100B ; Np a ch cng A ; Xut thng tin ti chn d ; Np a ch cng B ; RS=0, R/W=1, E=1 cho xung cao

NOP MOV xung thp MOVX RET ; Chng trnh con ghi lnh DATAWRT ghi d liu ra LCD. CMDWRT: MOV MOVX liu ca LCD MOV cao xung thp MOV MOVX NOP NOP MOV cao xung thp MOVX liu ca LCD RET ; Ghi cc lnh v d liu ti LCD c s dng kim tra c bn. ; Gi s PA ca 8255 c ni ti D0 - D7 ca LCD v ; PB0 = RS, PB1 = R/W, PB2 = E i vi 8255 ti cc chn iu khin LCD MOV A, #80H ; t tt c cc cng 8255 l u ra A, # 00000001B @RC, A ; t RS=1, R/W=0, E=0 cho xung ; Cht thng tin trn chn d R0, # APORT @R0, A R0, # BPORT A, # 00000101B @R0, A ; Np a ch cng A ; Xut thng tin ti chn d ; t RS=1, R/W=0, E=0 cho xung ; Kch hot cc chn RS, R/W, E ; To xung cho chn E @R0, A ; Cht thng tin trn chn d liu ca LCD A, # 00000000B ; RS=0, R/W=1, E=1 cho xung cao

MOV MOVX MOV 5, 7 ACALL MOV ACALL MOV ACALL MOV ACALL ... MOV ACALL MOV ACALL ...

R0, #CNTPORT @R0, A A, #38H

; Np a ch thanh ghi iu khin ; Xut t iu khin ; Chn LCD c hai dng v ma trn

NMDWRT ; Ghi lnh ra LCD A, # 0EH ; Lnh ca LCD cho con tr bt

NMDWRT ; Ghi lnh ra LCD A, # 01H ; Xo LCD

NMDWRT ; Ghi lnh ra LCD A, # 06 ; Lnh dch con tr sang phi

CMDWRT ; Ghi lnh ra LCD ; v.v... cho tt c mi lnh LCD A, # 'N' ; Hin th d liu ra (ch N)

NCMDWRT ; Gi d liu ra LCD hin th A, # '0' ; Hin th ch "0"

NDADWRT ; Gi ra LCD hin th ; v.v... cho cc d liu khc

; Chng trnh con ghi lnh NCMDWRT c hin th c bn NCMDWRT: MOV trng thi LCD MOV MOVX MOV MOV R2, A A, #90H ; Lu gi tr thanh ghi A ; t PA l cng u vo c

R0, # CNTPORT ; Np a ch thanh ghi iu khin @R0, A A, # 00000110B ; t PA u vo, PB u ra ; RS=0, R/W=1, E=1 c lnh

MOV MOVX RS MOV READY:

@R0, BPORT R0, A

; Np a ch cng B ; RS=0, R/W=1 cho cc chn RD v

R0, APORT ; Np a ch cng A MOVX RLC JC MOV MOV MOVX MOV MOV A, R2 A READY A, #80H R0, #CNTPORT @R0, A @R0 ; c thanh ghi lnh ; Chuyn D7 (c bn) vo bit nh carry ; Ch cho n khi LCD sn sng ; t li PA, PB thnh u ra ; Np a ch cng iu khin ; Xut t iu khin ti 8255

; Nhn gi tr tr li ti LCD ; Np a ch cng A ; Xut thng tin ti cc chn ; Np a ch cng B ; t RS=0, R/W=0, E=1 cho xung ; Kch hot RS, R/W, E ca

R0, #APORT @R0, A R0, #BPORT A, #00000100B @R0, A

MOVX d liu ca LCD MOV MOV thp ln cao MOVX LCD NOP NOP MOV cao xung thp MOVX liu LCD

; To rng xung ca chn E

A, #00000000B @R0, A

; t RS=0, R/W=0, E=0 cho xung ; Cht thng tin chn d

RET ; Chng trnh con ghi d liu mi NDATAWRT s dng c bn NCMDWRT: MOV trng thi LCD MOV MOVX MOV MOV MOVX RS MOV READY: R0, APORT ; Np a ch cng A MOVX RLC JC MOV MOV MOVX MOV MOV MOVX d liu ca LCD MOV MOV thp ln cao A, R2 A READY A, #80H R0, #CNTPORT @R0, A @R0 ; c thanh ghi lnh ; Chuyn D7 (c bn) vo bit nh carry ; Ch cho n khi LCD sn sng ; t li PA, PB thnh u ra ; Np a ch cng iu khin ; Xut t iu khin ti 8255 MOV R2, A A, #90H ; Lu gi tr thanh ghi A ; t PA l cng u vo c

R0, # CNTPORT ; Np a ch thanh ghi iu khin @R0, A A, # 00000110B @R0, BPORT R0, A ; t PA u vo, PB u ra ; RS=0, R/W=1, E=1 c lnh ; Np a ch cng B ; RS=0, R/W=1 cho cc chn RD v

; Nhn gi tr tr li ti LCD ; Np a ch cng A ; Xut thng tin ti cc chn ; Np a ch cng B ; t RS=1, R/W=0, E=1 cho xung

R0, #APORT @R0, A R0, #BPORT A, #00000101B

MOVX LCD NOP NOP MOV cao xung thp MOVX liu LCD RET

@R0, A

; Kch hot RS, R/W, E ca

; To rng xung ca chn E

A, #00000001B @R0, A

; t RS=1, R/W=0, E=0 cho xung ; Cht thng tin chn d

3.2- Cc ch khc ca 8255: chng ny chng ta s i tm hiu k hn v ch lp/xa bt BSR( Bit Set/Reset) Mt c tnh duy nht ca cng C l cc bit c th c iu khin ring r. Ch BSR cho php ta thit lp cc bit PC0 - PC7 ln cao xung thp nh hnh sau:

Xt v d sau bit ch ny hot ng nh th no: