Chapter 5 MOS Field-Effect Transistors (MOSFETs)

Lecture adopted from:

Microelectronic Circuits (Sedra and Smith) Microelectronic Circuit Design (Jaeger and Blalock)

By: August Allo UTSA (2011)

(Slides contain a combination of the text book figures, modified figures and slides, and slides added by August Allo to meet the instructors preference and needs)

Chapter Goals
Describe operation of MOSFETs. Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Learn basic structure and mask layout for MOS transistors and circuits. Explore MOS device scaling Contrast 3 and 4 terminal device behavior. Describe sources of capacitance in MOSFETs. Explore FET modeling in SPICE.

Intro
MOSFET metal-oxide-semiconductor field-effect transistor Most commercially successful solid-state device High density VLSI chips, including microprocessors, memories (up to 2 billion on a single chip) PMOS p-channel MOS transistors NMOS n-channel MOS transistors Biopolar junction transistor was reduced to practice first, but FET conceptually easier to understand thus covered 1st

NMOS Transistor: Structure

4 device terminals: Gate(G), Drain(D), Source(S) and Body(B). Source and drain regions form pn junctions with substrate. vSB, vDS and vGS always positive during normal operation. vSB always < vDS and vGS to reverse bias pn junctions

NMOS Transistor: Structure

Can guarantee in cutoff by connecting the Source (S) and Body (B) Conductors can be non-metal silicon based such as polysilicon Voltage applied to the gate controls the current flow between the Drain and Source Device is completely symmetrical and therefore the Source and Drain can be flipped without any effect on the device performance or behavior L typically from 0.03 m to 1.0 m, W typically from 0.1 m to 100 m

NMOS Transistor: Qualitative I-V Behavior

VGS<<Vt : Only small leakage current flows. VGS<Vt: Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. VGS>Vt: Channel formed between source and drain. If vDS>0, finite iD flows from drain to source. iB=0 and iG=0. Vt is typically between 0.3 and 1.0 V

NMOS Transistor: Qualitative I-V Behavior

NMOSFET

B. Van Zeghbroeck, 2007

NMOS Transistor: Triode Region Characteristics (small vDS)

|Q | / unit _ length =WCox(v )
OV

Cox=ox/tox (F/m2) vOV = vGS VTN voltage, vDS establishes an electric field E |E| = vDS/L for vGS VTN vDS 0
ox=oxide
permittivity (F/cm) tox=oxide thickness (cm)

field causes a drift current towards the drain velocity(x) = n|E| = nvDS/L i(x) = (|Q|/unit_length)velocity(x)

NMOS Transistor: Triode Region Characteristics (small vDS)

iD = [(nCox)(W/L)(vOV)]vDS iD = [kn(vOV)]vDS for small vDS it acts as a voltage controlled linear resistance. For larger vDS one must consider the non-uniform channel size resulting in:
v i = Kn v V DS v GS D TN 2 DS

kn= knW/L process transconductance parameter kn=nCox (A/V2)

NMOS Transistor: Transconductance and On resistance (small vDS)

Output characteristics appear to be linear. FET behaves like a gate-source voltagecontrolled resistor between source and drain with iD = Kn(vGS-VTN)]vDS gDS = [Kn(vGS-VTN)] = 1/rDS

MOSFET as Voltage-Controlled Resistor

Example 1: Voltage-Controlled Attenuator
r vo 1 DS = vs = r + R 1 + k R V DS n GG Vt

If kn=500A/V2, Vt=1V, R=2k and VGG=1.5V, then,

vo 1 = 0.667 vs = A 20001.51V 1+ 500 2 V

To maintain triode region operation, v v vo V V or DS OV GG t

0.667v (1.5 1)V or vS 0.750V S Use the min vGS value of the range

MOSFET as Voltage-Controlled Resistor (contd.)

Example 2: Voltage-Controlled High-Pass Filter V s Voltage Transfer function, T (s)= Vo(s)= s+s o s( ) where, cut-off frequency
o =
1 r DS C = k n (V OV C )

If kn=500A/V2, Vt=1V, C=0.02F and VGG=1.5V, then, A

500 fo =
1.51V 2 V =1.99kHz 2 (0.02 F)

To maintain triode region operation, vs V V = 0.5V GG TN

NMOS Transistor: As vDS Increases

As vDS increases in value for a given vGS, the channel becomes non-uniform and the device begins to become non-linear in nature (moving out of the linear region and into pinch-off

v i = Kn v V DS v GS D TN 2 DS

NMOS Transistor: As vDS Increases

v i = Kn v V DS v GS D TN 2 DS

NMOS Transistor: As vDS Increases

NMOS Transistor: Saturation Region (vDS vOV)

If vDS increases above triode region limit, channel region disappears, also said to be pinched-off. Current saturates at constant value, independent of vDS. Saturation region operation mostly used for analog amplification.

NMOS Transistor: Saturation Region (contd.)

k' W 2 i = n v D OV 2 L v =v DSAT OV

for

v v DS OV

is also called saturation or pinch-off voltage

NMOS Transistor: Saturation Region (contd.)

k' W 2 i = n v D OV 2 L v =v DSAT OV

for

v v DS OV

is also called saturation or pinch-off voltage

NMOS Transistor: Saturation Region (contd.)

NMOS Transistor: Circuit Symbols

NMOS Transistor

Enhancement-Mode PMOS Transistors: Structure

Enhancement-Mode PMOS Transistors: Structure

P-type source and drain regions in n-type substrate. vGS<0 required to create p-type inversion layer in channel region For current flow, vGS< vTP To maintain reverse bias on source-substrate and drainsubstrate junctions, vSB <0 and vDB <0 Positive bulk-source potential causes VTP to become more negative

Enhancement-Mode PMOS Transistors: Output Characteristics

For VGS VTP , transistor is off. For more negative vGS, drain current increases in magnitude. PMOS is in triode region for small values of VDS and in saturation for larger values.

Enhancement-Mode PMOS: Circuit Symbols

Channel-Length Modulation
As vDS increases above vDSAT, length of depleted channel beyond pinch-off point, L, increases and actual L decreases. iD increases slightly with vDS instead of being constant.
K 'W 2 i = n v V 1+ v GS D 2 L TN DS

= channel length modulation parameter

NMOS Model Summary

PMOS Model Summary

Output resistance

Non-zero linear slope demonstrates the non-ideal finite output resistance that exist in saturation, ro. ro = 1/ (ID) or VA/ID

Output resistance

Non-zero linear slope demonstrates the non-ideal finite output resistance that exist in saturation, ro. ro = 1/ (ID) or VA/ID

MOSFET Circuits at DC
Bias sets the DC operating point around which the device operates.

MOSFET Circuits at DC
Diode-connected transistor (named due to BJT version of this circuit Chp. 6) Important circuit to understand as it is a building block for a very effective current source used in many IC designs

Behaves similar to a diode except with a squared relationship between the voltage and current

MOSFET Current Source

5 5

MOSFET Inverter

MOSFET 4-Resistor Bias

MOSFET Biasing
Bias sets the DC operating point around which the device operates. (Referred to as the Q-point) The signal is actually comprised of relatively small changes in the DC current and/or voltage bias.

MOSFET Amplifier

MOSFET Amplifier

MOSFET Amplifier

MOSFET Amplifier

Bias Analysis Approach

Assume an operation region (generally the saturation region) Use circuit analysis to find VGS Use VGS to calculate ID, and ID to find VDS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE :An enhancement-mode device with VDS = VGS is always in saturation

Four-Resistor and Two-Resistor Biasing

Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region. Two-resistor biasing uses lesser components than fourresistor biasing and also isolates drain and gate terminals

Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)

Problem: Find Q-pt (ID, VDS , VGS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.

Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)(contd.)

V = I R +V DD D D DS

V =10V (50uA)(100K) DS = 5.00 V

Since IG=0,
V = I R +V =V EQ G EQ GS GS

Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used.

K 2 I = n V V D 2 GS TN 6 2510 A 31 2 V2 = 50 A = 2( ) 2 V

Bias Analysis: Example 2 (Load Line Analysis)

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the load line. Use this to find Q-pt at Analysis: For circuit values above, intersection of load line with device load line becomes characteristic. 10 = I 100K +V D DS
= I R +V V DD D D DS

Assumption: Transistor is saturated, IG=IB=0

Use this to find two points on the load line.

Bias Analysis: Example 2 (Load Line Analysis)(contd.)

10 = I 100K +V D DS @VDS=0, ID=100uA @ID=0, VDS=10V Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve.
Check: The load line approach agrees with previous calculation. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region.

Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)

Problem: Find Q-pt (ID, VDS , VGS) of previous example, given =0.02 V-1. Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.

Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)
K 2 I = n V V 1+ V D 2 GS TN DS V =V I R DS DD D D (25106 ) 2 V =10V (100K) (31) 1+0.02 VDS DS 2 = 4.55 V (25106 ) 2 1+0.02 (4.55) = 54.5 A I = (31) ( ) D 2

Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (54.5 A, 4.55 V) with VGS= 3.00 V

Discussion: The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including effects in most circuits.

Bias Analysis: Example 4 (Four-Resistor Biasing)

Assumption: Transistor is saturated, IG=IB=0 Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage Problem: Find Q-pt (ID, VDS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

Bias Analysis: Example 4 (Four-Resistor Biasing)

V 2 +0.05V 7.21= 0 GS GS

V =2.71V,+2.66V GS

Since VGS<VTN for VGS= -2.71 V and MOSFET will be cut-off,

V =+2.66V and ID= 34.4 A GS Also, VDD = ID(RD +RS )+VDS V = 6.08V DS

Since IG=0,

V =V +I R EQ GS D S

K 2 V =V + n V V R EQ GS 2 GS TN S
4 =V + GS

25106 3.910 4

2 V 1 GS

VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (34.4 A, 6.08 V) with VGS= 2.66 V

Bias Analysis: Example 5 ( Biasing in Triode Region)

Also
V = I (R +R )+V DD D D S DS 4 =1600I +V D DS V = 2.19V DS

But VDS<VGS-VTN. Hence, saturation region assumption is incorrect Using triode region equation, Assumption: IG=IB=0, transistor is saturated (since VDS= VGS) Analysis: VGS=VDD=4 V
I D = 25 A (4 1)2 = 1.13mA 2 V2
V 4V =1600 250 A (41 DS )V DS DS 2 V2 2 V = 2.3V and ID=1.06 mA DS

VDS<VGS-VTN, transistor is in triode region Q-pt:(1.06 mA, 2.3 V)

Small Signal Parameters of MOSFET

2 K I = n V V D 2 GS TN
Transconductance: Since gate is insulated from channel by gate-oxide input resistance of transistor is infinite. Small-signal parameters are controlled by the Q-point. For the same operating point, MOSFET has higher transconductance and lower output resistance that BJT.

gm = K (V

n GS

V ) = 2 K n I TN D

Output resistance: |V | 1 ro = A = I I D D

Small Signal Operation of MOSFET

2 K v v V i = n v V for TN DS GS D 2 GS TN K 2 + 2v V 2 i = I + i = n V V gs GS VTN + v gs D D d 2 GS TN Kn i = V + v gs 2 2v V d 2 gs GS TN

( (

) )

vgs << 2V V TN GS Since MOSFET can be biased with (VGS - VTN) equal to several volts, it can handle much larger values of vgs than corresponding values of vbe for BJT.

For linearity, id should be proportional to vgs

Small Signal Operation of MOSFET

If we replace the MOSFET with the small-signal model, we can solve for the small-signal gain, Av.

v v Av = vo = vds = gm R = gm (R || ro ) L D i gs

Three Basic MOSFET Amplifier Configurations

The MOSFET Inverting Amplifier

Common Source

The MOSFET Inverting Amplifier With Source Resistance

ACS = vo gm R

1+ g m R S

Ro = R D

The MOSFET Non-Inverting Amplifier

CG Avo = gm RD

R =1/ gm i

Ro = R D

The MOSFET Follower Amplifier

CG Avo = gm RL /(1+ gm RL )

Ro =1/ gm

Biasing in MOS Amplifiers Using 4 Resistor Approach

Biasing in MOS Amplifiers Using a Current Source

Common-Source Amplifier

Common-Drain Amplifier

Source-Follower Amplifier