Sheet 1 of 11

MOS COMMON-SOURCE LNA Design Tutorial

J P Silver E-mail: john@rfic.co.uk
1 ABSTRACT This tutorial describes the theory and design on a MOS Low noise amplifier using source degeneration. Source degeneration offers lower noise figures ~2-3dB than the Common-gate LNA topographies (with NF of ~5dB). Design theory and the relevant equations are given, with a worked example using Agilent ADS simulation circuits and plots.
Zin M2 Vbias Rs M1

2 INTRODUCTION 3 INDUCTIVE SOURCE DEGENERATION INPUT MATCHING Previous design examples have assumed that the input is resistive and offered the best value of source resistance (Rs) to obtain best noise match. In reality the input of the device is reactive, with a real and capacitive impedance. Figure 1 shows the equivalent model of a MOSfet, consisting of a voltage controlled voltage source in parallel with the load resistor (Rds).
D G Rg Cgs S Rds S Vc gmVc Cds

Ls

Figure 2 Simple schematic of a cascode LNA design with source de-generation. If we add lossless inductive feedback to the source the above circuit is again re-drawn as shown in Figure 2 below:

Is
D G

Rg Cgs Vg

Vc

gmVc

Figure 1 Equivalent model of a MOSFet What we would like to do is remove the capacitive reactance (and therefore restore the FET input to a pure resistance) and one way of achieving this is to add inductive feedback to the source. The input impedance of the MOSFet circuit shown in Figure 1 will be capacitive due to the gate-source capacitance.
Zi

Ls

Is = Ig+gmVc

Figure 3 New equivalent model of MOSfet with source de-generation added.

Sheet 2 of 11

Z in =

Vg Ig Ig

(I R
g

+ Vc + j .I s .L s ) Ig

- (1)

Rin = Rg jX CGS Rin = jX CGS

Adding series feedback adds the following term to the original input impedance:

Vc =

S.C gs

and I s = I g + g m Vc sub into (1)

Ra + jX LS

Let S = j

Z in

I Ig I R + g + S. I + g m g g g S.C gs S.C gs = Ig

.L s

Additionally, another inductor is added in series with the gate Lg that is selected to resonate with the Cgs Capacitor. What we are trying to achieve is:
Rin = L s .g m Where Rin may be say 50 ohms. C gs

Divide through by Ig I gR g Ig Ig I g .S.C gs Ig + S. I g + g m S.C gs Ls . = I g

Z in =

Lg is designed so that at the resonant frequency it cancels out Cgs ie 1 j L s C gs =0

= Rg +

1 1 + S.L s + S.L s .g m S.C gs S.C gs

= Rg +

L .g S.L s .g m 1 1 + S.L s + = Rg + + S.L s + s m C gs S.C gs S.C gs S.C gs 1 L s .g m + S 2 + L s Sub in S = j S .C C gs gs L s .g m 1 + j 2 + Ls j .C C gs gs

In most LNA designs the value of Ls is picked and the values of gm and Cgs are calculated to give the required Rin.
4 DESIGN EXAMPLE The aim of this example is to design step-by-step a narrow band LNA (Low noise amplifier) to work over the Bluetooth frequency band. A summary of the required specification for the LNA is given in Table 1. Parameter Frequency Noise Figure Gain Power consumption Source/load impedance Specification 2.45 to 2.85 <2.5 >10 <50 50 Units GHz dB dB mW ohms

Rin = Rg +

Rin = Rg +

= Rg +

L s .g m 1 + j L s 2 C gs .C gs

L .g Rin = Rg + s m + j L s 2 C gs .C gs

Table 1 Required specification for the Bluetooth front end LNA. For this design we will be using the Agilent CMOS14 0.5um process that allows a minimum gate length of 0.6um. The schematic of the LNA we will be designing is shown in Figure 4.

L .g 1 Can be re - written as Rin = Rg + s m + j L s C gs C gs Rin = Rg + Ra + j[X LS - X CGS ] Where Ra = L s .gm C gs

Note for MOSFETs Rg is taken as zero. Therefore, the impedance of the MOSFET without feedback is:

Sheet 3 of 11

Vcc +1.5V Lbias

p=

4.(0.9) 2 = 0.162 5.4 1 = 2.67 0.162

QL = 1 +
Lg

Vbias
M1 Using Agilent CMOS14 process Ls

4.3 EVALUATION OF LG
Lg = Q L .Rs - Ls o

Rs = 50

Where o = centre frequency = 2.2.65E 9 = 1.665E 10 rad/sec Lg = 2.67.50 - 1E -9 = 7.52nH 1.665E 10

Figure 4 Initial LNA schematic

4.1 STARTING VALUE OF DEGENERATION INDUCTOR LS.

The value of this inductor is fairly arbitrary but is ultimately limited on the maximum size of inductance allowed by the technology, which is typically about 10nH (anything bigger would probably be too big to be put on the chip). For this example we will pick a value of 1.0nH. We now find the cut-off frequency defined as:
gm Rs 50 T = = = = 1E 11rad/sec (~ 16GHz) Cgs Ls 0.5E -9

4.4 FIND CGS (GATE-SOURCE CAPACITANCE)

Cgs = o (Lg + Ls )
2

Cgs =

(1.665E ) (7.52E
10 2

+ 0.5E 9

= 0.45pF

4.5 FIND W
Cgs = 2 Cox.W.L min rearrange to get W ie 3

4.2 OPTIMAL Q OF INDUCTOR

Optimal Q is given by:
QL = 1 + 1 p . 2 5.

W=

3 Cgs 2 Cox.L min

Lmin = 0.6E -6 m; Tox = 1.01E -8 m ox = ox . o Where s = dielectric constant for silicon = 3.9 and o = dielectric constant for free space = 8.854E -14 F/cm ox 3.9 x 8.854E -14 = = 3.419E -3 pF/um 2 Tox 1.01E -8

Where p =

The parameters for p are dependant on the CMOS technology but typically

Cox =

is set between 2 - 3 (normally 2) is set to 2 - 3 times the value of (normally 4) is assumed to be 0.8 - 1 (take to be 0.9)
W=

3 0.45 . = 330 2 3.419E -3 .0.6

W = 330um

Sheet 4 of 11

I_Probe ID

4.6 CALCULATE GM
DC_Feed DC_Feed1

V_DC SRC1 Vdc=1.5 V

gm = T .Cgs gm = 1E .0.45E
11 -12

Var VAR Eqn VAR3 Ibias=1010 I_DC SRC3 Idc=Ibias uA MOSFET_NMOS MOSFET2 Model=cmosn Length=L um Width=(W/10) um

Var VAR Eqn VAR4 Ls=0.5 Lg=6

Var VAR Eqn VAR1 L=0.6 W=330 C C1 C=10 pF

= 0.045A/V

MOSFET_NMOS MOSFET1 Model=cmosn Length=L um Width=W um vg C C2 C=10 pF L L1 L=Lg nH R=

Term Term2 Num=2 Z=50 Ohm

DC
DC DC1 L L2 L=Ls nH R=

R R3 R=2 kOhm

4.7 V EFFECTIVE
Veff = (Vgs VT ) = gm.Lmin un .Cox.W

S-PARAMETERS
S_Param SP1 Start=0.45 GHz Stop=4.45 GHz Step=

Term Term1 Num=1 Z=50 Ohm BSIM3_Model cmosn NMOS=yes Idsmod=8 Version=3.1 Mobmod=1 Capmod=2 Rsh=2.8 Js=0 Lint=1.097132e-7 Ll=0 Lln=1 Lw=0 Lwn=1 Lwl=0 Wint=2.277646e-7 Wl=0

un = device mobility = 433cm/V Convertingunits gives : Veff = 45000.0.6 = 0.5V 164.330

Wln=1 Ww=0 Wwn=1 Wwl=0 Tnom=27 Tox=1.01e-8 Cj=5.067009e-4 Mj=0.7549569 Cjsw=4.437149e-10 Mjsw=0.1 Pb=0.99 Pbsw=0.99 Cjswg=2.2346e-10 Mjswg=0.1 Pbswg=0.99

Cgso=2.79e-10 Cgdo=2.79e-10 Cgbo=2e-9 Xpart=0.5 Dwg=-7.483283e-9 Dwb=1.238214e-8 Nch=1.7e17 Vbm=-3.0 Xj=1.5e-7 U0=433.6065339 Vth0=0.6701079 Pvth0=8.691731e-3 K1=0.825917 K2=-0.0316751 Pk2=9.631217e-3

K3=68.279056 K3b=1.252205 W0=1e-5 Nlx=5.28517e-8 Dvt0=6.5803089 Dvt1=0.9107896 Dvt2=-0.1427458 Ua=1e-12 Ub=1.582544e-18 Uc=1.831708e-11 Delta=0.01 Rdsw=1.28604e3 Prdsw=-33.9337286 Prwg=0.0182608 Prwb=-0.0586598

Vsat=1.174604e5 A0=0.9059229 Keta=3.997018e-3 Lketa=-0.0143698 Wketa=-5.792854e-3 Ags=0.1450882 Pags=0.0968 B0=1.648829e-6 B1=5e-6 Voff=-0.0850186 Nfactor=1.2410485 Cdsc=2.4e-4 Cdscb=0 Cdscd=0 Cit=0

Eta0=0.1178659 Etab=2.603903e-3 Dsub=0.751089 Drout=0.0428851 Pclm=0.7319137 Pdiblc1=2.091364e-3 Pdiblc2=9.723614e-4 Pdiblcb=-0.5 Pscbe1=2.541131e10 Pscbe2=5e-10 Pvag=0.1945781 Ute=-1.5 At=3.3e4 Ua1=4.31e-9 Ub1=-7.61e-18

Uc1=-5.6e-11 Kt1=-0.11 Kt2=0.022 Em=4.1e7 Xw=0 Xl=-1e-7

With VT = 0.67V Therefore,we need to apply (0.67 + 0.5) = 1.16V to the gate

4.8 BIAS CURRENT ID

Id = 1 1 .gm.V eff = .0.045 .0.5 = 11mA 2 2

Figure 5 ADS simulation setup to analyse the basic LNA design. Note we have added a current mirror and current source, together with a bias resistor to isolate the current mirror from the RF input. Note with this simulation we have used ideal inductors ie no Q value has been entered and therefore have no loss.
2.0

1.5

(9) Estimated Optimum Noise Figure

m2 freq=2.409GHz nf(2)=0.690
nf(2)

2 o Fopt = 1 + T Take c = 0.4 Fopt = 1 +

p c + p + 1+ p

1.0

m2

0.5

4 1.665E 10 0.162 [0.4] + 0.162 + 1 + 0.162 0.9 5E10

0.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Fopt = 2.12 = 10log(2.12) = 3.26dB

With these circuit values we can now simulate the circuit using ADS. The schematic circuit is shown in Figure 5 with the resulting noise and gain plots shown in Figure 6.
14 12 10 8 6 4 0.0

ID.i 11.03mA

freq, GHz vg 1.055 V

m1

dB(S(2,1))

m1 freq=2.491GHz dB(S(2,1))=12.602

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

freq, GHz

Sheet 5 of 11

Figure 6 Resulting simulation plots of noise figure and gain from the ADS simulation shown in Figure 5.

2r

5 INDUCTOR Q
The LNA simulation gives a very low noise figure because zero loss inductors have been used on the source and gate. We need to determine that sort of loaded Qs we might get with the current technology at a frequency of 2.4GHz. Of course we could always use high Q off-chip inductors but in the quest for systems on a chip we are restricted to gold bond wires (with a typical inductance of 1nH per 1mm of length) and spiral printed inductors. There two types of spiral inductor, square planar and hollow: The square planar spiral inductor is shown in Figure 7. Inductance is given by [1]:
L o .n 2 .r = 4E -7 .n 2 .r L 1.2E - 6 .n 2 .r
2r

Figure 8 Diagram of a hollow spiral inductor

The maximum Q possible is a function of the CMOS process being used. Typical Qs for submicron technologies are ~ 4 to 6 with inductors of 10nH. [2].

6 ADDITION OF CASCODE STAGE

The Cascode is a combination of a common-source device (ie our LNA) with a common-gate load. This has the effect of increasing the output impedance. We have assumed we are using a resistive load, but if we are going to connect to another stage say another LNA or mixer, then the load will be capacitive. This capacitance will limit the frequency response of the first amplifier stage (resulting in lower gain) due to the Miller effect. The additional cascode device has been configured as a diode (ie at DC the gate is connected to the source) as shown in Figure 9. The inductor between the cascode source and supply blocks any RF leaking to the supply rail and maybe varied in value to optimize the gain response of the LNA.

Figure 7 Diagram of a square planar spriral inductor

The resulting plot of the circuit shown in Figure 9 is shown in Figure 10.

The second type of spiral inductor is shown in Figure 8. Inductance is given by:
L 37.5. o .n 2 .a 22r - 14a

Where o = permeability of free space = 4.x10 -7 H/m

Sheet 6 of 11

Var VAR Eqn VAR3 Ibias=1100

Var VAR Eqn VAR1 L=0.6 W=330

Var VAR Eqn VAR4 Ls=0.5 Lg=6

I_Probe ID

V_DC SRC1 Vdc=2.5 V

2.00 1.98 1.96

m2 m2 freq=2.450GHz nf(2)=1.994
nf(2)

DC_Feed DC_Feed1 MOSFET_NMOS MOSFET3 Model=cmosn Length=L um Width=W um I_DC SRC3 Idc=Ibias uA MOSFET_NMOS MOSFET2 Model=cmosn Length=L um Width=(W/10) um

C C1 C=10 pF Term Term2 Num=2 Z=50 Ohm

1.94 1.92 1.90 2.45

MOSFET_NMOS MOSFET1 Model=cmosn Length=L um Width=W um vg INDQ L1 L=Lg nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

DC
DC DC1

R R3 R=2 kOhm C C2 C=10 pF Term Term1 Num=1 Z=50 Ohm BSIM3_Model cmosn NMOS=yes Idsmod=8 Version=3.1 Mobmod=1 Capmod=2 Rsh=2.8 Js=0 Lint=1.097132e-7 Ll=0 Lln=1 Lw=0 Lwn=1 Lwl=0 Wint=2.277646e-7 Wl=0

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

freq, GHz
INDQ L2 L=Ls nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

S-PARAMETERS
S_Param SP1 Start=0.45 GHz Stop=4.45 GHz Step=

ID.i 11.08mA
11.52 11.50

vg 1.078 V dB(S(2,1))

Wln=1 Ww=0 Wwn=1 Wwl=0 Tnom=27 Tox=1.01e-8 Cj=5.067009e-4 Mj=0.7549569 Cjsw=4.437149e-10 Mjsw=0.1 Pb=0.99 Pbsw=0.99 Cjswg=2.2346e-10 Mjswg=0.1 Pbswg=0.99

Cgso=2.79e-10 Cgdo=2.79e-10 Cgbo=2e-9 Xpart=0.5 Dwg=-7.483283e-9 Dwb=1.238214e-8 Nch=1.7e17 Vbm=-3.0 Xj=1.5e-7 U0=433.6065339 Vth0=0.6701079 Pvth0=8.691731e-3 K1=0.825917 K2=-0.0316751 Pk2=9.631217e-3

K3=68.279056 K3b=1.252205 W0=1e-5 Nlx=5.28517e-8 Dvt0=6.5803089 Dvt1=0.9107896 Dvt2=-0.1427458 Ua=1e-12 Ub=1.582544e-18 Uc=1.831708e-11 Delta=0.01 Rdsw=1.28604e3 Prdsw=-33.9337286 Prwg=0.0182608 Prwb=-0.0586598

Vsat=1.174604e5 A0=0.9059229 Keta=3.997018e-3 Lketa=-0.0143698 Wketa=-5.792854e-3 Ags=0.1450882 Pags=0.0968 B0=1.648829e-6 B1=5e-6 Voff=-0.0850186 Nfactor=1.2410485 Cdsc=2.4e-4 Cdscb=0 Cdscd=0 Cit=0

Eta0=0.1178659 Etab=2.603903e-3 Dsub=0.751089 Drout=0.0428851 Pclm=0.7319137 Pdiblc1=2.091364e-3 Pdiblc2=9.723614e-4 Pdiblcb=-0.5 Pscbe1=2.541131e10 Pscbe2=5e-10 Pvag=0.1945781 Ute=-1.5 At=3.3e4 Ua1=4.31e-9 Ub1=-7.61e-18

Uc1=-5.6e-11 Kt1=-0.11 Kt2=0.022 Em=4.1e7 Xw=0 Xl=-1e-7

11.48

m1 11.46
11.44 11.42 11.40 11.38 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85

m1 freq=2.450GHz dB(S(2,1))=11.447

freq, GHz

Figure 9 Updated ADS schematic with loaded Qs of inductors added together with the cascode stage on the output.

It is normal to set the cascode device with the same W/L ratio as the first LNA stage ie 330/0.6. As the bias mirror device MOSFET2 is only required to drive the gate of MOSFET1 then we can scale back the W/L ratio to say 1:10 or even 1:20. We need to raise the voltage supply to the LNA as each stage requires ~1V therefore we need at least 2V driving the gates, so the supply has been raised to 2.5V. This still gives us a power consumption of 2.5*(11mA + 1mA (bias arm) ) = 30mW.

Figure 10 Gain and Noise figure frequency responses of the cascode LNA shown in Figure 9.Note The supply rail has been raised as the required bias to each gate was ~ 1V.

7 LINEARITY
Finally the 1dB compression point of the LNA was calculated & simulated. If an amplifier is driven hard enough the output power will begin to roll off resulting in a drop of gain known as gain compression. The measurement of gain compression, is given by the 1dB gain compression point. This parameter in another measure of the linearity of a device and is defined as the input power that causes a 1dB drop in the linear gain due to device saturation. An example of the 1dB compression point is shown in Figure 11.

Sheet 7 of 11

Pout (dBm) 30

PIIP3 ~
Saturated Output Power 21dBm

.V .Vod 8 Vsat .L 1 + 1 od Vod 1 + 1 2Vsat .L 4Vsat .L 3 .Rs 1

- (2)

1dB Compression Point 20dBm

25

+ 2 Vsat.L 1 o

20

Running the simulation shown in Figure 17, the values of Vgs = 1.08V.
1dB gain change

15

Using the spice model data for the Agilent CMOS14

0.5um we have: L = 0.6um, 0 = 433 cm^2/(V*s), = 0.1, Rs = 50 ohms, VT = 0.67V Vsat = 1.73E5 m/s First convert numbers to metre format:

10

0 -10 -5 0 Pin (dBm) 5 10

Figure 11 Compression point plot. The red curve is the gain compression characteristic of a 15dB gain amplifier. The parallel black line is 1dB below and represents a gain of 14dB. The input power where the amplifier gain crosses the 1dB down line is know as the 1dB input compression point. We can get a rough estimate of the gain compression of the LNA a non-linear expression of the input and output parameters can be expanded using Taylors theorem. This results in the following equations for 1dB gain compression point and IM3 [3].
V 2 od I .C . =W DSAT vsat ox V + E .L od sat With V = Voltage overdrive = Vgs - Vt and od E sat = Velocity saturation field strength given by 2V o sat Where = eff 1 + .V eff od
2

0 = 433 cm^2/(V*s), = 0.433 m^2/(V*s L = 0.6um, = 0.6E-6m.

V = V - V = 1.26 - 0.67 = 0.59V od gs T

0.433 + 2x0.1x1.73E 5 .0.6E 6 = 453 1

Feeding these values into equations 1 & 2 yields P1dB = 9.39dBm and IIM3 = 19.02dBm. The equations 1 & 2 were entered into a spreadsheet, along with a range of Vod from 0.01 to 5V. The table of results is shown in Table 2. Vod (V) 0.01 0.5 0.41 1 1.5 2 2.5 3 3.5 4 4.5 5 1dB Comp (dBm) -10.05 8.42 7.30 12.77 15.74 18.09 20.07 21.80 23.34 24.73 26.01 27.19

sat

P1dB

.Vod .V V .L 1 + 1 od ~ 0 .29 sat Vod 1 + 1 4Vsat .L 2Vsat .L .Rs 1

- (1)

to convert to dBm = 10 log (1000*P1dB)

Table 2 Calculated 1dB compression point

Sheet 8 of 11

The following two graphs show the plotted data of the data shown in Table 2. 1dB compression point is shown in Figure 12.
Input referred 1dB compression point vs Vod 30 25 Input 1dB comp (dBm) 20 15 10 5 0 -5 -10 -15 Vod = Vgs-Vt (Volts) 0 1 2 3 4 5
-40

sweep plan sets the input power sweep. The harmonic balance allows the LNA harmonics to be plotted and the gain compression block allows a pin vs pout plot to be generated.

1dB Compression Characteristic of MOS LNA

Output Spectrum at 1 dB Gain Compression Point 10 0 -10 -20 -30

dBm(HB2.HB.Vout)

10

freq, GHz

Eqn Gain=dBm(HB1.HB.Vout[1])-HB1.HB.Pin Eqn linear=Gain[0]+HB1.HB.Pin

Input and Output Powers at 1 dB Compression Point

Figure 12 Referred to input 1dB compression point plot using the CMOS 14 Spice data

inpwr[1] -4.055

outpwr[1] 6.421

Figure 13 shows the ADS simulation setup to allow the 1dB compression point to be simulated. The resulting plots are shown in Figure 14 (harmonic spectrum) and Figure 15 (gain compression plot).
Vout MOS_LNA X1
Var Eqn

Figure 14 Harmonic spectrum of the MOS LNA with a prediction of the 1dB compression point of -4dBm.

The gain compression calculation agrees with the simulation value to within 1dB at 7.5dBm (Simulation value calculated at 6.5dBm). Finally, to increase the gain margin of the LNA another C-S stage could be added to the cascode output.. This output stage is DC coupled to the output of the first cascode stage so that is receives a correct bias to be in saturation. The increased gain will greatly improve the noise figure of the receiver as the noise figure of the second stage (most likely the mixer) will be reduced by ~1/gain_LNA. The ADS simulation of the modified LNA is shown in Figure 17 together with the resulting gain & noise figure prediction shown in Figure 16.

P_1Tone PORT1 Num=1 Z=50 Ohm P=dbmtow(Pin) Freq=RFfreq

VAR VAR1 RFfreq=2.5 GHz Pin=-5

Term Term2 Num=2 Z=50 Ohm

HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=RFfreq Order[1]=5 SweepVar="Pin" SweepPlan="Plan1"

GAIN COMPRESSION
XDB HB2 Freq[1]=RFfreq Order[1]=5 GC_XdB=1 GC_InputPort=1 GC_OutputPort=2 GC_InputFreq=2.5 GHz GC_OutputFreq=2.5 GHz GC_InputPowerTol=1e-3 GC_OutputPowerTol=1e-3 GC_MaxInputPower=100

SWEEP PLAN
SweepPlan Plan1 Start=-40.0 Stop=10 Step=0.5 Lin= UseSweepPlan= SweepPlan= Reverse=no

Figure 13 ADS simulation setup to measure the 1dB compression point of the LNA. The

Sheet 9 of 11

m1 indep(m1)=-4.000 plot_vs(dBm(HB1.HB.Vout[1]), HB1.HB.Pin)=6.458 30 20 10 0 -10 -20 -30 -40 -30 -20 -10 0 10 HB1.HB.Pin Pin linear dBm(HB1.HB.Vout[1])

boosted to >20dB. The increased gain will greatly improve the noise figure of the receiver as the noise figure of the second stage (most likely the mixer) will be reduced by ~1/gain_LNA.

m2 m1

8 SUMMARY
This tutorial gave the design equations to design an LNA using shunt feedback realized with on-chip inductors. A design example of a bluetooth LNA was given, with the associated step-by-step design process to meet a given specification. ADS simulations have been given to predict the various circuit parameters of gain, noise figure, power consumption and 1dB compression point, all summarized in Table 3.
An additional C-S stage was added to the basic LNA to boost the power gain of the LNA to > 20dB. The increased gain will

Eqn compression=m1-m2
compression -1.018 m2 Pin=-4.000 linear=7.476

Figure 15 Gain compression plot of the MOS LNA. The markers m1 and m2 are adjusted to give a compression of 1dB, giving a 1dB compression point of 4dBm.
nf(2)
2.02 2.00 1.98 1.96 1.94 1.92 1.90 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85

greatly improve the noise figure of the receiver as the noise figure of the second stage (most likely the mixer) will be reduced by ~1/gain_LNA at the expense of an increase in power consumption. Finally the definition of linearity was given, together with the associated equations for the calculation of 1dB gain compression point and 3rd Order Intercept point.
Parameter Specification 2.45 to 2.85 <2.5 >10 <50 50 Not specified Prediction 2.45 to 2.85 <2 >11.4 30 50 6.4 Units GHz dB dB mW ohms dBm

m1

m1 freq=2.654GHz nf(2)=1.949

Frequency Noise Figure Gain Power consumption Source/load impedance 1dB O/P compression point

freq, GHz
21.0 20.8 20.6 20.4 20.2 20.0 19.8 19.6 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85

m2
Table 3 Summary of simulated device performance.

m2 freq=2.621GHz dB(S(2,1))=20.920

9 REFERENCES
[1] T.H Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, ISBN 0 521 63922 0, Chapter 2. [2] C.S Kim, M Park, C-H Kim, Y C Hyeon, H K Yu, K Lee, K S Nam, A fully integrated 1.9GHz CMOS Low-noise amplifier in IEE Microwave and guided wave letters, Vol 8, No 8 August 1998.

dB(S(2,1))

freq, GHz

Figure 16 Simulated gain & noise figure plots from the degenerated LNA with added C-S output stage. The power gain (S21) has now been

Sheet 10 of 11

[3] T Soorapanth, T.H Lee, RF Linearity of ShortChannel MOSFETs, IEEE Journal of Solid State Circuits, vol. 32, no. 5, May 1997.

Sheet 11 of 11

Var Eqn

VAR VAR3 Ibias=1100

Var Eqn

VAR VAR1 L=0.6 W=330

Var Eqn

VAR VAR4 Ls=0.5 Lg=5.5

I_Probe ID INDQ L3 L=10 nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm V_DC SRC1 Vdc=2.5 V

I_Probe Ibias I_DC SRC3 Idc=Ibias uA

MOSFET_NMOS MOSFET3 Model=cmosn Length=L um Width=W um

MOSFET_NMOS MOSFET2 Model=cmosn Length=L um Width=(W/10) um

MOSFET_NMOS MOSFET1 Model=cmosn Length=L um Width=W um vg INDQ L1 L=Lg nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

R R3 R=2 kOhm C C2 C=10 pF Port P1 Num=1 Term Term1 Num=1 Z=50 Ohm

MOSFET_NMOS MOSFET4 Model=cmosn Length=L um Width=W um

INDQ L4 L=10 nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

INDQ L2 L=Ls nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

C INDQ C1 L5 C=10 pF L=10 nH Q=6 F=2400.0 MHz Mode=proportional to freq Rdc=0.0 Ohm

Port P2 Num=2 Term Term2 Num=2 Z=50 Ohm

S-PARAMETERS S_Param SP1 Start=2.45 GHz Stop=2.85 GHz Step= Cgso=2.79e-10 Cgdo=2.79e-10 Cgbo=2e-9 Xpart=0.5 Dwg=-7.483283e-9 Dwb=1.238214e-8 Nch=1.7e17 Vbm=-3.0 Xj=1.5e-7 U0=433.6065339 Vth0=0.6701079 Pvth0=8.691731e-3 K1=0.825917 K2=-0.0316751 Pk2=9.631217e-3 DC DC1 K3=68.279056 K3b=1.252205 W0=1e-5 Nlx=5.28517e-8 Dvt0=6.5803089 Dvt1=0.9107896 Dvt2=-0.1427458 Ua=1e-12 Ub=1.582544e-18 Uc=1.831708e-11 Delta=0.01 Rdsw=1.28604e3 Prdsw=-33.9337286 Prwg=0.0182608 Prwb=-0.0586598 Vsat=1.174604e5 A0=0.9059229 Keta=3.997018e-3 Lketa=-0.0143698 Wketa=-5.792854e-3 Ags=0.1450882 Pags=0.0968 B0=1.648829e-6 B1=5e-6 Voff=-0.0850186 Nfactor=1.2410485 Cdsc=2.4e-4 Cdscb=0 Cdscd=0 Cit=0 Eta0=0.1178659 Etab=2.603903e-3 Dsub=0.751089 Drout=0.0428851 Pclm=0.7319137 Pdiblc1=2.091364e-3 Pdiblc2=9.723614e-4 Pdiblcb=-0.5 Pscbe1=2.541131e10 Pscbe2=5e-10 Pvag=0.1945781 Ute=-1.5 At=3.3e4 Ua1=4.31e-9 Ub1=-7.61e-18

DC

BSIM3_Model cmosn NMOS=yes Idsmod=8 Version=3.1 Mobmod=1 Capmod=2 Rsh=2.8 Js=0 Lint=1.097132e-7 Ll=0 Lln=1 Lw=0 Lwn=1 Lwl=0 Wint=2.277646e-7 Wl=0

Wln=1 Ww=0 Wwn=1 Wwl=0 Tnom=27 Tox=1.01e-8 Cj=5.067009e-4 Mj=0.7549569 Cjsw=4.437149e-10 Mjsw=0.1 Pb=0.99 Pbsw=0.99 Cjswg=2.2346e-10 Mjswg=0.1 Pbswg=0.99

Uc1=-5.6e-11 Kt1=-0.11 Kt2=0.022 Em=4.1e7 Xw=0 Xl=-1e-7

Figure 17 ADS schematic of the C-S LNA with a simple C-S stage added to the cascode output to increase the power gain of the LNA to > 20dB.