z

z
Thc hnh nng cao

B CNG THNG
TR N

N-

T U T

N T

T
Tng quan v

N NN
O
i
DL v thit k Sequential Logic Using
UDP dng Verilog

Ging vi n h ng dn

Sinh vi n thc hin

: Th.s h c
:

o ng

Nh m 14:
1. ip Th Nh n
2.Nguyn Ngc Tun
3.Nguyn Th Nhung
4.L Minh a
L p : DT17AHN
Kh 2008-2011
H

I ,ngy 25/ 04/ 2011

Nhm 14

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P N
TN

Mc Lc:
1: ................................................................................................................... 6

QU N V

DL ........................................................................................ 6

1.1. M u .................................................................................... 6
1.2. Khi nim ................................................................................. 6
1.3. Nhng u im c phng php thit k h thng s bng ngn ng m t phn
cng HDL...7
1.4. Gi i thiu ngn ng m t phn cng VHDL ..................................... 8.9

1.5. Code c HDL trong

Verilog.10,11
P N 2 .................................................................................................................. 12
TM

U V VER LO ................................................................................ 12

..................................................................... 12
II. CHC NNG CC T VNG TRONG VERILOG ............................. 12
I. Tng qu n v verilog

1. Khong trng ............................................................................................................ 13

2. Ch gii .................................................................................................................... 13
3. Ch s: ..................................................................................................................... 13
4. T nh d nh: ........................................................................................................... 13
5. C php: ................................................................................................................... 13
6. Ton t: .................................................................................................................... 13
7. T kh Verilog: ....................................................................................................... 13
III.CC CNG C BN TRONG VERILOG ......................................... 14
1. Cc cng c bn: ...................................................................................................... 14
1.1. C php: ................................................................................................................ 14
1.2. V d: .................................................................................................................... 14
2. Cng buf, not: .......................................................................................................... 14
2.1. C php: ................................................................................................................ 14
2.2. V d: .................................................................................................................... 14
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IV. CC DNG D LIU ................................................................. 15
I. t gi tr: ................................................................................................................. 15
II. Wire: ........................................................................................................................ 16
III. Reg: ........................................................................................................................ 16
IV. Input, Output, Inout: .................................................................... 16
I. Integer (S nguy n):

...................................................................... 17

II. Supply 0, Supply1: .................................................................................................. 17

III. Time: ...................................................................................................................... 18
IV. P r meter (Th m s): ............................................................................................ 18
V. TON T ................................................................................. 19
I. Ton t s hc: ......................................................................................................... 19
II. Ton t qu n h: ...................................................................................................... 19
III. Ton t bit_wire:.................................................................................................... 19
IV. Ton t logic: ......................................................................................................... 20
V. Ton t bin i: ..................................................................................................... 20
VI. Ton t ghp: ......................................................................................................... 20
VII. Ton t dch: ........................................................................................................ 20
VIII. Ton t iu kin: ............................................................................................... 20
IX. Th t ton t: ....................................................................................................... 20
VI.TON HNG ............................................................................ 21
I. Liter ls (dng k t): ................................................................................................. 21
II. Chn 1 phn t bit v chn 1 phn cc bit. ............................................................. 21
III. Gi hm chc nng: ............................................................................................... 22
IV. Wire, reg, v th m s: ............................................................................................ 22
VII. MODULES .............................................................................. 23
I. Khai bo modules: .................................................................................................... 23
II. Ch nh li n tip: .................................................................................................... 23
III. Module instantiations: ............................................................................................ 24
VIII. KHUN MU HNH VI (BEHAVIORAL) ..................................... 25
I. Nhng ch nh theo th tc: .................................................................................... 25
II. Delay trong ch nh: ............................................................................................... 26

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III. Ch nh khi: ........................................................................................................ 26
IV. Begin end: .......................................................................................................... 26
V. Vng lp for: ........................................................................................................... 27
VI. Vng lp while:...................................................................................................... 27
VII. Khi lnh if else if else: ................................................................................ 27
VIII. Case: .................................................................................................................... 27
IX. KHI ALWAYS V KHI INITIAL ............................................... 28
I. Khi lw ys: ............................................................................................................. 28
II. Khi initi l............................................................................................................... 29
X. HM ....................................................................................... 30
I. Khai bo hm: ........................................................................................................... 30
XI. CHC NNG LINH KIN ........................................................... 30
I. Th nh ghi Edge_triggered, flip_flop, b m: ......................................................... 31
II. B cng:.............................................................................................................. 32
III. B cng, tr: .......................................................................................................... 32
IV. B m 3 trng thi: .............................................................................................. 32
V. Cc linh kin khc: .................................................................................................. 32

P N 3
MT S V D33
I. Cu trc mt chng trnh dng ngn ng Verilog: ................................................ 33
1. V d 1: .................................................................................................................... 33
. Chng trnh tnh NOR cc bit c bin vo ........................................................... 33
b. M phng ................................................................................................................. 33
2. V d 2: .................................................................................................................... 34
. Chng trnh cng h i bin bn bit ......................................................................... 34
b. M phng ................................................................................................................. 34
3. V d 3: .................................................................................................................... 35
. Chng trnh gii m 2 s ng 4 ................................................................................. 35
b.m phng...............36
.4.vi d 437
a. dn k nh 4 s ng 2..........37
b.m phng..38

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5.v d 5
. Chng trnh i BCD s ng by on ................................................................ 39.40
b. M phng ................................................................................................................. 41
6 V d 6....................................................................................................................... 42
. Chng trnh gim t 9 xung 0, hin th r led 7 on ..................................... 42,43
b.Mphng ................................................................................................................... 44
7 V d 7....................................................................................................................... 44
. Chng trnh tng t 0 n 9, hin th r led 7 on .......................................... 44,45
b. M phng ................................................................................................................. 46

P N 447
i T p: ..................................................................................... 47
T
T
SEQUENT L LO
US N UDP DN
VERILOG. ..47,48,49
Kt lun ........................................................................................................................ 50
Ti liu th m kho: ...................................................................................................... 51

Nhm 14

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P N
TN

QU N V

DL

1.1. M u
Ngy ny ngnh cng ngh ch to phn cng lun c nhng t
ph khng ngng. T cc mch in n gin n cc mch s, mch
tch hp, kin trc mch tr n n ngy mt phc tp hn. Nh nhng u
im hn hn so v i cc phng php phn tch, m hnh ho, thit k
mch s kiu truyn thng m phng php s dng cc ngn ng m
phng phn cng( HDL-H rd w re Description L ngu ges ) ng tr
thnh mt phng php thit k cc h thng in t s ph bin tr n
ton th gi i. Trong khun kh phm vi c bi bo ny chng ti xin
gi i thiu mt loi ngn ng m phng phn cng l VHDL (Very
high speed intergr ted circuit H rdw re Description L ngu ge), loi
ngn ng ch yu c s dng m phng phn cng trong cng
ngh CPLD, FPGA, ASIC

1.2

hi nim

- L ngn ng thuc l p ngn ng my tnh(computer language

- Dng miu t cu trc v hot ng mt vi mch
- Dng m phng, kim tra hot ng vi mch
- Biu din hnh vi theo thi gian va cu trc khnggian ca mch

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- Bao gm nhng k hiu biu din thi gian v s1ng thi (time and
concurrence)

1.3. Nhng u im ca phng php thit k h thng s

ng ngn ng m phng phn cng ( DL)
Ngy n y, cc mch tch hp ngy cng thc hin c nhiu chc
nng do m vn thit k mch cng tr n n phc tp. Nhng
phng php truyn thng nh dng phng php ti thiu ho hm
Boolean h y dng s cc phn t khng cn p ng c cc y u
cu t r khi thit k. Nhc im l n nht c cc phng php ny
l chng ch m t c h thng d i dng mng ni cc phn t v i
nh u. Ngi thit k cn phi i qu h i b c thc hin hon ton th
cng: l chuyn t cc y u cu v chc nng c h thng s ng biu
din theo dng hm Boole n, s u cc b c ti thiu ho hm ny t li
phi chuyn t hm Boole n s ng s mch c h thng. Cng
tng t khi phn tch mt h thng ngi phn tch cn phi phn tch
s mch c h thng, ri chuyn n thnh cc hm Boole n, s u
m i lp li cc chc nng, hot ng c h thng. Tt c cc b c n i
tr n hon ton phi thc hin th cng khng c bt k s tr gip no
c my tnh. Ngi thit k ch c th s dng my tnh lm cng c
h tr trong vic v s mch c h thng v chuyn t s mch
s ng cng c tng hp mch vt l dng cng c Synthesis. Mt nhc
im khc n c phng php thit k truyn thng l s gi i hn v
phc tp c h thng c thit k .Phng php dng hm
Boole n ch c th dng thit k h thng l n nht biu din bi vi
trm hm. Cn phng php d tr n s ch c th dng thit k
h thng l n nht ch khong vi nghn phn t.
Phng php thit k, th nghim, phn tch cc h thng s s
dng cc ngn ng m t phn cng ni bt l n v i cc u im hn
hn vs dn th y th cc phng php truyn thng. S r i c
ngn ng m phng phn cng gii quyt c rt nhiu nhc
im l n c cc phng php thit k tr c y: Nu cc phng
php c i hi phi chuyn i t m t h thng (cc ch ti u v chc
nng) s ng tp hp cc hm logic bng t y th b c chuyn hon
ton khng cn thit khi dng HDL. Hu ht cc cng c thit k dng
ngn ng m phng phn cng u cho php s dng biu trng
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Thc hnh nng cao

thi( finite-state-m chine) cho cc h thng tun t cng nh cho php

s dng bng chn l cho h thng tng hp. Vic chuyn i t cc
biu trng thi v bng chn l s ng m ngn ng m phng phn
cng c thc hin hon ton t ng.
Nh tnh d kim tr th nghim h thng trong sut qu trnh thit
k m ngi thit k c th d dng pht hin cc li thit k ng y t
nhng gi i on u, gi i on ch vo sn xut th, do tit
kim c lng chi ph ng k bi t thit k n to r sn phm
ng nh mong mun l mt vic rt kh trnh khi nhng kh khn,
tht bi.
Khi mi lnh vc c kho hc u pht trin khng ngng th s
phc tp c h thng in t cng ngy mt tng theo v gn nh
khng th tin hnh thit k th cng m khng c s tr gip cu cc
loi my tnh hin i. Ngy n y, ngn ng m t phn cng HDL
c dng nhiu thit k cho cc thit b logic lp trnh c PLD
t loi n gin n cc loi phc tp nh m trn cng lp trnh c
FPGA.

1.4.

ii thiu ngn ng m t phn cng V DL

VHDL l ngn ng m t phn cng cho cc mch tch hp tc

rt c o, l mt loi ngn ng m t phn cng c pht trin dng cho
trng trnh VHSIC( Very High Speed Itergr ted Circuit) c b quc
phng M. Mc ti u c vic pht trin VHDL l c c mt ngn
ng m phng phn cng ti u chun v thng nht cho php th
nghim cc h thng s nh nh hn cng nh cho php d dng cc
h thng vo ng dng trong thc t. Ngn ng VHDL c b
cng ty Intermetics, IBM v Tex s Instruments bt u nghi n cu pht
trin vo thng 7 nm 1983. Phi n bn u ti n c cng b vo thng
8-1985. S u VHDL c xut t chc IEEE xem xt thnh
mt ti u chun chung. Nm 1987 r ti u chun v VHDL( ti u
chun IEEE-1076-1987).
VHDL c pht trin gii quyt cc kh khn trong vic pht
trin, th y i v lp ti liu cho cc h thng s. Nh t bit, mt
h thng s c rt nhiu ti liu m t. c th vn hnh bo tr s
ch mt h thng t cn tm hiu k lng ti liu . V i mt ngn
ng m phng phn cng tt vic xem xt cc ti liu m t tr n n d

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Thc hnh nng cao

dng hn v b ti liu c th c thc thi m phng hot ng

c h thng. Nh th t c th xem xt ton b cc phn t c h
thng hot ng trong mt m hnh thng nht.
VHDL c pht trin nh mt ngn ng c lp khng gn v i
bt k mt phng php thit k, mt b m t h y cng ngh phn
cng no. Ngi thit k c th t do l chn cng ngh, phng
php thit k trong khi ch s dng mt ngn ng duy nht. V khi em
so snh v i cc ngn ng m phng phn cng khc k r tr n t
thy VHDL c mt s u im hn hn cc ngn ng khc:
- Th nht l tnh cng cng: VHDL c pht trin d i s bo
tr c chnh ph M v hin n y l mt ti u chun c IEEE. VHDL
c s h tr c nhiu nh sn xut thit b cng nh nhiu nh cung
cp cng c thit k m phng h thng.
- Th h i l kh nng h tr nhiu cng ngh v phng php thit
k. VHDL cho php thit k bng nhiu phng php v d phng
php thit k t tr n xung, h y t d i l n d vo cc th vin sn
c . VHDL cng h tr cho nhiu loi cng c xy dng mch nh s
dng cng ngh ng b h y khng ng b, s dng m trn lp trnh
c h y s dng mng ngu nhi n.
- Th b l tnh c lp v i cng ngh: VHDL hon ton c lp
v i cng ngh ch to phn cng. Mt m t h thng dng VHDL
thit k mc cng c th c chuyn thnh cc bn tng hp mch
khc nh u tu thuc cng ngh ch to phn cng m i r i n c th
c p dng ng y cho cc h thng thit k .
- Th t l kh nng m t m rng: VHDL cho php m t hot
ng c phn cng t mc h thng s cho n mc cng. VHDL c
kh nng m t hot ng c h thng tr n nhiu mc nhng ch s
dng mt c php cht ch thng nht cho mi mc. Nh th t c th
m phng mt bn thit k b o gm c cc h con c m t chi tit.
- Th nm l kh nng tr o i kt qu: V VHDL l mt ti u
chun c chp nhn, n n mt m hnh VHDL c th chy tr n mi
b m t p ng c ti u chun VHDL. Cc kt qu m t h thng
c th c tr o i gi cc nh thit k s dng cng c thit k khc
nh u nhng cng tun theo ti u chun VHDL. Cng nh mt nh m
thit k c th tr o i m t mc c o c cc h thng con trong mt
h thng l n (trong cc h con c thit k c lp).

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Thc hnh nng cao

- Th su l kh nng h tr thit k mc l n v kh nng s dng

li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc
c o, v vy n c th c s dng thit k mt h thng l n v i s
th m gi c mt nh m nhiu ngi. B n trong ngn ng VHDL c
nhiu tnh nng h tr vic qun l, th nghim v chi s thit k. V
n cng cho php dng li cc phn c sn.

1.5. ode cua

DL trong verilog

/**
* A behavioural model of a pipelined MAC unit. The two 4-bit
inputs are
* multiplied in an 8-bit multiplier, with the result added to a 10-bit
* accumulator. The number of pipe stages is set by the 'stages'
parameter,
* which defaults to 1.
*
* RST Synchronous reset
* C Clock
* A[3:0] Data Input
* B[3:0] Data Input
* Q[9:0] Accumulator output
*/
module MAC1
(input RST, CLK,
input [3:0] A, B,
output [9:0] Q);
parameter stages = 1;
reg [7:0]

Nhm 14

mul;

10

Thc hnh nng cao

reg [9:0]
integer

sum[stages-1:0];
i;

always @(posedge CLK) begin

for(i=stages-1; i>0; i = i-1)
sum[i] = sum[i-1];
if(RST)
sum[0] = 0;
else begin
mul = A * B;
sum[0] = sum[0] + mul;
end
end
assign Q = sum[stages-1];
endmodule

Nhm 14

11

Thc hnh nng cao

P N 2

TM
I. TN

U V VER LO
QU N V VER LO

Verilog HDL l mt trong h i ngn ng m phng phn cng

thng dng nht, c dng trong thit k IC, ngn ng ki l
VHDL.
HDL cho php m phng cc thit k d dng, s ch li, hoc
thc nghim bng nhng cu trc khc nh u. Cc thit k c m
t trong HDL l nhng k thut c lp, d thit k, d tho g, v
thng d c hn dng biu , c bit l cc mch in l n.
Verilog thng c dng m t thit k n dng
Thut ton (mt s lnh ging ngn ng C nh: if, c se,
for,while).
Chuyn i th nh ghi (kt ni bng cc biu thc Boole n).
Cc cng kt ni( cng: OR, AND, NOT).
Chuyn mch (BJT, MOSFET). Ngn ng ny cng ch r cch
thc kt ni, iu khin vo/r trong m phng.
u trc chng trnh dng ngn ng Verilog
// Khai bo module
Module t n chng trnh (t n bin I/O); // t n chng trnh trng
tn file.v.
Input [msb:lsb] bin;
Output [msb:lsb] bin;
Reg [msb:lsb] bin reg;
Wire [msb: lsb] bin wire;
// Kh i bo khi lw ys, hoc khi initi l.
cc lnh
Endmodule

Nhm 14

12

Thc hnh nng cao

II.

NN

T VN

TRON

VER LO

Nhng tp tin vn bn ngun Verilog b o gm nhng biu hin

thuc tnh t vng s u y:
1. Khong trng

Khong trng ngn nhng t v c th ch khong cch, khong

di, dng m iv dng ng dn. Do , mt lnh c th r
nhiu dng phc tp hn m khng c nhng c tnh c bit.
2. Ch gii

Nhng ch gii c th ch nh bng h i cch: ( ging trong

C/C++)
Ch gii c vit s u h i du gch xi n (//). c vit tr n cng
mt dng.c vit gi /* */, khi vit nhiu dng ch gii.
3. Ch s:

Lu tr s c nh ngh nh l mt con s c cc bit, gi tr c

th l: s nh phn, bt phn, thp phn, hoc thp lc phn.
V d 3b001, 5d30 = 5b11110,
16h5ED4 = 16d24276 = 16b0101111011010100
4. T nh danh:

T nh d nh do ngi dng quy nh cho bin s, t n hm, t n

mun, t n khi v t n trng hp. T nh d nh bt u bng mt
mu t hoc ng gch d i _ ( khng bt u bng mt con s
hoc $ ) v k c mi ch s c mu t, nhng con s v ng
gch d i, t nh d nh trong Verilog th phn bit dng ch.
5. C php:

K hiu cho php:

ABDCE bcdef1234567890_$
Khng cho php: cc k hiu khc -, &, #, @
6. Ton t:

Ton t l mt, h i, hoc b k t dng thc hin cc ton hng

tr n bin. Cc ton t b o gm >, +, &, !=.

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13

Thc hnh nng cao

7. T khaVerilog:

C nhng t m phi c ngh c bit trong Verilog. V d:

assign, case, while, wire, reg, and, or, nand, v module. Chng
khng c dng nh t nh d nh. T kh Verilog cng b o
gm c ch dn chng trnh bi n dch v System T sk (h thng
son tho) v cc hm.
.

N TRON

VER LO

Cc cng logic c s l mt b phn c ngn ng Verilog. C h i

c tnh c ch r l: drive_strenght v del y.
Drive_strenght ch sc bn c cng. bn ng r l s kt ni
mt chiu n ngun, k to n n s kt ni trong sut tr ns dn,
kt thc l tng tr ko l n hoc xung. Drive_strenght thng
khng c ch r, trong trng hp ny bn mc nh l
strong1 v strong0 .
Delay: nu del y khng c ch r, th khi cng khng c tr
hon truyn ti; nu c h i del y c ch nh, th tr c ti n l
mi u t tr hon l n, th h i l tr hon xung. Nu ch c mt
del y c ch nh, th khi tr hon l n xung l nh nh u.
Del y c b qu trong tng hp. Phng php c s tr hon
ch nh ny l mt trng hp c bit c P r meterized
Modules. Cc th m s cho cc cng c s phi c nh ngh
tr c nh del y.
1. Cc cng c bn:

Cc cng c bn c mt ng r , v c mt hoc nhiu ng vo.

Trong cc cng, c php c th biu din b n d i, cc t kho c
cc cng: nd, or, n nd, nor.
1.1. C php:

GATE (drive_strength)#(delays)
T n t kh cng _t n (output, input_1, input_2, , input_N);
Delay: #( l n, xung) hoc #l n_vxung hoc #( l n_vxung)

Nhm 14

14

Thc hnh nng cao

1.2. V d:

And c1 (o, , b, c. d); // c 4 ng vo cng And gi l c1

c2 (p, f, g); // v 2 ng vo cng nd gi l c2
Or #(4,3) ig ( o, b, c); // cng Or c gi l ig, rise time = 4, f ll
time = 3
Xor #(5) xor1 ( , b, c); // s u 5 n v thi gi n th = b xor c
2. Cng buf, not:

Cc cng ny thc thi m v o theo theo th t mh sn.

Chng c mt ng vo, h i h y nhiu ng r . C php c th biu
din b n d i, t kho buf, not.
2.1. C php:

T n t kh

cng _t n (output_1, output_2, , output_N, input);

2.2. V d:

Not #(5) not_1( ,c); // s u 5 n v thi gi n th = o c

Buf c1 (o, p, q, r, in); // b m 5 ng r v 2 ng r
c2 (p, f, g);
IV. D N

D L

I. t gi tr:

Verilog b o gm 4 gi tr c bn. Hu ht cc dng d liu Verilog

ch cc
gi tr s u:
0: mc logic 0, hoc iu kin s i.
1: mc logic 1, hoc iu kin ng.
X: mc logic tu nh
Z: trng thi tng tr c o.
X v Z dng c gi i hn trong tng hp (synthesis)
II. Wire:

M t vt liu ng dy dn trong mt mch in v c dng

kt ni cc cng h y cc module. Gi tr c Wire c th c,
nhng khng c gn trong hm (function) hoc khi (block).
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15

Thc hnh nng cao

Wire khng lu tr gi tr c n nhng vn phi c thc thi bi

1 lnh gn k tip h y bi s kt ni Wire v i ng r c 1 cng
hoc 1 module. Nhng dng c bit khc c Wire:
W nd(wired_ nd): gi tr ph thuc vo mc logic And ton b b
iu khin kt ni n Wire.
Wor (wired_or): gi tr ph thuc vo mc logic Or ton b b
iu khin kt ni n Wire.
Tri(three_st te): tt c b iu khin kt ni n 1 tri phi trng
thi tng tr c o.
1. C php:
Wire [msb:lsb] tn bin wire.
Wand [msb:lsb] t n bin w nd.
Wor [msb:lsb] t n bin wor.
Tri [msb:lsb] t n bin tri.
2. V d:
Wire c;
Wand d;
Assign d= a;
Assign d= b;// gi tr d l mc logic c php And v b.
Wire [9:0] A; // vect A c 10 wire.
III. Reg:

Reg (register) l mt i tng d liu m n ch gi tr t mt

th tc gn k tip. Chng ch c dng trong hm v khi th
tc. Reg l mt loi bin Verilog v khng nht thit l th nh ghi
t nhi n. Trong th nh ghi nhiu bit, d t c lu tr bng nhng
ch s khng du v khng c k hiu ui m rng, c thc
hin m ngi s dng c ch y l s b h i.
1. C php:
Reg [msb:lsb] t n bin reg.
2. V d:
Reg ; // bin th nh ghi n gin 1 bit.
Reg [7:0] A; // mt vect 8 bit; mt b nk c 8 th nh ghi.
Reg [5:0]b, c; // h i bin th nh ghi 6 bit.

Nhm 14

16

Thc hnh nng cao

IV. Input, Output, Inout:

Nhng t kho ny biu th ng vo, ng r , v port h i chiu c

mt module hoc t sk. Mt port ng r c th c cu hnh t cc
dng: wire, reg, w nd, wor, hoc tri. Mc nh l wire.
1. C php:
Input [msb:lsb] port ng vo.
Output [msb:lsb] port ng ra.
Inout [msb:lsb] port ng vo,r h i chiu.
2. V d:
Module sample (b, e, c, a);
Input ; // mt ng vo mc nh l kiu wire.
Output b, e; // h i ng r mc nh l kiu wire.
Output [1:0] c; /* ng r h i bit, phi c kh i botrong mt lnh
ring*/
Reg [1:0] c; // ng c c kh i bo nh mt reg.
I. Integer (S nguyn):

Integer l mt bin nng. Trong tng hp chng c dng ch

yu cho vng lp, th m s, v hng s. Chng hon ton l reg.
Tuy nhi u chng ch d liu bng nhng s c du, trong khi
kh i bo dng reg ch chung bng s khng du. Nu chng ch
nhng s m khng nh ngh thi gi n bi n dch th kch th c
mc nh l 32 bit. Nu chng ch hng, s tng hp iu chnh
cc s c kch th c nh nht cn thit cho s bi n dch.
1. C php:
Integer t n bin nguy n;
t n hng nguy n;
2. V d:
Integer ; // s nguy n n gin 32bit.
Assign b= 63; // mc nh l mt bin 7 bit.
II. Supply 0, Supply1:

Xc nh ch ng dn l n mc logic 0 ( t), logic 1( ngun)

theo th t nh sn.

Nhm 14

17

Thc hnh nng cao

III. Time:

Time l mt lng 64 bit m c s dng cng v i $time, h

thng th o tc ch lng thi gi n m phng. Time khng c
h tr tng hp v v th ch c dng trong mc ch m phng.
1. C php:
Time bin time;
2. V d:
Time c;
c = $time; // c = thi gi n m phng dng in.
IV. Parameter (Tham s):

Mt P r meter xc nh 1 hng s m c t khi bn cho v d

c th l mt module. Cc ny cho php t c th s ch .
1. C php:
Parameter p r_1= gi tr, p r_2= gi tr, ;
Parameter [gi i hn] p r_3 = gi tr;
2. V d:
Parameter dd = 2b00, sub = 3b111;
Parameter n = 4;
Parameter [3:0] p r_2 = 4b1010;

reg [n-1:0] h rry;// mt th nh ghi 4 bt m rng c t bi

th m s n
trn.
always @(x)
y = {{(add - sub) {x}}}
if (x) begin
state = par_2[1];
else
state =par_2[2];
end.

Nhm 14

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Thc hnh nng cao

V. TON T
I. Ton t s hc:

Nhng ton t ny thc hin cc php tnh s hc. Du + v -

c th c s dng mt trong h i ton t n (-z) hoc kp (x y).
Ton t
+, -, *, /, %.
II. Ton t quan h:

Ton t qu n h so snh h i ton hng v tr v mt n bit l 0

hoc 1.Nhng ton t ny tng hp vo dng c so snh. Bin
Wire v Reg l nhng bin dng. V th, (-3b001) = (3b111) v (3b001) > ( 3b110) nhng nu l s nguy n th -1< 6.
c ton t quan h
<, <=, >, >=, = =, !=.
III. Ton t bit_wire:

So snh tng bit h i ton ton hng.

c ton t
~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwire
XOR), ~^ hoc ^~ (bitwire XNOR).
IV. Ton t logic:

Ton t logic tr v 1 bit n 0 hoc 1. chng ging nh ton t

bitwire ch l nhng ton hng n bit. Chng c th lm vic tr n
biu thc, s nguy n hoc nh m bit, v coi nhu tt c cc gi tr
khng bng 0 l 1. Ton t logic c dng nhiu trong lnh iu
kin (if else), khi chng lm vic tr n biu thc.
Ton t
!(NOT), && (AND), || (OR)
Wire [7:0] x, y, z;
Reg a;

if ((x= = y)&&(z)) a=1;

else a=! x;

Nhm 14

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Thc hnh nng cao

V. Ton t bin i:

C tc dng tr n tt c cc bit c mt vect ton hng v tr v

gi tr nbit. Nhng ton t ny l hnh thc t i s c cc
ton t bitwire tr n.
c ton t
~ (bin i NOT), & (bin i AND), ~&( bin i NAND), | (bin
i OR), ~|
(bin i NOR), ^ (bin i XOR), ~^ hoc ^~ (bin i XNOR).
VI. Ton t ghp:

Dch ton t u bng ch s c cc bit c nh ngh bi ton

t thou h i.V tr cn trng s c in vo v i nhng s 0 cho c
h i trng hp dch tri hoc phi.
Ton t
<< ( dch tri), >> (dch phi).
VII. Ton t dch:

Ghp h i hoc nhiu ton hng thnh mt vect l n.

Ton t
{} (concatenation)
Wire [2:0] x;
Wire [3:0] y, Z;
To r nhiu bn s o c mt mc chn.
Ton t:
{n{ mc chn }} n nh m th bn trong mt mc chn.
VIII. Ton t iu kin:

Ging nh C/C++. Chng nh gi mt trong h i biu thc c bn

trong mt iu kin. N s tng hp thnh b cng (MUX).
Ton t
(iu kin)? kt qu khi iu kin ng : kt qu khi iu kin s i.
IX. Th t ton t:

Nhng ton t trong mc ging nh u nh gi t tri s ng phi

Nhm 14

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Thc hnh nng cao

Ton t
[]

Tn

Chn bit, chn phn

Phn trong ngoc n
()
Mc logic v bit_wire NOT
!,~
&, |, ~&, ~|, ^, ~^ Bin i: AND, OR, NAND, NOT, XOR,
XNOR.
+, Du ch s m s dng.
{}
Ghp ni { 3b101,3b110} = 6b101110
{{ } }
Th bn {3{3b101 } }=9b101101101
*, /, %
Nhn, chi , phn trm.
+, Cng tr nh phn.
<<, >>
Dch tri, phi.
<, <=, >, >=
Du so snh. Bin Reg v wire c ly bng
nhng s
dng.
= =, !=
Bng v khng bng trong ton t logic.
&
Bit_wire AND, nd tt c cc bit v i nh u.
^, ~^
Bit_wire XOR, Bit_wire XNOR.
|
Bit_wire OR.
&&, ||
Ton t logic AND, OR.
?:
x = ( iu kin ) T:F

V .TON

I. Literals (dng k t):

L ton hng c gi tr khng i m c dng trong biu thc

Verilog. C h i dng k t l:
hui: l mt mng c nhiu k t c t trong du .
h s: l nhng s khng i, nh phn, bt phn, thp phn,
hoc s hex.
1. php cc ch s
nF dddd
Trong :
n : s nguy n mi u t s bit.
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Thc hnh nng cao

F: mt trong bn nh dng s u: b( s nh phn), o( s bt phn), d(

s thp
phn), h( s hex).
2. V d
time is// chui k t.
267 // mc nh 32 bit s thp phn.
2b01 // 2 bit nh phn.
20h B36E // 20 bit s hex.
o62 // 32 bit bt phn.
II. Chn 1 phn t bit v chn 1 phn cc bit.

y l s l chn mt bt n hoc mt nh m bit theo th t, t

mt wire, reg hoc t th m s t trong ngoc [ ]. Chn 1 phn t
bit v chn 1 phn cc bit c th c dng nh l cc ton hng
trong biu thc bng nhiu cch thc ging nh u m cc i tng
d liu gc c dng.
1. C php:
T n bin [ th t bit].
T n bin [ msb: lsb].
2. V d:
Reg [7:0] a, b;
Reg [3:0] ls;
c = a[7] & b[7];
ls = a[7:4] + b[3:0];
III. Gi hm chc nng:

Gi tr tr v c mt hm c th c dng trc tip trong biu

thc m khng cn gn tr c cho bin reg hoc wire. Gi hm
chc nng nh l mt trong nhng ton hng. Chiu rng bt c
gi tr tr v chc chn c bit tr c.
1. C php:
T n hm(d nh sch bin).
2. V d:
Assign a = b & c & chk_bc(b, c);
Function chk_bc;

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Thc hnh nng cao

Input c, b;
Chk_bc = b^ c;
Endfunction
IV. Wire, reg, v tham s:

Wire, reg, v th m s c th uc dng nh l cc ton hng trong

biu thc
Verilog.
VII. MODULES
I. Khai bo modules:

Mt module l bn thit k ch yu tn ti trong Verilog. Dng

u ti n c kh i bo module ch r d nh sch t n v port (cc i
s). Nhng dng k tip ch r dng I/O (input, output, hoc inout)
v chiu rng c mi port. Mc nh chiu rng port l 1 bit.
S u , nhng bin port phi c kh i bo wire, w nd, , reg.
Mc nh l wire. Nhng ng vo c trng l wire khi d liu
c cht be n ngoi module. Cc ng r l dng reg nu nhng
tn hiu c chng c ch trong khi lw ys hoc initi l.
1. C php:
Module tn module (danh sch port);
Input [msb:lsb] danh sch port ng vo;
Output [msb:lsb] danh sch port ng ra;
Inout [ msb:lsb ] danh sch port vo_ ra;
cc lnh
endmodule
2. V d
Module add_sub(add, in1, in2, out);
Wire, reg, v tham s
Input[7:0 ] in1, in2;
Wire in1, in2;
Output [7:0] out;
Reg out;
cc lnh khc
Endmodule
Nhm 14

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Thc hnh nng cao

II. Ch nh lin tip:

Cc ch nh li n tip c dng gn mt gi tr l n tr n mt
wire trong mt module. l cc ch nh thng thng b n ngoi
khi lw ys hoc khi initi l. Cc ch nh li n tip c thc hin
v i mt lnh gn ( ssign) r rng hoc bng s ch nh mt gi tr
n mt wire trong lc kh i bo. Ch rng, cc lnh ch nh li n
tip th tn ti v c chy li n tc trong sut qu trnh m
phng. Th t cc lnh gn khng qu n trng. Mi th y i b n
phi c bt c ng vo s lp tc th y i b n tri c cc ng r .
1. C php:
Wire bin wire = gi tr;
Assign bin wire = biu thc;
2. V d
Wire [ 1:0 ] = 2b 01;
Assign b = c &d;
Assign d = x | y;
III. Module instantiations:

Nhng kh i bo module l nhng khun mu m n c to n n

t cc i tng thc t ( inst nti tion). Cc module n c b n
trong cc module khc, v mi dn chng to mt i tng c
nht t khun mu. Ngoi tr l module mc tr n l nhng dn
chng t chnh chng. Cc port c module v d phi th nhng
dnh ngh trong khun mu. y l mt l thuyt: bng t n, s
dng du chm(.) .t n port khun mu ( t n c wire kt ni n
port). Bng v tr, t nhng port nhng v tr ging nh u trong
d nh sch port c c khun mu ln inst nce.
1. C php:
T n inst nce1 (d nh sch kt ni port );
T n inst nce2(d nh sch kt ni port);

2. V d
// nh ngh module
module and4(a,b,c);
input [3:0]a,b;
Nhm 14

24

Thc hnh nng cao

output [3:0]c;
assign c = a&b;
endmodule
// module instantiations
wire [3:0] in1, in2;
wire [3:0] o1, o2;
// t v tr
and4 C1(in1, in2,o1);
// tn
and4 C2(.c(o2), .a(in1), .b(in2));
V

U N MU

V ( E

V OR L)

Verilog c 4 mc khun mu:

Chuyn mch. Khng c cp n y.
Cng.
Mc trn d liu.
Hnh vi hoc th tc c cp b n d i
Cc lnh th tc Verilog c dng to mt mu thit k mc
c o hn. Chng ch r nhng cch thc mnh c vc lm r
nhng thit k phc tp. Tuy nhi n, nhng th y i nh n phng
php m h c th g y r bin i l n trong phn cng. Cc lnh
th tc ch c th c dng trong nhng th tc.
I. Nhng ch nh theo th tc:

L nhng ch nh dng trong phm vi th tc Verilog (khi

lw ys v initi l). Ch bin reg v integers (v chn n bit/ nh m
bit c chng, v kt ni thng tin) c th c t b n tri du =
trong th tc. B n phi c ch nh l mt biu thc m c th
dng bt c dng ton t no.
II. Delay trong ch nh:

Trong ch nh tr t l khong thi gi n tri qu tr c khi mt

lnh c thc thi v b n tri lnh gn c to r . V i nhiu ch
nh tr (intr - ssignment del y), b n phi c nh gi tr trc
Nhm 14

25

Thc hnh nng cao

tip nhng c mt del y c t tr c khi kt qu c t b n tri

lnh gn. Nu th m mt qu trnh th y i n cnh b n phi tn
hiu trong khong thi gi n t,th khng cho kt qu ng r .
Del y khng c h tr bi cc cng c.
1. C php ch nh th tc:
Bin = biu thc;
Ch dnh tr:
#t bin = biu thc;

intra_assignment delay:
bin = #t biu thc.
III. Ch nh khi:

Ch nh khi (=) thc hin li n tc trong th t lnh c vit.

Ch nh th h i khng c thc thi nu nh ch nh u cho
hon thnh.
1. C php:
Bin = biu thc;
Bin = #t biu thc;
#t bin = biu thc;
IV. Begin end:

Lnh khi begin end c dng nh m mt vi lnh m mt

lnh c php c cho php. B o gm function, khi lw ys v
khi initi l. Nhng khi ny c th c ty gi t n. V b o gm
kh i bo reg, integer, th m s.
1. C php:
Begin: t n khi
Reg[msb:lsb] d nh sch bin reg;
Integer [msb:lsb] danh sch integer;
Parameter [msb:lsb] d nh sch th m s;
cc lnh
End

Nhm 14

26

Thc hnh nng cao

V. Vng lp for:

Ging nh c/c++ c dng thc hin nhiu ln mt lnh hoc

khi lnh.Nu trong vng lp ch ch mt lnh th khi begin
end c th b qu .
1. C php:
For (bin m = gi tr 1; bin m </ <=/ >/ >= gi tr 2;
bin m = bin m +/- gi tr)
begin
lnh
end
VI. Vng lp while:

Vng lp while thc hin nhiu ln mt lnh hoc khi lnh cho
n khi biu thc trong lnh while nh gi l s i.
1. C php:
While (biu thc)
Begin
cc lnh
End
VII. Khi lnh if else if else:

Thc hin mt lnh hoc mt khi lnh ph thuc vo kt qu c

biu thc theo s u mnh if.
C php
If (biu thc)
Begin
cc lnh
end
else if (biu thc)
Begin
cc lnh
end
else
Begin
cc lnh

Nhm 14

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Thc hnh nng cao

end
VIII. Case:

Lnh c se cho php l chn trng hp. Cc lng trong khi

def ult thc thi khi khng c trng hp l chn so snh ging
nh u. Nu khng c s so snh, b o gm c def ult, l ng, s
tng hp s to r cht khng mong mun.
1. C php:
Case (biu thc)
Case 1:
Begin
cc lnh
end
Case 2:
Begin
cc lnh
end
Case 3:
Begin
cc lnh
end

default:
begin
cc lnh
end
endcase
X.

LW YS V

NT

I. Khi always:

L cu trc chn trong khun mu RTL (Register Transfer Level).

Ging ch nh li n tc, y l trng thi tn ti m c thc thi
li n tc trong khi m phng. Ci ny cng c ngh l tt c cc
khi lw ys trong mt module thc thi mt cch li n tc. Khi

Nhm 14

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Thc hnh nng cao

lw ys c th c dng trong cht, flip flop h y cc kt ni logic.

Nu cc lnh c khi lw ys nm trong phm vi khi begin end
th c thc thi li n tc, nu nm trong khi fort join, chng
c thc thi ng thi (ch trong m phng). Khi lw ys thc
hin bng mc, cnh l n hoc cnh xung c mt h y nhiu tn
hiu (cc tn hiu cch nh u bi t kh OR).
C php:
Always @(s kin 1 or s kin 2 or)
Begin
cc lnh
end
Always @(s kin 1 or s kin 2 or)
Begin: t n khi
cc lnh
End
II. Khi initial

Ging nh khi lw ys nhng khi initi l ch thc thi mt ln t

lc bt du c qu trnh m phng. Khi ny th ti u biu bin
khi chy v ch nh dng s ng tn hiu trong lc m phng.
1. C php:
Initial
Begin
cc lnh
End
2. V d
Initial
Begin
Clr = 0;
Clk = 1;
End
Initial
Begin
= 2b00;
#50 = 2b01;
Nhm 14

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Thc hnh nng cao

#50 = 2b10;
End
X. HM

Hm c kh i bo trong phm vi mt module, v c th c gi

t nhng lnh li n tc, khi lw ys, hoc nhng hm khc. Trong
lnh ch nh li n tc, cng c ch nh li n tc khi bt k cc
hm kh i bo ng vo th y i. Trong chng trinh chng c
ch dng t i khi cn gi. Cc hm m t s kt ni logic, v khng
to r cht. Do mt lnh if m khng else se m phng , mc d
n c cht d liu nhng m phng th khng c . y l trng
hp d c tng hp khng c m phng theo s u. y l khi
nim tt m h hm, v vy chng s khng to r cht nu m
hm c dng trong mt chng trnh.
I. Khai bo hm:

Kh i bo hm l ch r t n hm, chiu rng c hm gi tr tr v,

i s hm d liu vo, cc bin (reg) dng trong hm, v th m s
cc b c hm, s nguy n c hm.
1. C php:
Function [msb:lsb] tn hm;
Input [msb:lsb]bin vo;
Reg [msb:lsb]bin reg;
Parameter [msb:lsb] th m s;
Integer [msb:lsb] s nguy n;
cc lnh
Endfunction
XI.

NN

LN

Cht d liu (l tches): c suy nu mt bin, mt trong cc bit

khng c gn trong cc nhnh c mt lnh if. Cht d liu
cng c suy r t lnh c se nu mt bin c gn ch trong mt
vi nhnh.

Nhm 14

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Thc hnh nng cao

Hon thin m c th c c dng lnh if tng hp cht v

tht kh ch nh r rng. Theo l thuyt, mt s xc lp hp l
n n c suy r t m Verilog.
C php:
If else if else v c se.
I. Thanh ghi Edge_triggered, flip_flop, b m:

Mt th nh ghi (flip_flop) c suy lun bng vic dng xung kch

cnh l n
hoc xung trong d nh sch s kin c lnh khi lw ys.
C php:
Always @(posedge clk or posedge reset1 or nesedge reset2)
Begin
If (reset1) begin
Cc ch nh reset
end
else if (reset2) begin
Cc ch nh reset
End
Else begin
Cc ch nh reset
End
II. B a cng:

c suy r bi vic gn mt bin m gi tr mi bin khc nh u

trong mi nhnh c lnh if hoc c se. C th trnh cc ch nh v
mi nhnh c th tn ti bng vic s dng ngoi nhng nhnh
mc nh. Ch rng cht s c to r nu mt bin khng c
gn cho cc iu kin nhnh c th tn ti. hon thin m c th
c c, dng lnh c se to mu cng l n.
III. B cng, tr:

Ton t cng tr trong b cng tr m c chiu rng ph thuc

vo chiu rg c ton t l n hn.

Nhm 14

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Thc hnh nng cao

IV. B m 3 trng thi:

B m b trng thi c suy r nu bin c gn theo iu kin

gi tr tng tr c o Z dng mt trong cc ton t: if, c se,
V. Cc linh kin khc:

Hu ht cc cng logic c suy r t vic dng nhng ton hng

tng ng c chng. Nh mt s l chn mt cng hoc mt
thnh phn c th c gii thch r rng bng v d c th v s
dng cc cng c s ( nd, or, nor, inv) min l bng ngn ng
Verilog.

Nhm 14

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Thc hnh nng cao

PHN 3: MT S V D
1.V D 1
a.Chng trnh tnh NOR cc bt ca bin vo
module vdcong(in,out);
input[3:0] in;
output out;
assign out= ~|in;
endmodule

b. M phng

Nhm 14

33

Thc hnh nng cao

2.v d
.chung trnh cng 2 bin 4 bt

.M

Nhm 14

P N

34

Thc hnh nng cao

3. v d 3
a. Chung trnh gii m 2 sang 4

Nhm 14

35

Thc hnh nng cao

.m phng

Nhm 14

36

Thc hnh nng cao

4. v d 4
a.B dn knh 2 sang 1

Nhm 14

37

Thc hnh nng cao

. m phng

Nhm 14

38

Thc hnh nng cao

5.v d 5
.chng trnh chuyn i BCD s ng 7 on

Nhm 14

39

Thc hnh nng cao

Nhm 14

40

Thc hnh nng cao

b.m phng

6.v d 6
a. Chng trnh gimt 0 xung 9, hin th ra led 7 on

Nhm 14

41

Thc hnh nng cao

Nhm 14

42

Thc hnh nng cao

. m phng

Nhm 14

43

Thc hnh nng cao

7. v d 7
a. chng trng tng t 0 n 9 hin th ra led 7 on

Nhm 14

44

Thc hnh nng cao

Nhm 14

45

Thc hnh nng cao

.m phng

Nhm 14

46

Thc hnh nng cao

PHN 4:THIT K SEQUENTIAL

LOGIC USING UDP DNG VERILOG

//CC PHN
//

P P T

T DN

T
P N

P P S U

D LACTH
1 primitive latch_udp(q, clock, data) ;
2 output q; reg q ;
3 input clock, data;
Table
4 // clock data
q
q+
0
1
: ? : 1 ;
0
0
: ? : 0 ;
1
?
: ? : - ; // - = no change
5 endtable
6 endprimitive

D Flip Flop
1 //---------------------------------------------------2 // Design Name : dff_udp
3 // File Name
: dff_udp.v
4 // Function
: D Flip Flop
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 primitive dff_udp (q,clk,d);
8
input clk,d;
Nhm 14

47

Thc hnh nng cao

9
output q;
10
reg q;
11
table
12
// clk d
13
r 0
14
r 1
15
f ?
16
? *
17
endtable
18 endprimitive

:
:
:
:
:

q
?
?
?
?

:
:
:
:
:

q+
0 ;
1 ;
- ;
- ;

SR Flip Flop
1 primitive srff_udp (q,s,r);
2 output q;
3 input s,r;
4
5 reg q;
6
7 initial q = 1'b1;
8
9 table
10
// s r q q+
11
1 0 : ? : 1 ;
12
f 0 : 1 : - ;
13
0 r : ? : 0 ;
14
0 f : 0 : - ;
15
1 1 : ? : 0 ;
16 endtable
17
18 endprimitive

Nhm 14

48

Thc hnh nng cao

JK Flip Flop
1 //---------------------------------------------------2 // Design Name : jkff_udp
3 // File Name
: jkff_udp.v
4 // Function
: JK Flip Flop Using UDP
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 primitive jkff_udp (q,clk,j,k);
8 input clk,j,k;
9 output q;
10 reg q;
11 table
12
// clk j k : q : q+
13
r 0 0 : ? : - ;
14
r 0 1 : ? : 0 ;
15
r 1 0 : ? : 1 ;
16
r 1 1 : 0 : 1 ;
17
r 1 1 : 1 : 0 ;
18
f ? ? : ? : - ;
19
? * ? : ? : - ;
20
? ? * : ? : - ;
21 endtable
22 endprimitive

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t lu n
Vic ging dy phng php thit k s dng Verilog l rt cn thit i v i
sinh vi n in t vin thng - cng ngh thng tin. i v i sinh vi n th vic
trin kh i nghi n cu v ng dng c Verilog trnh by tr n qu thc
rt c ngh . Hiu qu c vn khng phi ch l nm bt c nhng
tin b m i c kho hc n i chung, cng ngh ch to phn cng n i ri ng
m chnh Verilog s l mt phng thc h tr ging dy tht hu hiu, n
s gip cho cc mn hc vi x l, kin trc my tnh, tr n n b t tru tng
hn. Hin n y Verilog v ng c s dng rt ph bin trong cc
phng thc hnh th nghim in t-Vin thng cc trng i hc tr n
th gi i, v ng c nhiu cng ty in t - vin thng - tin hc s dng
thit k, pht trin cc sn phm c mnh.. Cc mn hc phng php
thit k s dng Verilog s tr ng b cho sinh vi n mt phng php thit k
cc h thng s ti n tin t sinh vi n c th phn tch v thit k c cc
thit b, h thng in t s ng dng trong ngnh in t - vin thng c
hiu qu c o. Do thi lm bi tp c hn v nhng hn ch khng trnh khi
c vic hiu bit cc vn d tr n l thuyt l chnh n n bi tp c
nh m em chc chn khng trnh khi nhng thiu s t. Chung em rt mong
c c nhng kin nh gi, g p c cc thy v cc bn bi tp c
chng em th m hon thin.
S u thi gi n lm bi tp. Chng em rt r c rt nhiu kinh
nghim cho bn thn, cng l nh vo s ch dy nhit tnh c cc thy
c v s gip c cc bn.
Chng em xin chn thnh cm n !

i
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T i liu tham kho

1.Verilog Digital System Design
2.Introduction of Verilog
3.Cadence Verilog XL Reference Manual
4.Synopsys HDL Compiler for Verilog Reference Manual
5.Diglad 10k10 Mannual
6.www.Syncad .com
7.TimingTool.com
8.www.maia-eda.net
9.http://tailieu.vn/xem-tai-lieu/tom-tat-bai-giang-verilog.174162.html
10. http:// www.eej.ulst.ac.uk/guide/guide.html
11. http:// www.eej.ulst.ac.uk/guide/syntax.html
12. http:// www.eej.ulst.ac.uk/tutor/Vhdnotes.html
13. VHDL : Active Tutorial ALDEC Cooperation
14.http:// www.xilinx.com

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