BiCMOS Two-Stage Operational Amplier

Increased second-stage transconductance --> boost second pole location First cut: replace M3, M4, M5 by Q3, Q4, Q5
V+

M8

M7 ISS

M6

_ vI1 IREF Q3 Q4 M1 M2

+ vI 2

+ Cc CL vO Q5

vo

(note that npn bipolar current mirror is necessary to avoid a systematic input offset voltage)

EE 105 Spring 1997 Lecture 38

First-Cut BiCMOS Two-Stage Op Amp (Cont.)

s

Drawback to rst-cut design

vi+

+ vd Gm1vd Rout1 Rin2

+ vi2 Gm2vi2 Rout

+ vo

vi

a vdo = g m1 ( r o2 r o4 r 5 )g m5 ( r o5 r o6 ) since the input resistance of the common-emitter is much smaller than the output reisstance of the input stage a vdo g m1 r 5 g m5 ( r o5 r o6 )
s

Reduced low-frequency gain is unacceptable

EE 105 Spring 1997 Lecture 38

Improved BiCMOS Two-Stage Op Amp

s

Increase input resistance of the second stage: insert a common-collector device Q11 and associated biasing transitors M12, M13, and M14. DC level of M2s drain is increased by VBE11 --> must add Q9 and Q10 to avoid a systematic input offset

V+

M8

M7 ISS VI1 + VI 2

M14

M6

M1

M2

Cc CL + vO Q5

IREF

Q9

Q10

vb11

Q11

Q3

Q4

M13

M12

EE 105 Spring 1997 Lecture 38

Small-Signal Performance
s

Low-frequency gain is increased:

a vdo = A dm1 A v, cc A v, ce = ( g m1 ( r o2 o r o10 ) ) A v, cc ( g m5 ( r o5 r o6 ) )

s

The common-collector gain is Av,cc = vo/vb5 and is about 1

a vdo g m1 r o2 g m5 ( r o5 r o6 )

low-frequency gain is much higher than rst-cut BiCMOS design

EE 105 Spring 1997 Lecture 38

Improved BiCMOS Two-Stage Design

s

Minimize power --> set IC11 = 25 A

V+ (75/3) M8 1 2 VI1 3 IREF Q9 M7 (150/3) M14 (37.5/3) M6 (150/3)

M1 (150/3)

M2 (150/3) 4 Q10

+ VI 2 Cc CL + vO Q5

vb11

Q11 5 M12 (12/3)

vb5 Q3 Q4 M13 (12/3)

V vertical npn bipolar transistor F = o = 100 IS = 1017 A VAn = 25 V F = 50 ps rb = 250 rc = 200 rex = 5 Cjeo = 8 fF Co = 22 fF Ccso = 41 fF mje = 0.5 mjc = 0.5 mjs = 0.5 Be = 0.95 V Bc = 0.79 V Bs = 0.71 V

EE 105 Spring 1997 Lecture 38

Small-Signal Performance and Frequency Response

s

Low-frequency differential gain a vdo = A dm1 A v, cc A v, ce = ( 212 ) ( 0.78 ) ( 525 ) = 86, 800 in decibels |avdo|dB = 99 dB

Second stage transconductance (composite CC/CE amplier) I C5 G m2 g m5 = -------- = 3.85 mS V th which is a factor of 10 higher than for the CMOS two-stage amplier As a result, the compensation capacitor is reduced to G m1 0.357 mS C c ---------- C L = ---------------------- ( 7.77 pF ) = 720 fF 3.85 mS G
m2

The exact result is Cc = 980 fF

s

Dominant pole 1 1 = ------------------------------------------------------------------- = 3.3 krad/s ( R out1 R out2 )G m2 R out C c 2 a vdo 1 300 Mrad/s ... which is much higher than for the CMOS op amp

EE 105 Spring 1997 Lecture 38

Simulation of Frequency Response

s

SPICE indicates that higher frequency poles reduce the unity-gain frequency Increasing the compensation capacitor to Cc = 1.3 pF results in 2 a vdo 1 1 = 2.6 krad/s and 2 240 Mrad/s BiCMOS op amp has a unity-gain bandwidth that is over 10 times greater than the CMOS op amp, at the cost of 1. use of a more complex (and expensive) BiCMOS technology 2. greater area 3. slightly higher DC power

EE 105 Spring 1997 Lecture 38

Op Amp Bode Plots

100 improved BiCMOS op amp

80 avd( j!) (dB) two-stage CMOS op amp 60

40

20

0 102 103 104 105 106 107 108

109 f (Hz)

CMOS Transistor Count Static Power Gain avdo VIC,max VIC,min VO,max VO,min Cc f1 f2 8 1.25 mW 82.4 dB 0.82 V 2.22 V 2.1 V 2.22 V 20 pF 202 Hz 3.3 MHz

Improved BiCMOS 14 1.5 mW 99.9 dB 0.82 V 2.1 V 2.1 V 2.4 V 1.3 pF 410 Hz
not

38.3 MHz

counting the reference current source.

EE 105 Spring 1997 Lecture 38