Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section.

Typically L = 0,1 to 3 m, W = 0,2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

The enhancement-type NMOS transistor with a positive voltage applied to the gate. An N channel is induced at the top of the substrate beneath the gate.

An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS. Note that the depletion region is not shown (for simplicity). The iDvDS characteristics of the MOSFET; when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt. Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is pinched off at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.

Derivation of the iD vDS characteristic of the NMOS transistor.

SATURATION REGION

ACTIVE REGION

The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.

Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a).

Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.

Operation of the CMOS inverter when vIN is high: (a) circuit with vIN = VDD (logic-1 level, or VOH). (b) graphical construction to determine the operating point. (c) equivalent circuit.

Operation of the CMOS inverter when vIN is low: (a) circuit with vIN = 0V (logic-0 level, or VOL). (b) graphical construction to determine the operating point. (c) equivalent circuit.

SATURATION REGION

ACTIVE REGION

(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iDvDS characteristics for a device with kn(W/L) = 1,0 mA/V2. (c) The iDvGS characteristic for an enhancement-type NMOS transistor (Vt = +1V, kn W/L = 1,0 mA/V2).

SATURATION REGION

ACTIVE REGION

The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = 4 V and kn(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated. (b) the iDvDS characteristics. (c) the iDvGS characteristics.

ESTRUCTURA ESQUEMTICA DE UN MOSFET DE ACUMULACIN (ENRIQUECIMIENTO) DE CANAL N, NMOS. Dos regiones de tipo N+ actan como conexiones de baja resistencia a la fuente y el drenador. Encima del sustrato de tipo P se forma una capa aislante de dixido de silicio, mediante la oxidacin del silicio. En las regiones N+ se forman contactos hmicos para conectar el dispositivo al circuito externo, que consisten en dos ventanas en el dixido de silicio cubiertas por una capa de aluminio. Normalmente el sustrato B se conecta al terminal de fuente. El canal se induce por la influencia de un campo elctrico; no existe un canal fsico entre drenador y fuente de un NMOS.

ESTRUCTURA ESQUEMTICA DE UN MOSFET DE ACUMULACIN (ENRIQUECIMIENTO) DE CANAL P, PMOS. El MOSFET incremental de canal P, tambin conocido como PMOS, se forma con dos regiones de tipo P+ sobre un sustrato de tipo N, como se muestra en la figura. Las regiones P ofrecen resistencias bajas. El smbolo de un PMOS es igual al de un NMOS, excepto que la direccin de la flecha se invierte.

POLARIZACIN DE UN TRANSISTOR NMOS Y DE UN PMOS. El transistor NMOS se opera con tensiones de puerta y drenador positivas con respecto a la fuente, tal y como muestra la figura (a), mientras que un transistor PMOS lo hace con tensiones de puerta y drenador negativas con respecto al terminal de fuente, figura (b). En ambos casos los sustratos estn conectados al terminal de fuente.