University of Michigan, EECS 511 Final Project: Comparator Based Switched Capacitor Implementation for Pipeline ADC

Comparator Based Switched Capacitor Implementation for Pipeline ADC

Jim Huang, Xiaohua Su, University of Michigan
down as follows: Section II will discuss the CBSC concept in detail, followed by section III, which introduces a practical realization of a pipeline ADC stage using this technique. Section IV discusses performance of the pipeline ADC designed using this technique.

AbstractThis paper presents design carried out for a 10-bit pipeline ADC implemented using Comparator Based Switched Capacitor (CBSC) concept. Each stage in the pipeline ADC is consisted of a core high gain, minimum delay comparator, the digital logic block that will take the output of the comparator as inputs, and output clock signals to regulate two current sources. The CBSC concept developed by Sepke et al allows for design of low power Pipeline ADC, since the comparator senses virtual ground condition, rather than forcing the virtual ground condition, in the case of traditional switched op amp design. Index Terms comparator based switched capacitor circuits, pipeline ADC, minimum delay comparator

II. CBSC CONCEPT Figure 1. shows a block diagram of a 10b pipeline ADC with 1.5b/stage digital correction introduced. Each stage is capable of resolving 2 bits, and the residue is propagated down the pipeline. The residue from each stage is amplified two times to maintain a constant Vref. Each of the ADC in the pipeline stages is implemented using switched capacitor op amp method [3]. Power dissipation of 4.8 mW is reported for the initial stage in the pipeline ADC, which requires the greatest accuracy [4].

IPELINE Analog-to-Digital Converter (ADC) is one of the most popular schemes used in industry today. It offers adequate resolution and speed for a wide range of applications. Al though it is not as fast as a flash ADC, the power consumption of a pipeline ADC can be much lower than that of a flash ADC. In todays applications, pipeline ADC is most often used in digital video devices and applications where delay in the digital circuit is tolerable [1]. Currently, most pipeline ADCs are designed using a switched op amp method. In which a high gain op amp is designed in conjunction with input/output referred offset cancellation. As process technology is scaled down further and further, from 0.25 m down to 90 nm and beyond, this creates a voltage limitation on the circuitry. It is projected that circuits will need to operate at a supply voltage of below 2.5V [2]. The increasing demand suggests that modern day analog integrated circuit must also be combined on the same chip as the digital parts, which means the performance of the analog circuitry is severely limited by the voltage limitation. For an op amp, lower VDD leads to lower output signal swing, as well as reduced intrinsic device gain. The device gain can be boosted by either cascading several gain stages, or introduce additional gain boosted amplifiers [3], but this would introduce additional poles that will in certain cases, severely limit the frequency response of the op amp. This paper discusses the concept of comparator based switched capacitor (CBSC) circuit, as well as its implementation on a pipeline ADC stage. The paper is broken

I. INTRODUCTION

Fig. 1. System block diagram of a 10b pipeline ADC with 1.5b/stage and digital correction implemented [1].

Alternatively, a low power pipeline stage ADC is introduced that avoids the use of op amp. The CBSC method is shown in Figure 2. The op amp at the core of the pipeline stage is replaced by a comparator and two current sources [5]. Capacitors C1a and C1b serve as charge transfer devices. When an input signal of Vin is applied, each stage samples and quantizes the signal to a resolution of 1.5b. This is usually 2 decision levels in three states 00,01,10, not counting state 11. This quantized signal is represented by the output of two additional comparators d1(0), and d0(0) in the first stage of the pipeline.

University of Michigan, EECS 511 Final Project: Comparator Based Switched Capacitor Implementation for Pipeline ADC

Fig. 2. Actual stage in a pipeline ADC. Two stages are shown here [5].

The unique characteristic of an ADC using op amp is exhibits exponential settling to virtual ground, in an ADC using comparators, it detects the virtual ground condition, and the subsequent output voltage is sampled on CL. There are two main phases of this switched capacitor scheme. 1 defines the sample phase of the stage, and 2 defined the charge transfer phase. 2 also has a very interesting breakdown: it is further divided into three sections: the preset phase (P), coarse charge transfer phase (E1), and fine charge transfer phase (E2) [5]. Figure 3. shows output characteristics of 2 phase.

shown in Figure 4. At the start of E1 phase, E1 will turn on current source I1, and both Vx and Vo will ramp up rapidly due to the large current thats charging the capacitors. At some point, Vx will cross over the VCM range, and the comparator detects this virtual ground condition, and makes a decision. Due to the finite delay of the comparator, E1 will go low after a while, and this causes overshoot at both nodes. E2 is then enabled, and I2, a much smaller current source, will slowly discharge the capacitors and bring down the nodes. When Vx drops across the VCM value, the comparator makes another decision, and turns off I2. The final output is then sampled during 1. The final overshoot is predictable, and thus, a overshoot correction scheme can be employed. This scheme is not implemented in this design, so it is only mentioned. Another Voc voltage source can be added in parallel to the VCM input to the comparator. This will actually allow the comparator to detect virtual ground condition when Vx is equal to Voc. Since Voc is lower than VCM, this will reduce the overshoot in E1 phase.

Fig. 4. Simplified representation of the ADC stage during the charge transfer phase [5].

III. PIPELINE ADC REALIZATION EMPLOYING CBSC TECHNIQUE A. Comparator Design The design of the comparator is made somewhat easier by the fact that stability is not an issue. The output common mode of each gain stage is constant. Common mode feedback technique is used for the first stage to guarantee a constant output common mode, but all subsequent stages did not require the use of feedback to achieve stability. A total of five gain stages are used. They are shown in Figure 5. The first stage has a gain of 15, and it is band limited so that noise is filtered out. The two diode connected NMOS is used to clamp the output swing to allow for faster recovery. The output is feed into a wide bandwith, low gain amplifier. The diode connected PMOS on top has a VDSAT of around 0.9V. This reduces the output common mode of the amplifier to 0.9V, it also reduces the output swing to allow for faster recovery. Since this PMOS device ensures the output common

Fig. 3. Voltage characteristic plot during 2, the charge transfer phase [5].

During the preset phase, a switch at the output node of the stage, which is between current sources I1 and I2, is turned on, and grounds the output node briefly. This will discharge C1 and CL. Vx will drop below VCM, and Vo will be at VCM,

University of Michigan, EECS 511 Final Project: Comparator Based Switched Capacitor Implementation for Pipeline ADC

done using a latch that will take d1(0) and d0(0) as inputs, and followed by a MUX. The third application is the conversion from comparator output to E1 and E2, clock pulses that will control the two current sources I1, and I2. E1 must turn on right after the falling edge of the preset clock. And E1 must be able to sense when the node Vx crosses over the VCM level, and be switched off. E2 is then turned on right after the falling edge of E1, and be turned off once Vx crosses back down across the VCM again. This is implemented as shown in Figure. 7.
Fig.5 Comparator schematic, a total of five gain stages are cascaded.

mode of 0.9V, no feedback is needed. The resistors are implemented as PMOS transistors in the triode region. The resistance is modeled with:

R=

p C ox W L (VGS VTH )
Fig.7 Digital Logic schematic. E1 E2 is generated by comparing the comparator output waveform, P waveform, and the charge transfer waveform.

The gain can be calibrated accordingly by changing either the transistor sizing, or the gate bias, or IB. The gain of each of the three stages is 2.5. The last stage provides a gain of 20. The overall gain of the comparator is 4687.5. The common mode of the output of the comparator is level shifted to about 0.8V, and the transition voltage of the inverter is calibrated to 0.8V as well. The Common Mode Feedback (CMFB) circuit is shown in Figure 6. When the output common mode drifts, the current across the input pair to the CMFB will change, and that will change the VCMFB value, which in turn, will adjust the current flowing down the amplifier, and modifying the output common mode back to the original level. Vref is set to VCM.

C. Design for 1.2V full swing output The overall pipeline ADC stage output will have a full scale swing of 1.2V in a 1.8VDD supply. To realize that, current sources I1 and I2 must consume only 0.3V each. This is done as shown in Figure 8. The three transistors that make up the current sources I1 and I2 is biased carefully to achieve a voltage drop of 0.3V each.

VB1 VB1 VB3 VB2

*V
VB3

OUT

VB2

Fig.8 Biasing for 1.2V ADC stage output full swing Fig..6 Common Mode Feedback circuit schematic.

B. Digital Logic Design To realize the pipeline ADC stage, digital circuits are also implemented for three applications. The first is the implementation of transmission gate as switches. The second is the conversion from d1(0) and d0(0) to D(0)Vref. This is

IV. PIPELINE ADC STAGE PERFORMANCE Figures 9 is a transient response plot of the comparator. The rise time between logical low and logical high (0.9V) is less than 1ns. This means the comparator is capable of running at more than 100 MHz.

University of Michigan, EECS 511 Final Project: Comparator Based Switched Capacitor Implementation for Pipeline ADC

2 P Cout E1 E2
Fig. 11 Input and output waveform of the digital logic circuit. E1 E2 is generated based on the response of the comparator and P. Fig. 9 Transient response of the comparator output. Transition from logical high to low occurs in less than 1 ns for the first output, less than 0.5 ns for the second output.

Figure 10 is a plot of a DC analysis of the comparator outputs, transition of the comparator outputs occur in less than 0.4 mV, which translates to a 14b accuracy, with a resolution of 20 uV.

E2 E1
ADC Stage Out

2 P
Fig. 12 Overall pipeline ADC stage output. E1 E2 had unexpected fluctuations, but the ramping behavior is still observed at the output.

V. CONCLUSION A 14 bit, 100 MHz comparator with a resolution of 20 uV is realized. This comparator consumes 0.3 mW. Estimated power consumption for the first stage of the pipeline ADC is 0.96 mW. As requirements relax for the subsequent stages, so will the power consumption. A 10b pipeline ADC implemented using the CBSC concept will consume less than 10 mW of power. Furthermore, The coarse and fine charge transfer phase is successfully observed. Output full swing is designed to 1.2V. Due to spikes and fluctuations in the E1 E2 output, ADC stage output is not ideal. Therefore, we could not obtain SNR and ENOB data through simulation. CBSC does show great promise to realize low power, low voltage applications such as a pipeline ADC.

Fig. 10 DC response of the comparator output. Transition of the output occurs in less than 0.4mV.

Figure 11 shows the output of the digital logic. As the preset phase comes to an end, E1 starts, and the digital logic will detect the rising edge of the output of the comparator, at which time, E1 will go low, and E2 will enable to turn on I2. Figure 12 shows the ADC stage output given the clock signals E1 and E2. E1 and E2 both have fluctuations that was introduced accidentally. As a result, the ADC stage output is not ideal. But when E1 is enabled, the stage does exhibit rapid ramping up, when E2 is enabled, output slowly ramps back down to the common mode voltage level. Even in the presence of the spikes on the two clock inputs, this ramping up and down behavior is observed. When The output is then held constant for the reminder of the 2 phase so that it can be sampled.

University of Michigan, EECS 511 Final Project: Comparator Based Switched Capacitor Implementation for Pipeline ADC APPENDIX The schematic and simulation files are stored on /afs/engine.umich.edu/class/w06/eecs511/group4/finalProj. All the components, including the comparator, digital logic, DFF, NAND, NOR, transmission gate schematic is saved, along with its symbol. Cellview finalCompile has the schematic of the pipeline ADC stage. REFERENCES
[1] Abo, Andrew M. and Paul R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599-606, May 1999 [2] [3] [4] [5]

B. Davari, R. Dennard, and G. Shahidi, CMOS scaling for high performance and low power the next ten years, Proc. IEEE, vol. 83, pp.595-606, April 1995. M. Das, Improved Design Criteria og gain-boosted CMOS OTA with high-speed optimizations, IEEE Transactions on Circuits and SystemsII: Analog and Digital Signal Processing, vol. 49, no. 3, March 2002. T. Cho and P. R. Gray, A 10b 20 Ms/s, 35 mW pipeline ADC converter, IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995. T. Sepke, J. K. Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee, Comparator Based Switched Capacitor Circuits For Scaled CMOS Technologies, ISSCC 2006