Chng 5 B nh my tnh

5.1 Tng quan b nh trong my tnh 5.2 B nh bn dn 5.3 B nh m nhanh (Cache) 5.4 B nh ngoi (b nh ph) 5.5 H thng nh trn my PC hin nay

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5.1 Tng quan

Cc c trng ca b nh V tr: Bn trong CPU: tp thanh ghi, cache B nh trong: B nh chnh v Cache B nh ngoi: cc thit b nh, RAID Dung lng: di t nh (tnh bng bit) S lng t nh n v truyn: T nh Khi nh
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5.1 Tng quan

Phng php truy nhp: Truy nhp tun t (bng t) Truy nhp trc tip (cc loi a) Truy nhp ngu nhin (b nh bn dn) Truy nhp lin kt (cache) Hiu nng: Thi gian truy nhp Chu k truy xut b nh Tc truyn
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5.1 Tng quan

Kiu b nh vt l: B nh bn dn B nh t B nh quang Cc c tnh vt l: Kh bin/khng kh bin Xo c/khng xo c

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Phn cp b nh
Tc

Registers CPU Cache Central Memory Disk Cache Disks CD/ROM Archival Stores
Kch thc Peripheral memories

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Phn cp b nh

Tp thanh ghi

register

B nh Cache L1

B nh Cache L2

B nh chnh

B nh trong

B nh mng

T tri qua phi: dung lng tng dn, tc gim dn, gi thnh tnh theo n v byte hoc bit gim dn.
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5.2 B nh bn dn
B nh ch c (ROM: Read Only Memory) B nh khng kh bin S dng lu cc thng tin sau: Th vin cc chng trnh con. Cc chng trnh con iu khin h thng (BIOS) Cc bng chc nng.
k ng a ch

2k t nh (n bit t nh)
n ng d liu ra
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5.2 B nh bn dn
Cc kiu ROM: ROM mt n, PROM: Programmable ROM, EPROM: Erasable PROM, EEPROM Electrically EPROM, Flash Memory (B nh cc nhanh): Ghi theo khi, xo bng in.

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5.2 B nh bn dn
B nh truy cp ngu nhin (RAM : Random Access Memory) B nh c ghi (R/W memory) B nh kh bin Lu thng tin tm thi C hai loi chnh l SRAM (Static RAM) v DRAM (Dynamic RAM) n ng d liu vo
k ng a ch Read Write
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2k t nh (n bit t nh)
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n ng d liu ra

5.2 B nh bn dn
RAM tnh (SRAM: Static RAM) Cc bit c lu da trn cc Flip- Flop (4-8 FF lu 1 bit) Thng tin lu n nh Cu trc phc tm Dung lng nh(KB) Tc nhanh (6-8 ns) Dng lm cache Gi thnh cao
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5.2 B nh bn dn
RAM ng (DRAM: Dynamic RAM) Cc bit c lu da trn cc t in => nguyn nhn thng xuyn lm ti. Dung lng ln. Tc chm (60-80ns). Dng lm b nh chnh Gi thnh phi chng. Cc DRAM tin tin: SDRAM: Synchronous Dynamic RAM, DDRAM: Double Data RAM. Ram BUS RDRAM.
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B nh chnh
Cc c trng c bn Tn ti trn mi h thng my tnh Cha chng trnh ang thc hin v cc d liu c lin quan. Gm cc ngn nh c nh a ch trc tip bi CPU. Dung lng b nh chnh bao gi nh hn khng gian m CPU c th qun l. Vic qun l logic b nh ph thuc vo h iu hnh.
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T chc ca chip nh
S c bn ca chip nh

A0..An-1

Chip nh 2nx m bit

cs
WE OE

D0..Dm-1

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T chc ca chip nh
Cc tn hiu ca chip nh Cc ng a ch: A0An-1 xc nh 2n ngn nh. Cc ng d liu: D0Dm-1 di t nh (m bit) =>dung lng chip nh = 2n x m bit Cc tn hiu iu khin o Tn hiu chn chip hot ng: CS (Chip Select) o Tn hiu iu khin c hoc ghi (WE: Write Enable; OE: Output Enable) o Thng cc tn hiu iu khin tch cc vi mc 0
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Thit k Mudule nh
Thit k module nh bn dn Cho chip nh 2n x m bit Yu cu s dng chip nh trn thit k module nh dung lng l bi kch thc chip nh trn. Gii quyt vn C hai cch: Thit k tng di t nh, s ngn nh khng thay i. Thit k tng s lng ngn nh, di t nh khng thay i.
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Thit k Mudule nh
Thit k tng s lng t nh Gi thit: Cho cc chip nh c dung lng 2n x m bit. Yu cu: Thit k module nh c kch thc: 2n x (k.m) bit Gii quyt: thit k c yu cu ta xc nh hai thng s n (s ng a ch)v k(s chip nh cn ghp vo module thit k

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Thit k Mudule nh
V d: Cho cc chip nh SDRAM dung lng 4K x 4 bit. Hy thit k module nh c kch thc 4K x 8 bit Dung lng chip nh 212 x 4 bit Thng tin cn cho chip nh s ng a ch n =12 v s ng d liu m=4 Thng tin v module nh s ng a ch l 12 ng (s ngn nh khng thay i), s ng d liu l 8 ng v s chip s dng thit k 2(k=2)

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Thit k Mudule nh
A0A11

Chip nh 212 x 4 bit

Chip nh 212x 4 bit D0D3 D 4D7

cs
WE OE

cs
WE OE

cs
WE OE

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Thit k Mudule nh
Thit k tng s lng ngn nh Gi thit: Cho cc chip nh c dung lng 2n x m bit. Yu cu: Thit k module nh c kch thc: 2k.2n x m bit Gii quyt: thit k c ta xc nh hai thng s n+k (s ng a ch) v 2k (s chip nh cn ghp vo module thit k)

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Thit k Mudule nh
V d : Cho cc chip nh SDRAM dung lng 4K x 8 bit. Hy thit k module nh c kch thc 8K x 8 bit. Dung lng chip nh gii thit 212 x 8 bit Thng tin cn cho chip nh s ng a ch n =12 v s ng d liu m=8 Thng tin v module nh s ng a ch l 13 ng (s ngn nh thay i) v s ng d liu l 8 ng( di t nh khng i).

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Thit k Mudule nh
A0A11

Chip nh 212x 8 bit

A12

cs y0
WE OE
D0D7

cs

B gii m 1->2

y1

Chip nh 212 x 8 bit

G
0 0 1 0 1 x

A
0
1

y1 1

y0

cs
WE OE

WE
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OE
21

Bi lm thm
Thit k module nh 16K x 8 bit t cc chip nh 4K x 8 bit Thit k module nh 32K x 8 bit t cc chip nh 4K x 8 bit Thit k module nh 8K x 8 bit t cc chip nh 4K x 4 bit Thit k module nh 32M x 32 bit t cc chip nh 4M x 32 bit

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Pht hin v chnh li trong b nh

Pht hin v chnh li trong b nh Nguyn tc chung: Trong qu trnh truyn d liu c th gp s thay i cc bit thng tin do nhiu hoc do sai hng ca thit b hay module vo ra. V vy, thc t t ra l phi lm sao pht hin c li v c th sa sai c. Mt trong phng php pht hin li (EDC: Error Dectecting Code) v sa li (ECC: Error Correcting Code) l: Gi s cn kim tra m bit th ngi ta ghp thm k bit kim tra c m ho theo cch no ri truyn t ghp m+k bit (k bit c truyn khng mang thng tin nn gi l bit d tha) Trong m l s bit cn ghi vo b nh v k bit l s bit cn to ra kim tra li trong m bit.
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Pht hin v chnh li trong b nh

Khi c d liu ra c kh nng sau: Khng pht hin d liu c li. Pht hin thy d liu li v c th hiu chnh d liu li thnh ng. Pht hin thy li nhng khng c kh nng ch ra li v th pht ra tn hiu bo li. S pht hin li v sa li

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Pht hin v chnh li trong b nh

m bit
B nh

m bit

Dliu ra
B hiu chnh v a d liu ra

B to m
M bit k bit

B to m

k bit

k bit
k bit

Tbo li B so snh

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Pht hin v chnh li trong b nh

V d 1: Pht hin li vi bit chn l(Party) M EDC n gin l bit chn l c gn thm vo cc bit d liu. Nu bit chn l =1: nu s bit 1 trong xu l l Hoc s dng Nu bit chn l =0: nu s bit 1 l chn u im: n gin v s bit d tha t. Nhc im: khng nh v c li, hoc nu c s thay i c hai bit hoc 1 hoc 0 th khng pht hin c. Khc phc nhc im trn xy dng m EDC khi.

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Pht hin v chnh li trong b nh

V d 2: Pht hin li bng m d tha CRC (Cycle Redundary Check). Nguyn tc: Mt xu nh phn bt k c th coi l tp hp cc h s ca a thc B(x) trong x l h s. Chn a thc G(x) l a no ta quy nh trc gi a thc sinh. Ta tin hnh chia module2 a thc B(x) cho G(x) ta c thng s Q(x) v phn d R(x). a thc sinh do t chc vin thng quc t quy nh. Khi ta cn truyn xu B(x) + R(x) bit kim tra li ta cn chia gi tr nhn c cho a thc sinh nu php chia c d th c li xut hin trong xu.
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Pht hin v chnh li trong b nh

V d:
Xu gc: 1101011011 M(x)=x9+x8+x6+x4+x3+x+1(m=9) a thc sinh G(x) = x4+x+1 10011 (r=4) Xu gc: 11010110110000 x4M(x) Chia mod2 11010110110000 10011 1100001010 -> thng

1110 phn d php chia Xu cn truyn i: 11010110111110 T(x)

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Pht hin v chnh li trong b nh

V d 3: M sa li Hamming Nguyn tc: Mt t m Hamming gm m bit d liu v k bit kim tra chn l. Mi bit c chn v tr thch hp pht hin chnh xc v tr c th sa li c. V d chn m=4 => k=3 (m=2n; k=n+1) Ta c th t sau: 7 6 5 4 3 2 1 I4 I3 I2 C3 I1 C2 C1 Cc bt ny c m ho theo quy lut sau: C1=I1 I2 I4 C2=I1 I3 I4 C3=I2 I3 I4 GV: inh ng Lng
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Pht hin v chnh li trong b nh

Gi s cc bit cn truyn l: I4 I3 I2 I1 = 1101 tnh cc C3C2C1=010 Bit cn truyn 1100110 Gi s ta c b li, th d bit I2 t gi tr 0 thnh gi tr 1 m nhn c 1110110. Bn thu tnh ra bit kim tra: C3=1 1 1=1 C2=1 1 1=1 C1=1 1 1=1 Nu module 2 s ny ta c 111 010 = 101 (C1,C3 thay i v v tr thay i l 101 (5))
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5.3 B nh m nhanh
Nguyn tc: Cache c tc truy xut nhanh hn rt nhiu b nh chnh Cache c t gia CPU v b nh chnh nhm tng tc trao i thng tin gia CPU v b nh chnh. Cache thng c t trong chip vi x l

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5.4 B nh m nhanh
Thao tc ca Cache CPU yu cu ly ni dung ca mt ngn nh bng vic a ra mt a ch xc nh nh. CPU kim tra xem c ni dung cn tm trong Cache Nu c: CPU nhn d liu t b nh Cache Nu khng c: B iu khin Cache c Block nh cha d liu CPU cn vo Cache. Tip chuyn d liu t Cache n CPU S thao tc cache, b nh chnh v CPU

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5.4 B nh m nhanh
Start

a ch RA t CPU

C BLOCK no trong cache cha RA

miss

Truy cp b nh ly ra BLOCK cha a ch RA

hit
Chuyn t ng RA ti CPU
Done
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a BLOCK vo mt Line trong Cache

Chuyn t a ch RA ti CPU
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5.4 B nh m nhanh
B nh Cache
Tag

B nh chnh Block 1
Block 2 Block 3

CPU

Line 1 Line 2 Line 3

Line C

Block 4 Block M-2 Block M-1 Block M

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5.3 B nh m nhanh
T chc Cache Gi s b nh chnh gm c 2n t nh c nh a ch ( mi t nh c a ch duy nht rng n bit) B nh chnh chia thnh M khi, mi khi c K t nh M=2n/K B nh Cache c C khe mi khe c K t nh.(C<<M) Ti mt thi im lun c mt tp con cc khi nh thng tr trong cache. Nu mt t s c c th khi cha t s c chuyn vo trong cache.
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5.3 B nh m nhanh
V d cho phng php nh x c th trong cache Cho dung lng Cache l 64KB (m=16) Mi khi knh thc 4 bytes => C=16K(214) lines mi line kch thc 4 bytes Cho dung lng b nh chnh 16MB (n=24) Mi khi knh thc 4 bytes => M=4M(222) khi mi khi kch thc 4 bytes

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5.3 B nh m nhanh
Phng php nh x trc tip (Direct mapping)
Mi block c nh x duy nht ti 1 line trong cache a ch pht ra t CPU c chia 2 phn w bits c trng s thp xc nh duy nht t cn truy xut(WORD) s bits cn li xc nh khi nh. Trong s bits chia 2 nhm r bits LINE v s-r bits TAG C th ha v d:
Tag s-r 8
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Line or Slot r 14
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Word w 2
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5.3 B nh m nhanh
Tng bit trong a ch b nh chnh n=24 bit: trong 2 bit phn word xc nh chnh xc 4 t 22 bit xc nh khi( 8 bit tag (=22-14) v 14 bit slot or line) Khng c hai block no trong Cache c cng Line v Tag. Kim tra ni dung t tn ti Cache chnh l kim tra a ch line v Tag

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5.3 B nh m nhanh

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5.3 B nh m nhanh
Cache line 0 1 Main Memory blocks 0, C, 2C, 3C2s-C 1,C+1, 2C+12s-C+1

C-1 C-1, 2C-1,3C-12s-1 Nhn xt: n gin Chi ph t Nhc im l s c nh cc khi trong cc line ca Cache. Trong trng hp chng trnh mun truy xut ti 2 Block tin tc m 2 block c phn nm trong cng line th kh nng Cache miss rt cao.
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5.3 B nh m nhanh

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5.3 B nh m nhanh
Phng php nh x lin kt (Associative mapping)
Mt Block ca b nh chnh c th nhp bt k line no trong Cache. a ch CPU pht ra c chia thnh 2 a ch tag v word a ch Tag xc nh khi duy nht ca b nh nm trong Cache. Mi gi tr Tag ca Line l khc nhau. Chi ph phng php ny i vi Cache l cao.
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5.3 B nh m nhanh

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5.3 B nh m nhanh
Tag 22 bit Word 2 bit

22 bit Tag lu tr Block 4 byte d liu. Vic kim tra Cache da vo cc gi tr Tag trong line (22 bit) nhn bit Cache hit hay miss. 2 bits cui xc nh chnh xc t cn truy xut V d a ch Tag D liu Cache line FFFFFC FFFFFC 24682468 3FFF

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5.3 B nh m nhanh

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5.3 B nh m nhanh
Phng php nh x lin kt tp hp (Set Associative mapping)
Cc line trong Cache c chia ra thnh tp(nhm) line Mi block ch c nh x vo bt k line no trong tp no m thi. V d Block b ch c th np vo bt k line no trong nhm cc line th i. V d 2 lines mt nhm (two way associative mapping), S Block b nh chnh l modulo 213 000000, 00A000, 00B000, 00C000 nh x cng nhm.
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5.3 B nh m nhanh

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5.3 B nh m nhanh
Tag 9 bit Set 13 bit Word 2 bit

S dng tp hp bit tp no c truy xut. So snh trng Tag xc inh Cache hit hay miss V d: a ch Tag D liu s tp 1FF 7FFC 1FF 12345678 1FFF 001 7FFC 001 11223344 1FFF

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5.3 B nh m nhanh

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5.4 B nh m nhanh
Mt s Block ca b nh chnh c np vo trong cc line ca Cache Ni dung th TAG (th nh) cho bit block no ca b nh chnh hin ang c cha trong line Khi CPU truy nhp c hay ghi mt t nh ca b nh chnh, c 2 kh nng xy ra : T nh c trong Cache (cache hit). T nh ang khng c trong cache (Cache miss). Phng php ghi d liu khi cache hit Ghi xuyn qua (Write Through): ni dung sau khi x l xong c cp nhp vo c Cache v b nh chnh. Tc chm.
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Cache trong cc b x l Intel

Ghi sau (Write back): D liu x l ch c ghi ra Cache, tc nhanh. Tuy nhin khi Block trong cache khng dng na th phi ghi tr c block ti b nh chnh. Dung lng Cache c s dng cho th h my: 80486: c 3KB nh Pentium : c 2 cache L1 trn chip l Cache lnh v cache d liu (8KB). Cache L2 lin hp Pentium 4: hai mc Cache L1 v L2 trn chip. Cache L1 mi cache 8KB. Cache L2: mi cache 256KB, 512KB, 1GB
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5.5 B nh ngoi
Cc kiu b nh ngoi a t a quang B nh Flash RAID

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a cng (HDD: Hard Disk Driver)

L thnh phn quan trng lu tr h iu hnh v cc phn mm tin ch my tnh. Mt my tnh c th mt a hoc nhiu a Dung lng mi a rt ln. Nm 1993 a ln nht 200MB n nay 80 hay 120GB Tc c ghi nhanh so cc b nh ngoi khc Gi thnh h c s dng lm b nh RAID (Redundant Array of (Inexpensive) Independent Disks).

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a quang (CD-ROM, DVD)

CD-ROM (Compact Disk ROM) CD-R (Recordable CD) CD-RW (Rewriteable CD) Dung lng ph bin 650MB CD ROM: c th c d liu t a CD CD RW : C th va c a CD v c th ghi d liu ln a CD-R, v CD-RW. Tc c c s 150KB/s Tc bi ln : 40x, 52x, 60x, DVD(Digital Video Disk): ch dng trn u c DVD (Digital Versatile Disk): dng trn a my tnh Dung lng thng dng 4.7GB
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Flash disk
Thng kt ni qua cng USB Khng phi dng a l b nh bn dn cc nhanh Dung lng pht trin nhanh Gn nh v tin li c im a Flash 1)Supports USB full-speed (12MBps) transmission 2) Driverless installation in Windows ME / 2000 / XP, Mac 9.0 and above, Linux 2.4 and above 3) Supports boot-up by USB-HDD or USB-ZIP mode 4) LED indicator displays status
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Flash disk
5) Write protection switch 6) Reading and writing speed: 900k/s and 700k/s 7) Password protection and data encryption prevents unauthorized access to data 8) Application software support in Windows OS security function 9) Application software resize (partition) available 10) Capacity: 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB 11) Compliance: FCC(B), CE, CTick GV: inh ng Lng Kin trc My tnh

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RAID
(Redundant Array of Independent Disk)
Khi nim RAID l s chun ha d liu a a. Mc ch Nng cao hiu sut vn hnh ca ton b h thng. Qun l song song cho yu cu nhp xut. Tn dng tnh d tha d liu nhm ci thin tin cy a.

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RAID (Redundant Array of Independent Disk)

c im chng ca RAID RAID l tp hp cc a vt l c nhn t h iu hnh nh a logic n. D liu c phn b trn mng cc a vt l. Dung lng a d tha c s dng lu tr thng tin chn l nhm m bo kh nng phc hi d liu trong trng hp c h hng v a.

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RAID
(Redundant Array of Independent Disk)

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RAID
(Redundant Array of Independent Disk)

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RAID
(Redundant Array of Independent Disk)

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5.6 H thng nh trn my PC hin nay

H thng Cache: tch hp trc tip trn cc chip vi x l B nh chnh: tn ti di dng module nh RAM SIMM: Single Inline Memory Module 30 pin : 8 ng d liu 72 pin : 32 ng d liu DIMM: Dual Inline Memory Module 168 pin: 64 ng d liu RIMM: Rambus Inline Memory Module
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ROM BIOS
ROM BIOS: Basic Input Output System ROM cha chng trnh sau: Chng trnh POST (Power On Self Test) Chng trnh CMOS setup (Compementary Metal Oxide Semiconductor) Chng trnh Bootstrap Looader Chng trnh iu khin vo ra c bn (BIOS) CMOS RAM Cha cu hnh h thng hin thi ng h v ngy thng nm h thng
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