SREENIDHI INSTITUTE OF SCIENCE & TECHNOLOGY

(approved by AICTE & Govt. of A.P. and Affiliated to JNTU) Yamnampet, Ghatkesar Mandal, Hyderabad 501 301. Y

COURSE FILE For COMPUTER ORGANIZATION

(ECM Branch)

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COMPUTER ORGANIZATION Introduction and Course Objectives: Computer Organization and Computer Architecture are the terms used in describing digital computer systems. It is difficult to precisely define the two terms and draw a separating line between the two areas of coverage. Even so, there exists a general consensus that the programmers are concerned about the architecture which deals with the instruction sets, address fields, operation codes, addressing modes, effective utilization of I/O mechanisms and such other aspects which would interest the users of computers. Organizational aspects include hardware details such as generation of control signals, interface between the computer and peripherals, memory technologies used, modular design, flow of data, control mechanisms and so on. In brief, a programmer is generally more concerned about the architectural features and a designer of computer systems is more concerned about the organizational aspects. Both the architectural and organizational aspects must be made conceptually transparent to the programmer as well as computer designers. Course Objectives: Global Objectives: After going through the course, the student will be able to get a clear understanding and feel for various sub-systems of a computer. A serious student will be in a position to work out a detailed design and fabricate the modules and integrate them into a computer system.

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Syllabus: UNIT-I BASIC STRUCTURE OF COMPUTERS: Computer Types, Functional unit, Basic operational concepts, Bus structures, Software, Performance, multiprocessors and multi computers. Data Representation. Fixed Point Representation. Floating Point Representation. Error Detection codes. Addition, subtraction, and multiplication Algorithms. UNIT-II REGISTER TRANSFER LANGUAGE AND MICROOPERATIONS: Register Transfer language, Register Transfer Bus and memory transfers, Arithmetic Mircrooperations, logic micro operations, shift micro operations, Arithmetic logic shift unit. Instruction codes. Computer Registers, Computer instructions Instruction cycle. UNIT-III Memory Reference Instructions, Input Output and Interrupt, STACK organization, Instruction formats, Addressing modes, DATA Transfer and manipulation, Program control, Reduced Instruction set computer. UNIT-IV MICRO PROGRAMMED CONTROL: Control memory, Address sequencing, micro program example, design of control unit, Hard-wired control. Microprogrammed control UNIT-V THE MEMORY SYSTEM: Basic concepts, semiconductor RAM memories, Read-only memories, Cache memories, performance considerations, Virtual memories, secondary storage. Introduction to RAID. UNIT-VI INPUT-OUTPUT ORGANIZATION: Peripheral Devices, Input-Output Interface, Asynchronous data transfer Modes of Transfer, Priority Interrupt, Direct memory Access, Input Output Processor (IOP), Serial communication; Introduction to peripheral component, Interconnect (PCI) bus. Introduction to standard serial communication protocols like RS232, USB, IEEE1394. UNIT-VII PIPELINE AND VECTOR PROCESSING: Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline, RISC Pipeline, Vector Processing, Array Processors. UNIT-VIII MULTI PROCESSORS: Characteristics of Multiprocessors, Interconnection Structures, Interprocessor Arbitration, InterProcessor Communication and Synchronization, Cache Coherence, Shared Memory Multiprocessors. TEXT BOOKS:

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2.

1. Computer Systems Architecture M.Moris Mano, IIIrd Edition, Pearson/PHI Computer Organization Carl Hamacher, Zvonks Vranesic, SafeaZaky, th 5 Edition, McGraw Hill. REFERENCE:

1. 2. 3. 4.

Computer Organization and Architecture William Stallings Sixth Edition, Pearson/PHI Structured Computer Organization Andrew S. Tanenbaum, 4th Edition PHI/Pearson Fundamentals or Computer Organization and Design, - Sivaraama Dandamudi Springer Int. Edition. Computer Organization, Anjaneyulu, Himalaya Pub house.

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LECTURE SCHEDULE UNIT I Topic Basic structure of computers Computer types, functional unit, Basic Operational concepts Bus structures, Software, performance Multi processors and multi computers, data representation Fixed point representation, floating point representation, error detecting codes Addition, subtraction and multiplication algorithms UNIT II Topic Register transfer language and micro operations Register transfer language, register transfer bus and memory transfer Arithmetic micro operations, logic micro operations Shift micro operations, arithmetic logic shift unit Instruction codes, computer registers Computer instructions, Instruction cycle. UNIT III Topic Memory reference instructions Input and output interrupt, stack organization Instruction format, addressing modes Data transfer and manipulation Program control Reduced instruction set computer UNIT IV Topic Micro programmed control. Control memory Address sequencing Micro program example Design of control unit hard wired control Micro programmed control Lectures 10 2 2 2 2 2 Lectures 10 2 2 2 2 2 Lectures 10 2 2 2 2 2 Lectures 10 1 2 1 2 4

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UNIT V Topic Memory systems Basic concepts of semi conductor RAM memories ROMs, Cache memories, performance considerations Virtual memories, RAID UNIT VI Topic Input output organization Peripheral devices, I/O interface, asynchronous data transfer, modes of transfer Priority interrupt, DMA, I/O processor Serial communication, peripheral component, interconnect (PCI) bus Standard serial communication protocols RS232, USB, IEEE1394 UNIT VII Topic Pipeline and vector processing Parallel processing, pipelining, arithmetic pipeline Instruction pipeline, RISC pipeline Vector processing ,Array processors UNIT VIII Topic Multi processors Characteristics of multi processors, Interconnection structures Inter process arbitration, inter-process communication and cache coherence Shared memories, multi processors Total lectures Lectures 6 2 2 2 68 Lectures 6 2 2 2 Lectures 10 2 2 3 3 Lectures 6 2 2 2

SHORT ANSWER QUESTIONS 116

UNIT I BASIC STRUCTURE OF COMPUTERS: 1) Decimal equivalent of binary number 101110 is _____________.

2) Binary and Octal equivalent of hexadecimal number F3A6 are _____________ and _____________ respectively. 3) 4) 5) 6) What is timing diagram? MAR and MBR stands for what? Parity bit is a _________________ code. ASCII is the standard example of ______________ code.

7) The part of the computer system, which controls the operation of computer and performs data processing functions is a ______________. 8) 9) 10) Mention various Internal modules of a computer at a top-level structure? What is the need of system interconnection? Basic functions of the computer include _________________.

11) When the interrupt occurs, processor sets the program counter to starting address of ___________________. 12) 13) 14) 15) timing. 16) timing. Process of data transfer from I/O device and memory is called __________. BCD equivalent of decimal number 8534 is ______________. Purpose of interrupt ACK is to acknowledge ______________ interrupts. Events on the bus that are determined by clock is called ____________ Occurrence of current event on previous event is called _______________

17) Represent the decimal number 453.4 using floating-point representation, which have 16-bit mantissa and 8-bit exponent.

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18. In a BCD adder, carry can be represented by a Boolean function C = __________ with corresponding inputs K, Z8, Z4, Z2, Z1. 19. Other arithmetic operation (sub operation) involved in multiplication is __________. 20. All serial decimal addition employs (a) BCD adder (b) Full adder 21. Parallel decimal adder employs (a) BCD adder (b) Full adder

(c) Both (c) Both

(d) None (d) None

22. X output in BCD subtraction produces _________ complement of B. 23. __________ Micro operation is used to shift decimal digit to right.

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UNITS II & III : REGISTER TRANSFER LANGUAGE & MICRO OPERATIONS: 1) Give an example of RISC instruction that will perform Divide a signed number by 4. 2) NOP specifies _________________________________. 3) Represent -86 in binary using eight bits. 4) A computer has 32-bit instructions and 12-bit addresses. If there are 250 twoaddress instructions, how many one-address instructions can be formulated? 5) What must the address field of an indexed addressing mode instruction be to make it same as a register indirect mode instruction? 6) What are the two instructions needed in basic computer in order to set E flip-flop to 1? 7) Specify sequence of micro operations that will perform following operations: i) IR M (PC) ii) AC AC + TR iii) DR DR + AC 8) Make a change to basic computer by adding a register to a bus system CTR to be selected with S2S1S0 = 000. 9) How many references to memory are needed for each type of instruction to bring an operand into a processor register? 10) __________ Instruction is used to clear contents of accumulator. 11) STA and BSA are instructions categorized under __________ reference. 12) CLA and SZA are instructions categorized under __________ reference. 13) __________ Instruction is used from memory reference during subroutine calls. 14) Expand BUN _____________. 15) P: R1 R1 R2 specified __________ operation.

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UNIT IV: MICRO PROGRAMMED CONTROL 1) List out various blocks of micro programmed control organization. 2) Control data register some times also called as __________ register. 3) Each group of microinstructions specifies __________. 4) Transformation from instruction code bits to address in control memory is called __________ process. 5) List out microinstructions needed for fetch routine. 6) Assembler is used to translate symbolic micro program to _____ micro program. 7) _____ Field specifies a value for address field. 8) _____ Field has one of the letters U, I, S, Z. 9) CALL and RET are the symbols used in _____ field. 10) Purpose of micro program sequencer is for __________ selection. 11) Converse symbolic micro operation READ to register transfer statement. 12) Repeat above question for symbolic micro operation ACTOR.

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UNIT V:

The memory system

1) In sequential memory data is arranged as (a) Files (b) Fields (c) Records 2) The system in which address is unique is (a) Sequential (b) Direct (c) Random 3) The fastest memory is (a) Semiconductor (b) Magnetic 4) The fastest RAMs are (a) SRAM (c) DRAM (c) Cache (c) ROM (d) Depends (d) All (d) All (d) EPROM (d) EEPROM

5) Tag array and data array are present in (a) ROM (b) RAM (c) Cache 6) EDRAM indicates (a) Enhanced DRAM 7) Elaborate RAID. 8) Volatile storage is a device in which data are lost (a) With time (b) When power is removed (c) When programme is over (d) None 9) Scratch pad memory is a (a) FIFO memory (c) Local Temporary memory (b) Local permanent memory (d) LIFO memory

(b) Electrical DRAM (c) Electronic DRAM (d) None

10) Which of the following memories has the shortest access time? (a) Cache memory (b) magnetic bubble memory (c) Magnetic core memory(d) RAM 11) Serial access memories are useful in applications where (a) Data consists of numbers (b) Short access time is required (c) Each stored word is processed (d) Data naturally needs to flow in and out in serial form. 12) The principle advantage of dynamic shift registers over static shift register is that (a) They provide more bits in smaller area (b) They loose their data if shifted too slowly (c) They can be shifted faster (d) Less expensive 121

13) The fastest type of memory from the following list is (a) Tape (b) Semiconductor memory (c) Disk

(d) Bubble memory

14) Which of the following memories allows simultaneous read and write operations? (a) ROM (b) RAM (c) EPROM (d) none of the above. 15) The process of entering data into a storage location (a) Causes variation in its address number (b) Adds to the contents of the location (c) Is known as a readout operation (d) Is destructive of previous contents 16) The desirable characteristic(s) of a memory system is (are) Kb,C $#|.V?b50=ibhvcV? Xc/(a) Speed and reliability consumption (c) Durability and compactness (d) All of the above (b) Low power

17) The time elapsed between the initiation of a memory operation and the completion of that operation is known as (a) Memory cycle time (b) Memory access time (c) Transfer time (d) Skip time 18) The minimum time delay required between the initiations of two successive Memory operations is known as (a) Memory cycle time (b) Memory access time (c) Transmission time (d) Waiting time 19) For a memory system, the cycle time is (a) Same as the access time (b) Longer than the access time (c) Shorter than the access time (d) Submultiple of the access time 20) Non-volatility is an important advantage of (a) CCDs (b) Magnetic tapes and disks (c) Magnetic bubbles (d) both b & c 21) The memory, which is programmed at the time it is manufactured (a) ROM (b) RAM (c) PROM 22) Which memory is volatile? (a) RAM (b) ROM (c) EPROM (d) EPROM (d) PROM

23) Which of the following memory medium is not used as main memory System? (a) Magnetic core (b) Semiconductor (c) Magnetic tape (d) Both semiconductor and magnetic tape

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24) Which memory system is not as a mass memory medium? (a) Semiconductor memory (b) Magnetic tape (c) Magnetic disk (d) Magnetic drum 25) Which of the following statements is wrong? (a) Magnetic core memory, RAMs and ROMs have constant access time. (b) MOS transistor technology can be used in RAMs, ROMs and shift register memories. (c) Magnetic tape is a type of medium used in mass memory (d) In volatile memory, the binary information is destroyed after a Read operation. 26) Which of the following statements is wrong? (a) RAM is a type of volatile memory (b) Magnetic tape is non-volatile (c) Magnetic core and semiconductor memories are used as mass memory medium. (d) An EPROM can be programmed, erased and reprogrammed by the User with an EPROM programming instrument. 27) The memory which is ultraviolet light erasable and electrically programmable is (a) ROM (b) PROM (c) RAM (d) EPROM 28) Which memory is nonvolatile and may be written only once? (a) RAM (b) EE-ROM (c) EPROM 29) The 7489 IC is a (a) 64-bit RAM (b) 64-bit ROM (c) 32-bit RAM (d) PROM (d) 32-bit ROM

30) Which of the following memories must be refreshed many times per Second? (a) Static RAM (b) Dynamic RAM (c) EPROM (d) ROM 31) 38. The refreshing rate of dynamic RAMs is approximately once in (a) Two microseconds (b) Two milli seconds (c) Fifty milli seconds (d) Two seconds 32) The minimum number of MOS transistors required to make a dynamic RAM cell is (a) 1 (b) 2 (c) 3 (d) 4 33) In comparison with static RAM memory, the dynamic RAM memory has (a) Lower bit density and higher power consumption (b) Higher bit density and higher power consumption (c) Lower bit density and lower power consumption (d) Higher bit density and lower power consumption

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34) The disadvantage of dynamic RAM over static RAM is (a) Higher power consumption (b) Variable speed (c) Need to refresh the capacitor charge every once in two milliseconds (d) Higher bit density 35) Which of the following memories contains a thin film of magnetic material sandwiched between two permanent bias magnets? (a) ROM (b) Magnetic disk (c) Core memory (d) Bubble memory 36) EE-ROM is (a) Electrically erasable 37) EPROM consists of (a) Bipolar transistors (b) Easily erasable (c) Non-erasable (d) Effective erasable (b) MOSFETs (c) UJTS (d) Diodes

True (or) False

38) RAM is volatile memory 39) Bubble memory is volatile. 40) Compared with the primary storage, the secondary storage is slow and inexpensive. 41) ROMs are available in both bipolar and MOS families. 42) The typical speed (access time) ratio between bipolar and MOS ROMs is ten. 43) CD-ROM is a non-erasable disk used for storing computer data. 44) On a movable head system, the time it takes to position the head at the track is known as latency time.

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UNIV VI:

Input output organization

1) DMA controller is (a) Allowed to data transfer direct (b) allows memory direct (c) Both (d) None 2) The functions of I/O modules are (a) Control and timing (b) CPU communication (c) Device communication (d) All 3) The external devices are (a) Human readable (b) Machine readable (c) Communication 4) The basic unit of exchange is (a) Bit (b) Character (c) Word (d) All

(d) Sentence

5) CPU always communicates with (a) One device at a time (b) Many devices (c) Depends upon requirement (d) All 6) The most important function of I/O module is (a) Data transfer (b) Data storage (c) Data buffering (d) None

7) _________________ Is a method to implement interrupt priority. 8) The CPU ignores an interrupt from a device, if the corresponding ___________ bit is set to 0. 9) In a Daisy chain implementation of interrupt priority, the interrupt requests of all the devices are _______________, before connecting to the interrupt signal of CPU. 10) In DMA mode transfer of one data word at a time, is called ______________. 11) Punched cards use (a) Alpha numeric code (b) Hollerith code (c) EBCDIC code (d) ASCII code

12) When used with I/O devices, the term intelligent implies (a) A color output capability (b) Speech processing capability (c) High speed printing capability (d) Features to support offline and on line tasks. 13) What is the storage capacity of Hollerith card, which is organized into nibbles? (a) 32 (b) 64 (c) 120 (d) 240

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14) What technology is used for flat panel displays? (a) Solid state (b) RBG monitor (c) VLSI

(d) Direct view storage

15) The digitizing technology that uses an electric field radiated from the tablet and picked by cursor is (a) Raster (b) Electrostatic (c) Sonic (d) Electromagnetic 16) In which of the following terminals, the CPU copies the characters to be displayed to the video RAM in alternative bytes and screen is regarded as a 25 x 80 array of characters? (a) Character map terminal (b) Bit-map terminal (c) RS-232 C terminal (d) none 17) In which of the following terminals, the screen is regarded as an array of pixels, where each pixel is either on or off (a) Character map terminal (b) Bit-map terminal (c) RS-232 C terminal (d) none 18) Which video terminal is generally used in engineering workstations? (a) Character map terminal (b) Bit-map terminal (c) RS-232 C terminal (d) none 19) Bit map terminal (a) Support displays containing multiple windows (b) Requires considerable amount of video RA M (c) Requires tremendous amount of copying and hence low performance (d) All of the above. 20) Memory mapped displays (a) Are utilized for high resolution graphics such as maps (b) Uses ordinary memory to store the display data in character form (c) Stores the displays data as individual bits (d) Are associated with electromechanical teleprinters

True (or) False Questions

21) In DMA, the I/O module (controller) and main memory exchange data directly without CPU involvement. 22) In asynchronous transmission, the time interval between two characters is fixed. 23) Programmed I/O does not use interrupts. 24) With memory mapped I/O does not use interrupts.

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25) In synchronous transmission, blocks of characters or bits are transmitted without start or stop codes, and the exact departure and arrival time of each bit is predictable. 26) Give reason why Interrupt-driven transfer data is preferred over program driven transfer of data 27) The technique of resolving Bus connection is called ---------------

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UNIT VII:

Pipeline and vector processing

1) Decomposing a sequence process in sub-operations is known as _____ processing (a) Parallel (b) Pipeline (c) Bus (d) Multibus 2) If in a non-pipeline process a task takes tn time to complete each task and for n tasks it takes ntn. Then the speed up ratio for pipelining process for some n-tasks is S = ntn / (k + n 1) tp 3) The instruction pipeline is an _________buffer. 4) List out the sequence of steps included in processing the instruction. 5) List out the pipeline conflicts. 6) The associative memory included in the fetch segment of the pipeline is ___________. 7) List out the application areas where vector processing is major requirement. 8) Give the instruction format for vector processor. 9) Auxiliary processor attached to a general-purpose computer is ________________. 10) The processor that manipulates vector instructions by means of multiple functional units responding to a common instruction is____________. 11) The best-known SIMD array processor is _______________. 12) The advantage of modular memory is ______________________.

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UNIT VIII:

Multiprocessors
1) Multi processors are classified depending on how memory is organized. 2) List out the various forms of establishing interconnection network. 3) The IEEE 796 multibus system has _____ data lines (a) 16 (b) 20 (c) 24 (d) None

4) The algorithm which allocates a fixed-length time slice of bus time in round robbin fashion is (a) Time sharing (b) Time slicing (c) Both (d) None 5) The algorithm that gives the highest priority to the requesting device that has not used the bus for the longest interval is (a) Polling (b) LRU (c) Rotating daisy chain (d) None 6) List out the various dynamic arbitration algorithms 7) The compiler checks for _____________ in the program. 8) The multi processor system where each processor is allocated with its own. Private local memory is _____________________________.

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ESSAY QUESTIONS ( Compiled from JNTU old papers) UNIT I 1. Explain rs complement and the (r 1)s complement for base r system. 2. Explain about sign magnitude and 2s complement approaches for representing the fixed point numbers. Why 2s complement is preferable. 3. Give means to identify whether or not an overflow has occurred in 2s complement addition or subtraction operations. Take one example for each possible situation and explain. Assume 4 bit registers. 4. Explain with block diagram, the basic functional units of a computer. 5. Explain the basic aspects of system software. 6. Write short notes on a) Processor clock b) Basic performance equation c) Clock rate d) Gray code and BCD e) Error detection codes 7. Explain the terms compiler, linker, assembler, loader and describe how a C program or any other high level language program is executed in a system. Indicate entire process with a figure. 8. a) Draw a flow chart which explains multiplication of two signed magnitude fixed point numbers. b) Multiply 10111 with 10011 with the above procedure given (a). Show all the registers contents for each step. 9. Using flowchart, explain the hard ware algorithm for signed- magnitude addition and subtraction. 10. Using flowchart, explain Booth algorithm for multiplication of signed 2s complement numbers. 11 Using flowchart, explain multiplication algorithm for floating point numbers. 12. Using block diagram, explain BCD adder. 13. Using flowchart, explain multiplication algorithm for decimal numbers.

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UNIT II 1. Using block diagrams, explain the transfer of information from one register to another register. 2. Explain the bus transfer, using a bus system for four registers. Or Design register selection circuit to select one of the four 4-bit registers content on to bus. Give fuller explanation 3. Explain full adder circuit functionality with inputs and outputs using a block diagram. 4. Using FA blocks, design combined adder cum subtractor circuit. Assume two numbers are 4-bit numbers. 5. Using HA blocks, design 4-bit binary incrementer. 6. Explain with block diagram 4-bit arithmetic circuit. 7. Write short notes on logic micro operations. Design the logic diagram and the function table for one stage logic circuit. 8. What are the shift micro-operations?. Explain the 4-bit combinational circuit shifter with diagram and function table. 9. Explain one stage of an arithmetic logic shift unit with diagram and function table. 10. Explain with block diagram the control unit of basic computer. 11. What is instruction cycle.Draw flow chart for instruction cycle.

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UNIT III 1. What are the memory reference instructions.Draw flow chart for memory reference instructions. 2. What is program interrupt? Explain with example. Draw flow chart for interrupt cycle. 3. Explain about stack organization used in processors. What do you understand by register stack and memory stack? 4. Explain how X= (A+B) / (A B ) is evaluated in a stack based computer. 5. What is reverse Polish notation?. Explain the conversion from infix notation to reverse Polish notation,with a suitable example. 6. Explain the following CPU organizations. a) Single accumulator organization b) General register organization c) Stack organization. 7. Explain the following instruction formats a) Three-Address instructions b) Two-Address instructions c) One-Address instructions d) Zero-Address instructions e) RISC-Address instructions 8. Write short notes on various addressing modes. 9. Write short notes on RISC characteristics.

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UNIT IV . 1) What are the major design considerations in microinstruction sequencing? 2. Explain about microinstruction sequencing techniques, specially variable formal address microinstruction. 3. Explain the difference between hardwired control and micro-programmed control. 4. Define the following: a) micro-operation b) micro-instruction c) micro-program 5. Give the typical horizontal and vertical microinstruction formats. 6. Describe how microinstructions are arranged in control memory and how they are interpreted. 7) Explain the mapping of instruction code to micro-instruction address. 8) Write short notes on a) micro-instruction formats b) symbolic micro-instructions c) symbolic micro-program 9) Explain the decoding of micro-instruction fields in the design of control unit. 10) Draw the general block diagram of a micro-sequencer. Explain clearly the inputs and outputs of the same along with their functioning.

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UNIT V:

The memory system

1) Explain different levels of RAID. What are the advantages? 2) Compare and contrast Asynchronous DRAM and Synchronous DRAM 3) What is a virtual memory technique? Explain different virtual memory techniques. 4) Explain how the technique of paging can be implemented? 5) Explain any two mapping procedures in the organization of cache memory. 6) Write short notes on associative memory. Explain the match logic. 7) What is page fault?. Explain how a page fault is handled in virtual memory organization. 8)write short notes on CD technology. 9) write short notes on DVD technology.

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UNIT VI:

Input output organization.

1) Write short notes on Programmed I/O and Interrupt initiated I/O 2) Write short notes on UART. Explain with block diagram 3) What is DMA? Explain the working of DMA with block diagram. 4) What is polling? Explain in detail 5) Write short notes on Hand shaking 6) Write short notes on Daisy chaining with neat sketch.) 7) Write short notes on the following with neat sketches a) Parallel priority interrupt b) Priority encoder c) Interrupt cycle and interrupt service routine 8) Explain with block diagrams a) DMA controller (8 marks) b) IOP (8 marks) 9) write short notes on a) Character oriented protocol (8 marks) b) Data transparency (8 marks) c) Bit-Oriented protocol. (8 marks) 10) what are different issues behind serial communication ?. (10 marks) 11) Explain the following a) CPU-IOP communication. (8 marks) b) IBM 370 I/O channel. (8 marks)

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UNIT VII:

Pipe line & vector processing. 1) What is pipelining?. Explain with an example. (8 marks) 2) Write short notes on Arithmetic pipeline (8 marks) 3)Write short notes on Instruction pipeline ( 8 marks) 4) Write short notes on Vector processing (8 marks) 5) Write short notes on RISC pipeline (8 marks) 7)Write short notes on Memory interleaving (8 marks) 8) Write short notes on Attached array processor (8 marks) 9) Write short notes on SIMD array processor (8 marks) 10) Explain the following with respect to instruction pipeline a) Pipeline conflicts (4 marks) b) Data dependency (4 marks) c) Hardware interlocks (4 marks) d) Operator forwarding (4 marks) e) Delayed load (4 marks) f) pre-fetch target instruction(4 marks) g) Branch target buffer(4 marks) h) Delayed branch (4 marks)

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UNIT VIII: 1. What are the characteristics of multi-processing. (8 marks) 2. Write short notes on the following interconnection structures for multiprocessing systems. a) Time-Shared common bus ( 8 marks) b) Multi port memory. (8 marks) c) Cross bar Switch. (8 marks) d) Multi stage switching network.(8 marks) e) Hyper cube systems. (8 marks) 3) Write short notes on the following inter processor arbitration procedures. a) Serial arbitration procedure. (8 marks) b) Parallel arbitration procedures.(8 marks) c) Dynamic arbitration algorithms.(8 marks) 4) Explain how mutual exclusion is provided with a semaphore in a multi processor system.(8 marks). 5) What is cache coherence?. What are the conditions for incoherence? Explain the solutions to cache coherence problem. (16 marks) 6) write short notes on a) Inter-processor communication. (8 marks) b) Inter-processor synchronization.(8 marks)

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