Slide-ch4-Thiet Ke He Thong So Dung VHDL

Bi ging mn K thut s 2
Chng 5
THIT K S DNG VHDL
Ging vin: Nguyn Hu Chn Thnh
NI DUNG 1. 2. 3. 4. 5. 6. 7. GII THIU V HDLs (Hardware Description Languages) CC CU TRC C BN CA VHDL CC PHT BIU NG THI CC PHT BIU TUN T THIT K MCH TUN T THIT K MY TRNG THI THIT K PHN CP
1. GII THIU Cc phng php thit k: Cc phng trnh Boolean Thit k da trn Schematic Cc ngn ng m t phn cng HDLs (Hardware Description Languages): VHDL, Verilog HDL, ABEL,
1. GII THIU (tt) Qu trnh thit k h thng s:
1. GII THIU (tt) Cc cng c CAD: Nhp yu cu thit k (design entry)

Dng bng chn tr Trc tip V dng sng quan h vo/ra (Waveform Editor)
Dng s mch (Graphic Editor) thit k phn cp
1. GII THIU (tt) Cc cng c CAD: Nhp yu cu thit k (design entry)

Dng HDLs
1. GII THIU (tt) Cc cng c CAD: Tng hp (synthesis):

Tng hp logic (logic synthesis/logic optimization) nh x cng ngh (technology mapping) Tng hp s mch (layout synthesis/physical design)
M phng (simulation)
M phng chc nng (functional simulation) M phng nh thi (timing simulation)
1. GII THIU (tt) VHDL (Very High Speed Integrated Circuits HDL): Ngn ng c dng m t cc h thng s: lp ti liu (documentation), m phng (simulation), kim chng (verification) v tng hp (synthesis). VHDL c chun ha vo nm 1987 qua chun IEEE 1076 (VHDL-87) v c cp nht nm 1993 (VHDL-93). Sau c b sung qua chun IEEE 1164 vi h thng logic a tr. ng dng: thit k vi cc PLD, CPLD v FPGA. S khc bit gia VHDL v cc ngn ng lp trnh thng thng Ngn ng lp trnh thng thng: tun t VHDL: song song
2. CC CU TRC C BN CA VHDL 2.1. Entity

Entity Packages Entity Declaration Interface declaration Architecture body Functional definition Internal machinery Black box
2.1. Entity (tt) Khai bo entity Entity nh ngha giao tip ca module phn cng vi mi trng bn ngoi s dng n. C php khai bo: entity entity_name is generics ports begin entity statements end [entity] entity_name;
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2.1. Entity (tt) Cc port trong khai bo entity: Mi tn hiu I/O trong mt khai bo entity c xem l mt port. Mi port c khai bo phi c tn, chiu d liu (mode) v kiu d liu.
port (port_name: mode data_type; port_name: mode data_type; port_name: mode data_type);
Cc mode:
In: lung d liu ch i vo entity. Out: lung d liu ch i ra khi entity. Buffer: tng t out, nhng cho php hi tip ni Inout: lung d liu c th vo hay ra entity v cng cho php hi tip ni.
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2.1. Entity (tt) Kiu d liu:

IEEE 1076/93: boolean, bit, bit_vector, integer, IEEE std_logic_1164: std_ulogic, std_ulogic_vector, std_logic v std_logic_vector (h thng logic a tr). Cc kiu d liu do ngi s dng inh ngha. Khai bo ca cc kiu d liu phi cho php entity thy c qua cc mnh library v use.
V d 2.1: khai bo cng AND entity andgate is port (A, B: in bit; C : out bit); end andgate;
ANDGATE
A B
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2.1. Entity (tt) V d 2.2: khai bo b so snh 4-bit entity eqcomp4 is port (A, B : in bit_vector(3 downto 0); equals : out bit); [3:0] A[3:0] end eqcomp4; Equals V d 2.3: B[3:0] library ieee; use ieee.std_logic_1164.all; 4-bit comparator entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4;
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2.2. Thn kin trc (Architecture body) Khai bo entity l mt hp en vi m t cc giao tip I/O cn thn kin trc cung cp m t chc nng ca hp en . Mt entity c th c nhiu thn kin trc. Mi thn kin trc ch kt hp vi mt khai bo entity. Cc kin trc ca VHDL c chia lm 2 loi: M t hnh vi (behavior description)
M t dng gii thut (algorithmic description) M t lung d liu (data flow description)
M t cu trc (structural description) Mt thit k c th dng mt trong cc loi trn hay cng c th kt hp cc loi vi nhau.
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1. GII THIU (tt) Biu din h thng: Dng hnh vi: m t chc nng ca h thng tp trung vo quan h gia cc tn hiu vo v ra. Dng cu trc: m t ci t bn trong ca h thng c t r rng cc thnh phn no c dng v kt ni gia chng.
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2.2. Thn kin trc (Architecture body) (tt) Khai bo thn kin trc: architecture architecture_name of entity_name is declarations begin concurrent_statements end [architecture] architecture_name; M t hnh vi: m t chc nng ca h thng tp trung vo quan h gia cc tn hiu vo v ra. M t dng gii thut: cn c gi l m t cp cao (highlevel) v n tng t vi m t trong cc ngn ng cp cao nh C, Basic
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2.2. Thn kin trc (Architecture body) (tt) V d 2.4: M t dng gii thut:
-- b so snh bng 4-bit entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture behavioral of eqcomp4 is begin comp: process (a, b) begin if a=b then equals <= 1; else equals<=0; end if; end process comp; end behavioral;
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2.2. Thn kin trc (Architecture body) (tt) M t lung d liu: m t cch d liu truyn t ng vo n ng ra (khng dng cc pht biu tun t). V d 2.5: M t dng lung d liu: -- b so snh bng 4-bit library ieee; use ieee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture dataflow of eqcomp4 is begin equals <= 1 when (a=b) else 0; end dataflow;
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2.2. Thn kin trc (Architecture body) (tt) V d 2.6: M t dng lung d liu khc:
-- b so snh bng 4-bit library ieee; use ieee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; architecture bool of eqcomp4 is begin equals <= not(a(0) xor b(0)) and not(a(1) xor b(1)) and not(a(2) xor b(2)) and not(a(3) xor b(3)) ; end bool;
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2.2. Thn kin trc (Architecture body) (tt) M t dng cu trc: Cha cc danh sch kt ni (netlist) cc thnh phn (component) c khi to v c kt ni vi nhau qua cc tn hiu. Thit k dng phn tng (hierarchical design).
Top-down design Bottom-up design
Structural Decomposition
Behavioral Modeling
a. Full Tree Design
Behavioral Modeling
b. Partial Tree Design
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2.2. Thn kin trc (Architecture body) (tt) V d 2.7: M t dng cu trc:
library ieee; use ieee.std_logic_1164.all; entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0); equals: out std_logic); end eqcomp4; use work.gatespkg.all; architecture struct of eqcomp4 is signal x: std_logic_vector(0 to 3); begin u0: xnor2 port map (a(0), b(0),x(0)); u1: xnor2 port map (a(1), b(1),x(1)); u2: xnor2 port map (a(2), b(2),x(2)); u3: xnor2 port map (a(3), b(3),x(3)); u4: and4 port map (x(0), x(1),x(2),x(3),equals); end struct;
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2.3. Danh hiu Danh hiu c bn: gm cc k t alphabet, cc k s v du gch di. K t u tin phi l ch ci. K t cui cng khng c l du gch di. Khng phn bit ch hoa/thng. Khng cho php hai du gch di xut hin lin tip. Danh hiu m rng: chui k t c ghi gia hai du \ C th s dng bt c k t cho php no, bao gm c cc k t !, ., @, v $. Phn bit ch hoa v ch thng.
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2.3. Danh hiu (tt) V d 2.9: Cc danh hiu no sau y l hp l:

_tx_clk? Sai: phi bt u bng mt ch ci. Tx_clk? ng: danh hiu hp l. 6A15X? Sai: khng c bt u bng mt ch s. Big#buffer? Sai: khng c c k t # trong danh hiu. Select? Sai: t kha. tx_clk_ Sai: k t cui cng khng c l du gch di. ABC_456? ng: danh hiu hp l. Tx__clk Sai: khng cho php hai du gch di lin tip.
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2.4. Cc i tng d liu i tng d liu gi gi tr c kiu d liu c th. i tng d liu thuc mt trong 4 lp: hng s, bin s, tn hiu v tp tin (file). Kh nng nhn thy (visibility): Mot oi tng c khai bao trong mot package co the c tham chieu bi mot entity hay mot architecture dung package o. Mot oi tng c khai bao trong mot entity ch c thay trong entity o. Mot oi tng c khai bao trong mot architecture ch c thay trong architecture o. Mot oi tng c khai bao trong mot process ch c thay trong process o.
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2.4.1 Hng s Gi mt gi tr khng i trong m t thit k. Gi tr ny thng c gn khai bo. Khai bo: constant constant_name: type_name [:= value]; V d 2.10: Cc khai bo hng s: constant bus_width: integer := 8; constant rise_time: time := 10ns; constant iteration: integer := 4; c khai bao trong vung khai bao cua package, entity, architecture hay process. ng dung: nh ngha noi dung cua ROM hay cac thong so co nh (delay, so lan lap, rise time, hold time ).
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2.4.2 Tn hiu ai dien cho gia tr d lieu tren cac ng d lieu thc trong mach (wire, port ) hay trang thai cua cac phan t nh. Khai bao: signal signal_name: type_name [:= initial value]; V du 2.11: Cac khai bao tn hieu signal clock: bit; signal databus: std_logic_vector(0 to 7); Thng c khai bao trong phan khai bao cua entity hay architecrture. Co hai chieu: thi gian va gia tr. Mot gia tr c gan en mot tn hieu khong lam tn hieu thay oi tc thi ma phai sau mot thi gian delay nho. Ky hieu phep gan: <=
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2.4.3 Bin s Ch dung trong cac process hay subprogam (function va procedure). Khai bao: variable variable _name: type_name [:= initial value]; V du 2.12: Cac khai bao bien so variable result: std_logic := 0; variable sum: integer range 0 to 100 := 10; Phi c khai bao trong vung khai bao cua cac process hay subprogam. Phep gan cho mot variable la tc thi (khong co chieu thi gian). Ky hieu phep gan: := Cac bien c dung chu yeu cho muc ch tnh toan (vong lap, tr trung gian, ).
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2.5. Cc kiu d liu Trong VHDL cc i tng d liu ca cc kiu c bn (base type) khc nhau khng th gn cho nhau m khng dng hm chuyn i kiu. V d 2.13: Nu a v b u l cc bin nguyn th php gn a <= b + 1; s pht sinh li tr khi ton t + l overloaded. Cc kiu d liu trong VHDL c th chia ra lm 4 loi chnh: Kiu v hng (kiu mt chiu) Kiu phc hp (kiu a chiu) Kiu truy cp (access) Kiu tp tin (file)
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2.5.1. Kiu v hng Kiu v hng ch gi mt gi tr ti thi im m phng hin hnh (current simulation time). Kiu v hng c th t cho php dng vi cc ton t quan h. C 4 loi kiu v hng: (1) Kiu lit k (enumeration type) (2) Kiu s nguyn (integer type) (3) Kiu s du chm ng (floating type) (4) Kiu vt l (physical type)
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2.5.1.1. Kiu lit k Danh sch cc gi tr m mt i tng c th gi. Kiu lit k c th t: gi tr pha tri nht l nh nht, tng dn theo chiu sang phi v gi tr pha phi nht l ln nht. Cc kiu nh ngha sn (predefined) trong cc gi standard, std_logic_1164, standard: bit, boolean, character std_logic_1164: std_ulogic, std_logic V d 2.14: type boolean is (false, true); type bit is (0, 1);
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2.5.1.1. Kiu lit k (tt) std_ulogic: h thng 9 mc logic type std_ulogic is (U, X, 0, 1, Z, W, L, H, -); Kiu std_logic c cng tp gi tr nh std_ulogic nhng c hm phn gii, resolved, phn gii mc logic khi c nhiu php gn n cng mt tn hiu. subtype std_logic is resolved std_ulogic;
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2.5.1.1. Kiu lit k (tt) Do ngi s dng nh ngha (user-defined): V d 2.15: type states is (read, write , play, sleep); signal current_state: states; type sports is (baseball, football, basketball, soccer, running); signal your_sport: sports; better_than_baskball<=1 when your_sport>= basketball else 0;
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2.5.1.2. Kiu integer VHDL h tr cc s nguyn trong khong 2147483648 (hay (231-1)) 2147483647 ((231-1)) (32-bit) type integer is range -2147483648 to 2147483647; Mt i tng kiu integer c th rng buc vi mt khong. variable a : integer range -255 to 255; Cc thao tc vi s c du v khng du ty cng c tng hp h tr. 2.5.1.3. Kiu real Gi tr trong khong -1.0E38 +1.0E38 type real is range -1.0E38 to 1.0E38; Thng khng c h tr trong cc cng c tng hp do lng ti nguyn cn ci t cc thao tc s hc l rt ln.
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2.5.1.4. Kiu vt l Thng l cc n v o, khng c ngha cho vic tng hp. V d 2.16: Kiu vt l nh ngha sn l time type time is range -2147483647 to 2147483647 units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units;
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2.5.2. Kiu phc hp Mt i tng kiu phc hp c th gi nhiu gi tr ti 1 thi im. C 2 loi kiu phc hp: (1) Kiu mng (array type) (2) Kiu bn ghi (record type)
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2.5.2.1. Kiu mng i tng kiu mng gm nhiu phn t c cng kiu d liu. Cc kiu nh ngha sn: V d 2.17: type bit_vector is array (natural range <>) of bit; type std_logic_vector is array (natural range <>) of std_logic; signal a: std_logic_vector (7 downto 0); Ngi dng cng c th nh ngha kiu ring: V d 2.18: type byte is array(7 downto 0) of bit; signal b: byte; type data_word is array (7 downto 0) of std_logic; -- 1D type ROM is array (0 to 125) of data_word; -- 1D x 1D type decode_matrix is array (positive range 15 downto 1, natural range 3 downto 0) of std_logic; -- 2D
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2.5.2.1. Kiu mng (tt) Mt i tng mng c th gn cho mt i tng mng khc c cng kiu d liu. Php gn c th thc hin cho ton b mng, mt phn t hay mt phn ca mng. V d 2.19: signal X: std_logic_vector(0 to 3); X <= 1100; X(3) <= 0; X(0 to 2) <= 101; C th dng k hiu ch nh c s cho mt chui bit: nh phn (B), bt phn (O) v thp lc phn (X). V d 2.20: signal a: std_logic_vector(0 to 7); a <= X7A;
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2.5.2.2. Kiu bn ghi i tng kiu bn ghi gm nhiu phn t c th c cc kiu d liu khc nhau. V d 2.21: type iocell is record buffer_inp : bit_vector(7 downto 0); enable: bit; buffer_out: bit_vector(7 downto 0); end record; signal busa, busb, busc: iocell; busa.buffer_inp <= 01101011; busb.buffer_inp <= busa.buffer_inp; busb.enable <= 1; busc <= busb;
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2.5.3. Kiu con (subtype) V d 2.22: type byte_size is integer range 0 to 255; signal my_int: byte_size; signal your_int: integer range 0 to 255; Thao tc sau pht sinh li bin dch: if my_int=your_int then Kiu con l kiu c bn (base type) vi mt rng buc. V d 2.23: type DIGIT is (0,1,2,3,4,5,6,7,8,9); subtype MIDDLE is DIGIT range 3 to 7; subtype byte is bit_vector(7 downto 0); signal b1: byte; signal b2: bit_vector(7 downto 0); Thao tc sau khng pht sinh li bin dch: if b1 = b2 then
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2.5.4. Mt s kiu d liu b sung Chun IEEE 1076.3 nh ngha 2 package VHDL: numeric_bit v numeric_std. Hai package ny m rng mt vi ton t v nh ngha mt s hm mi cho cc kiu unsigned v signed. Numeric_std: type unsigned is array (natural range <>) of std_logic; type signed is array (natural range <>) of std_logic; Numeric_bit: type unsigned is array (natural range <>) of bit; type signed is array (natural range <>) of bit; Tham kho thm cc package khc trong \Refs\ieee1164pkg.pdf
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2.5.5. Chuyn i kiu d liu Chuyn i t mt kiu d liu ny sang mt kiu d liu khc. Cc package b sung cung cp sn mt s hm chuyn i kiu (tham kho \Refs\ieee1164pkg.pdf). V d 2.24:
- to_stdlogicvector(bit_vector): chuyn bit_vector thnh std_logic_vector. signal a: bit_vector(3 downto 0); signal b: std_logic_vector(3 downto 0); a <= 0101; b <= to_stdlogicvector(a); - conv_std_logic_vector(integer, bits): chuyn integer thnh std_logic_vector. conv_std_logic_vector(7,4) s cho kt qu l 0111 - conv_integer(std_logic_vector): chuyn std_logic_vector thnh integer. conv_integer(0111) s cho kt qu l 7
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2.6. Cc ton t Biu thc (expression): bao gm cc ton t v cc ton hng. Mi ton t (operator) c ch nh vi mt hay mt s kiu d liu c th dng ton t vi cc ton hng thuc kiu d liu khng c h tr l khng hp l cc ton t m rng (overloaded operators). Cc ton t c sn trong VHDL
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2.6. Cc ton t (tt) Mt s lu : Cc ton hng trong cc php ton s hc phi cng kiu, ngoi tr php ton ly m cn s m phi l s nguyn. Cc ton t logic khng c th t u tin nh trong i s Boole cn dng cc du ngoc trong cc phng trnh logic nhiu tng (multilevel logic equations). V d 2.25:
X = A + B.C trong i s Boole c tnh l X = A + (B.C) Nhng trong VHDL s l X = (A + B).C Do on m: X <= A or B and C cn vit li l X <= A or (B and C)
Cc ton hng trong cc php ton quan h phi cng kiu, tuy nhin kt qu lun l kiu Boolean (True hay False). Overloaded operators: tham kho \Refs\ieee1164pkg.pdf
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2.7. Cc thuc tnh Cung cp thng tin b sung v mt tn hiu, bin, kiu d liu hay mt thnh phn (component). Mt s thuc tnh nh ngha sn thng dng: Mt s thuc tnh ca kiu v hng v kiu mng:
X'high gii hn trn ca X (hay ch s trn nu X l 1 mng) X'low gii hn di ca X (hay ch s di nu X l mng) X'left gi tr pha tri nht ca X (hay ch s pha tri nht nu X l 1 mng) X'right gi tr pha phi nht ca X (hay ch s pha phi nht nu X l 1 mng)
Mt s thuc tnh ca kiu mng c rng buc:

X'range khong ca X (thng dng trong cc vng lp loop) X'reverse_range khong ca X theo th t ngc X'length X'high - X'low + 1 (integer)
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2.7. Cc thuc tnh (tt) Mt s thuc tnh ca tn hiu:

X'event c gi tr True khi c mt s kin trn X (kiu Boolean, thng dng pht hin xung clock).
V d 2.26: type count is integer range 0 to 127; type states is (read, write, play, sleep); type word is array(15 downto 0) of std_logic; countleft = 0; counthigh = 127; countright = 127 wordleft = 15; wordhigh = 15; wordlength=16. statesleft = read; stateslow=read, stateshigh=sleep variable temp : bit_vector(15 downto 0); for i in temp'range loop ...-- lp 16 ln if (clock'event and clock = 1) then -- pht hin cnh ln clock
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Cc li thng gp V d 2.27: library ieee; use ieee.std_logic_1164.all; entity many_errors is port a: out std_logic_vector( 3 to 0); b: out std_logic_vector(0 to 3); c: in bit_vector(5 downto 0);) end many_errors -----------------------------------------------entity no_error is port ( a: out std_logic_vector( 3 downto 0); b: out std_logic_vector(0 to 3); c: in bit_vector( 5 downto 0)); end no_error;
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Cc li thng gp (tt) V d 2.27: (tt)

architecture terrible of many_errors begin my_label: process (c,a) begin if c = xF then b <= a else b = 0101; end if end process; end terrible ------------------------------------------architecture terrible of no_error is begin my_label: process (c,a) begin if c = 001111 then b <= a; else b <= 0101; end if; end process; end terrible; Ging vin: Nguyn Hu Chn Thnh
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3. CC PHT BIU NG THI (Concurrent Statements) 3.1. Php gn tn hiu n gin Dng tng qut: signal_name <= [transport] expression [after delay] {,expression2 [after delay2]}; V d 3.1: f <= (x1 and x2) or x3; -- b cng bn phn c delay sum <= a xor b after 5 ns; carry <= a and b after 10 ns; -- to dng sng pulse <= '1', '0' after 10 ns, '1' after 30 ns, '0' after 50 ns; -- gn tn hiu vi others S <= 0000; S <= (others => 0);
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3.1. Php gn tn hiu n gin (tt) Php gn tn hiu l khng tc thi c delay Inertial delay (mc nh) Transport delay V d 3.2:
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3.1. Php gn tn hiu n gin (tt) Mi php gn tn hiu ng thi trong architecture to ra mt driver cho tn hiu nhiu php gn s to ra nhiu driver. V d 3.3:
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3.1. Php gn tn hiu n gin (tt) V d 3.4: To mch t hp vi pht biu gn tn hiu n gin status <= '1'; even <= (pl and p2) or (p3 and p4); arith_result <= a + b + c - 1;
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3.1. Php gn tn hiu n gin (tt) Lu : Php gn tn hiu vi vng hi tip kn: c th to ra trng thi ni khng mong mun hay mch b dao ng. V d 3.5: q <= (q and (not en)) or (d and en); q s bng d khi en = 1 v gi nguyn gi tr trc nu en = 0 q ph thuc ng vo v trng thi ni khng phi mch t hp. q <= ((not q) and (not en)) or (d and en); q dao dng gia 0 v 1 khi en = 0.
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3.2. Php gn tn hiu c chn lc Dng tng qut: with select_expression select signal_name <= expression_1 when choice_1, expression_2 when choice_2, expression_n when choice_n; Lu : choice_i phi l mt gi tr hp l hay mt tp cc gi tr hp l ca select_expression. Cc gi tr ca choice_i phi loi tr nhau (mutually exclusive) v ph tt c cc gi tr c th ca select_expression. T kha others c th c dng trong chn la cui cng i din cho tt c cc gi tr khng dng.
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3.2. Php gn tn hiu c chn lc (tt) V d 3.6: M t mch MUX 4 1 vi mi knh ng vo l 8-bit
library ieee ; use ieee.std_logic_1164.all; entity mux4 is port ( a,b,c,d: in std_logic_vector(7 downto 0); s: in std_logic_vector(1 downto 0); x: out std_logic_vector(7 downto 0) a[7:0] ); end mux4; b[7:0] architecture sel_arch of mux4 is begin c[7:0] with s select x <= a when 00, d[7:0] b when 01, c when 10", s(1) d when others; end sel_arch;
s(0)
MUX
00 01
x[7:0]
10
11
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3.2. Php gn tn hiu c chn lc (tt) V d 3.7: M t mch gii m 2 4 vi ng ra tch cc mc 1

library ieee ; use ieee.std_logic_1164.all; entity decoder4 is port ( s: in std_logic_vector (1 downto 0); x: out std_logic_vector (3 downto 0) ); end decoder4 ; architecture sel_arch of decoder4 is begin with s select x <= 0001 when 00, 0010 when 01, 0100 when 10, 1000 when others; end sel_arch;
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3.2. Php gn tn hiu c chn lc (tt) V d 3.8: M t mch m ha u tin 4 2

library ieee; use ieee.std_logic_1164.all; entity prio_encoder42 is port ( r: in std_logic_vector(3 downto 0); code: out std_logic_vector(1 downto 0); active: out std_logic ); end prio_encoder42; architecture sel_arch of prio_encoder42 is begin with r select code <= 11 when 1000|1001|1010|1011|1100|1101|1110|1111, 10 when 0100|0101|0110|0111, 01 when 0010|0011, 00 when others; active <= r(3) or r(2) or r(1) or r(0); end sel_arch; Ging vin: Nguyn Hu Chn Thnh
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3.2. Php gn tn hiu c chn lc (tt) V d 3.9: M t mch theo bng chn tr sau:
library ieee; use.ieee.std_logic_1164.all; entity truth_table is port ( a,b: in std_logic; y : out std_logic ); end truth_table ; architecture a of truth_table is signal tmp: std_logic_vector (1 downto 0); begin tmp <= a & b; with tmp select y <= 0 when 00, 1 when 01, 1 when 10, 1 when others; -- 11 end a; Ging vin: Nguyn Hu Chn Thnh
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3.2. Php gn tn hiu c chn lc (tt) Vn ci t mch ca pht biu gn tn hiu chn lc: da trn mch dn knh (MUX). V d 3.10: Xt pht biu sau: with select_expression select sig <= value_expr_0 when c0, value_expr_1 when cl, value_expr_n when others; Gi s select_expression c 1 trong 5 gi tr: c0, c1, c2, c3 v c4.
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3.2. Php gn tn hiu c chn lc (tt) V d 3.11: Xt on VHDL sau: signal s: std_logic_vector (1 downto 0) ; with s select x <= (a and b) when 11, (a or b) when 01|10, 0 when others;
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3.3. Php gn tn hiu theo iu kin Dng tng qut: signal_name <= expression_1 when boolean_expression_1 else expression_2 when boolean_expression_2 else expression_n; Lu : Boolean_expression_i tr v gi tr True hay False. Cc biu thc boolean_expression_i c tnh ln lt t trn xung cho n khi gp gi tr True th gn gi tr ca biu thc expression_i tng ng cho tn hiu. Gi tr cui cng expression_n s c gn cho tn hiu nu khng c iu kin no l True.
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.12: M t mch MUX 4 1 vi mi knh ng vo l 8-bit
library ieee ; use ieee.std_logic_1164.all; entity mux4 is port ( a,b,c,d: in std_logic_vector(7 downto 0); s: in std_logic_vector(1 downto 0); x: out std_logic_vector(7 downto 0) ); end mux4; architecture cond_arch of mux4 is begin x <= a when (s = 00) else b when (s = 01) else c when (s = 10) else d; end cond_arch;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.13: M t mch gii m 2 4 vi ng ra tch cc mc 1
library ieee ; use ieee.std_logic_1164.all; entity decoder4 is port ( s: in std_logic_vector (1 downto 0); x: out std_logic_vector (3 downto 0) ); end decoder4 ; architecture cond_arch of decoder4 is begin x <= 0001 when (s = 00) else 0010 when (s = 01) else 0100 when (s = 10) else 1000; end cond_arch;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.14: M t mch m ha u tin 4 2

library ieee; use ieee.std_logic_1164.all; entity prio_encoder42 is port ( r: in std_logic_vector(3 downto 0); code: out std_logic_vector(1 downto 0); active: out std_logic ); end prio_encoder42; architecture cond_arch of prio_encoder42 is begin code <= 11 when (r(3) = 1) else 10 when (r(2) = 1) else 01 when (r(1) = 1) else 00; active <= r(3) or r(2) or r(1) or r(0); end cond_arch; Ging vin: Nguyn Hu Chn Thnh
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3.3. Php gn tn hiu theo iu kin (tt) Vn ci t mch ca pht biu gn tn hiu theo iu kin: Cn 3 nhm phn cng: Cc mch cho cc gi tr biu thc gn cho tn hiu Cc mch cho cc biu thc iu kin Boolean H thng mch u tin (theo iu kin) H thng mch u tin c th ci t bng mt chui cc MUX 2 1. V d 3.15: Xt pht biu n gin sau vi 1 mnh when: sig <= value_expr_1 when boolean_expr_1 else value_expr_2;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.16: Xt pht biu sau vi 3 mnh when: sig <= value_expr_1 when boolean_expr_1 else value_expr_2 when boolean_expr_2 else value_expr_3 when boolean_expr_3 else value_expr_4;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.17: Xt on VHDL sau: signal a, b, y: std_logic; y <= 0 when a=b else 1;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.18: Xt on VHDL sau: signal r: std_logic_vector(2 downto 1); signal y: std_logic_vector(1 downto 0); y <= 10 when r(2)= 1 else 01 when r(1)= 1 else 00;
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3.3. Php gn tn hiu theo iu kin (tt) V d 3.19: Xt on VHDL sau: signal a, b, c, x, y, r: std_logic; r <= a when x = y else b when x > y else c;
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3.3. Php gn tn hiu theo iu kin (tt) So snh gia pht biu gn tn hiu chn lc v theo iu kin: Trong pht biu gn tn hiu chn lc, mi chn la tng ng vi mt hng trong bng chn tr. thch hp cho cc mch m t bng bng chn tr hay bng hot ng nh bng chn tr. Trong pht biu gn tn hiu theo iu kin, cc iu kin phi theo th t t trn xung. thch hp cho cc mch cn c s u tin gia cc hot ng.
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3.4. Pht biu khi tr component Dng tng qut: label: component_name generic map(generic_association_list) port map(port_association_list); C 2 cch kt hp gia cc tham s hnh thc v cc tham s thc: Kt hp theo v tr (positional association): mi tham s thc trong khi tr component c nh x theo v tr ca tham s hnh thc trong khai bo component. Kt hp theo tn (named association): formal1 => actual1, formal2 => actual2,
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3.4. Pht biu khi tr component (tt) V d 3.20:

entity dec2to4 is port(s0,s1,en : in bit; y0,y1,y2,y3 : out bit); end dec2to4; architecture structural of dec2to4 is component inv port(a : in bit; b : out bit); end component; component and3 port(a1,a2,a3 : in bit; o1 : out bit); end component; signal ns0,ns1 : bit; begin i1 : inv port map(s0,ns0); i2 : inv port map(s1,ns1); a1 : and3 port map(en,ns0,ns1,y0); a2 : and3 port map(en,s0,ns1,y1); a3 : and3 port map(en,ns0,s1,y2); a4 : and3 port map(a1 => en, a2 => s0, a3 => s1, o1 => y3); end structural; Ging vin: Nguyn Hu Chn Thnh
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3.5. Pht biu process Dng tng qut: [label:] process [sensitivity_list] is -- is [VHDL-93] process declarations begin sequential statements end process [label]; Process c 2 trng thi: Thc thi (execution): mi khi c mt trong cc tn hiu trong danh sch cm nhn (sensitivity list) thay i gi tr. Treo (suspension): khi thc thi xong pht biu cui cng trong process hay gp pht biu wait. wait for time_expression; wait until boolean_condition; wait on sensitivity_list;
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3.5. Pht biu process (tt) V d 3.21: proc1: process (a,b,c) begin x <= a and b and c; end process; proc2: process begin x <= a and b and c; wait on a, b, c; end process;
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3.5. Pht biu process (tt) Mt s cng c tng hp khng kim tra danh sch cm nhn, thay vo chng gi s l tt c cc tn hiu bn phi ca php gn v cc tn hiu trong cc biu thc iu kin l trong danh sch cm nhn. V d 3.22: proc3: process (a,b,c) begin x <= a and b and c; end process; proc4: process (a,b) -- khng c bin c begin x <= a and b and c; end process;
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3.5. Pht biu process (tt) VHDL to ra mt driver duy nht cho mi tn hiu c gn gi tr bn trong mt process tt c cc hot ng c thc hin trn driver v ch cp nht cho tn hiu khi process treo. Ch c php gn cui cng n tn hiu l c tc ng. V d 3.23: Gi s A, B, C, D, E l cc tn hiu v ban u u bng 1. Xc nh gi tr ca chng sau khi thc thi process sau:
signal A,B,E: integer; process (C, D) begin A <= 2; B <= A + C; A <= D + 1; E <= A*2; end process;
process (C, D) variable AV,BV,EV: integer; begin AV := 2; BV := AV + C; AV := D + 1; EV := AV*2; A <= AV; B <= BV; E <= EV; end process; Ging vin: Nguyn Hu Chn Thnh
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4. CC PHT BIU TUN T (Sequential Statements) 4.1. Pht biu if .. then .. else if boolean_expression then {sequential_statement} [{elsif boolean_expression then {sequential_statement} }] [else {sequential_statement} ] end if; Lu : Cc biu thc Boolean s c tnh tun t. Khi mt biu thc c gi tr True, cc pht biu trong nhnh tng ng c thc thi, cc nhnh cn li s b b qua. Nu khng c biu thc no l True, cc pht biu ca nhnh else s c thc thi.
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4.1. Pht biu if .. then .. else (tt) V d 4.1: M t mch MUX 4 1 architecture if_arch of mux4 is begin mux_4_1: process (a, b, c, d, s) begin if s = 00 then x <= a; elsif s= 01 then x <= b; elsif s = 10 then x <= c; else x <= d; end if; end process; end if_arch;
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4.1. Pht biu if .. then .. else (tt) V d 4.2: M t mch gii m 2 4

architecture if_arch of decoder4 is begin process (s) begin if (s = 00) then x <= 0001; elsif (s = 01) then x <= 0010; elsif (s = 10) then x <= 0100; else x <= 1000; end if ; end process; end if_arch;
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4.1. Pht biu if .. then .. else (tt) V d 4.3: M t mch m ha u tin 4 2

architecture if_arch of prio_encoder42 is begin process (r) begin if (r(3) = 1) then x <= 11; elsif (r(2) = 1) then x <= 10; elsif (r(1) = 1) then x <= 01; else x <= 00; end if ; end process; active <= r(3) or r(2) or r(1) or r(0); end if_arch;
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4.1. Pht biu if .. then .. else (tt) Cc nhnh khng y V d 4.4: Xt on m sau: process (a, b) begin if (a=b) then eq <= 1; end if; end process; process (a, b) begin if (a=b) then eq <= 1; else eq <= eq; end if; end process;
ngm nh trng thi (b nh) ni. eq <= 0;
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4.1. Pht biu if .. then .. else (tt) Php gn tn hiu khng y V d 4.5: Xt on m sau: process (a, b) begin if (a>b) then gt <= 1; elsif (a=b) then eq <= 1; else lt <= 1; end if ; end process;
process (a, b) begin if (a>b) then gt <= 1; eq <= 0; lt <= 0; elsif (a=b) then gt <= 0; eq <= 1; lt <= 0; else gt <= 0; eq <= 0; lt <= 1; end if ; end process;
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4.1. Pht biu if .. then .. else (tt) Mt cch khc cho m gn v r rng hn: V d 4.6: Xt on m sau: process (a, b) process (a, b) begin begin gt <= 0; if (a>b) then eq <= 0; gt <= 1; lt <= 0; elsif (a=b) then if (a>b) then eq <= 1; gt <= 1; else elsif (a=b) then lt <= 1; eq <= 1; end if; else end process; lt <= 1; end if; end process;
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4.1. Pht biu if .. then .. else (tt) Vn ci t mch ca pht biu if: dng h thng mch u tin tng t pht biu gn tn hiu theo iu kin. V d 4.7: Xt on m sau: if boolean_expression then sig_a <= value_expr_a_1; sig_b <= value_expr_b_1; else sig_a <= value_expr_a_2; sig_b <= value_expr_b_2; end if;
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4.1. Pht biu if .. then .. else (tt) Ghp cc pht biu if n: V d 4.8: Xt li v d mch m ha u tin 4 2:
architecture cascade_if_arch of prio_encoder42 is begin process (r) begin x <= 00; if (r(1) = 1) then x <= 01; end if; if (r(2) = 1) then x <= 10; end if; if (r(3) = 1) then x <= 11; end if; end process; active <= r(3) or r(2) or r(1) or r(0); end cascade_if_arch; Ging vin: Nguyn Hu Chn Thnh
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4.2. Pht biu case .. when Dng tng qut: case expression is when choice_1 => {sequential_statement} when choice_2 => {sequential_statement} when choice_n => {sequential_statement} end case; Lu : choice_i phi l mt gi tr hp l hay mt tp cc gi tr hp l ca expression. Cc gi tr ca choice_i phi loi tr nhau (mutually exclusive) v ph tt c cc gi tr c th ca select_expression. T kha others c th c dng trong chn la cui cng ph cho tt c cc gi tr khng dng.
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4.2. Pht biu case .. when (tt) V d 4.9: M t mch MUX 4 1

architecture case_arch of mux4 is begin mux_4_1: process (a, b, c, d, s) begin case s is when 00 => x <= a; when 01 => x <= b; when 10 => x <= c; when others => x <= d; end case; end process; end case_arch;
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4.2. Pht biu case .. when (tt) V d 4.10: M t mch gii m 2 4

architecture case_arch of decoder4 is begin process (s) begin case s is when 00 => x <= 0001; when 01 => x <= 0010; when 10 => x <= 0100; when others => x <= 1000; end case; end process; end case_arch;
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4.2. Pht biu case .. when (tt) V d 4.11: M t mch m ha 4 2

architecture case_arch of prio_encoder42 is begin process (r) begin case r is when 1000|1001|1010|1011|1100|1101|1110|1111 => code <= 11; when 0100|0101|0110|0111 => code <= 10; when 0010|0011 => code <= 01; when others => code <= 00; end case; end process; active <= r(3) or r(2) or r(1) or r(0); end case_arch;
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4.2. Pht biu case .. when (tt) Vn gn tn hiu khng y : V d 4.12: Xt on m sau:
process (a) begin case a is when 100|101|110|111 => high <= '1'; when 010|011 => middle <= '1'; when others => low <='l'; end case; end process;
process (a) begin case a is when 100|101|110|111 => high <= 1; middle <= 0; low <=0; when 010|011 => high <= 0; middle <= 1; low <= 0; when others => high <= 0; middle <= 0; low <= 1; end case; end process;
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4.2. Pht biu case .. when (tt) Mt cch khc cho m gn hn: V d 4.13: Xt on m sau:
process (a) begin case a is when 100|101|110|111 => high <= '1'; when 010|011 => middle <= '1'; when others => low <='l'; end case; end process;
process (a) begin high <= 0; middle <= 0; low <=0; case a is when 100|101|110|111 => high <= 1; when 010|011 => middle <= 1; when others => low <= 1; end case; end process;
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4.2. Pht biu case .. when (tt) Vn ci t mch ca pht biu case: dng mch dn knh tng t pht biu gn tn hiu chn lc. V d 4.14: Xt on m sau: case case_expr is when c0 => sig_a <= value_expr_a_0; sig_b <= value_expr_b_0; when c1 => sig_a <= value_expr_a_1; sig_b <= value_expr_b_1; when others => sig_a <= value_expr_a_n; sig_b <= value_expr_b_n; end case; Gi s case_expr c th c 5 gi tr: c0, c1, c2, c3 v c4.
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Bi tp M t mch gii m 3 8 (74LS138)
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5. THIT K MCH TUN T Mt tn hiu s to ra cht/flip-flop nu c gn di s thay i ca mt tn hiu khc. if (clk = 1) then to cht if (clkevent and clk = 1) then to flip-flop (cnh ln) Nu php gn cho bin c thc hin di s thay i ca tn hiu khc v gi tr ny sau truyn li cho mt tn hiu to cht/flip-flop. Mt bin s to ra cht/flip-flop nu n c dng trc khi c gn mt gi tr.
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5. THIT K MCH TUN T (tt) V d 5.1: process (clk) begin if (clk'event and clk='1') then output1 <= temp; -- output1 c lu output2 <= a; -- output2 c lu end if; end process; process (clk) begin if (clk'event and clk='1') then output1 <= temp; -- output1 c lu end if; output2 <= a; -- output2 khng c lu end process;
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5. THIT K MCH TUN T (tt) V d 5.2: Bin temp lm cho tn hiu x c lu process (clk) variable temp: bit; begin if (clk'event and clk='1') then temp := a; end if; x <= temp; -- bin temp lm cho tn hiu x c lu end process;
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5. THIT K MCH TUN T (tt) V d 5.3: To D-FF entity dff_logic is port ( d, clk : in std_logic; q : out std_logic); end dff_logic; architecture a of dff_logic is begin process (clk) begin if (clkevent and clk = 1) then q <= d; end if; end process; end a;
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5. THIT K MCH TUN T (tt) V d 5.4: To D-FF dng pht biu wait pht hin cnh xung entity dff_logic is port ( d, clk : in std_logic; q : out std_logic); end dff_logic; architecture a of dff_logic is begin process begin wait until (clkevent and clk = 1) then q <= d; end if; end process; end a;
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5. THIT K MCH TUN T (tt) V d 5.5: To D-FF dng hm rising_edge pht hin cnh xung entity dff_logic is port ( d, clk : in std_logic; q : out std_logic); end dff_logic; architecture a of dff_logic is begin process (clk) begin if rising_edge(clk) then q <= d; end if; end process; end a;
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5. THIT K MCH TUN T (tt) V d 5.6: To T-FF entity tff_logic is port (t, clk : in std_logic; q : buffer std_logic); end tff_logic; architecture a of tff_logic is begin process (clk) begin if (clkevent and clk = 1) then if (t = 1) then q <= not(q); end if; end if; end process; end a;
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5. THIT K MCH TUN T (tt) V d 5.7: To D-FF vi ng ra q v qbar

entity dff_logic is port (d, clk : in std_logic; q : out std_logic; qbar : out std_logic); end dff_logic; architecture a of dff_logic is begin process (clk) begin if rising_edge(clk) then q <= d; qbar <= not d; end if; end process; end a;
Ging vin: Nguyn Hu Chn Thnh 100
5. THIT K MCH TUN T (tt) V d 5.8: To D-FF vi ng ra q v qbar

entity dff_logic is port (d, clk : in std_logic; q : buffer std_logic; qbar : out std_logic); end dff_logic; architecture a of dff_logic is begin process (clk) begin if rising_edge(clk) then q <= d; end if; end process; qbar <= not q; end a;
5. THIT K MCH TUN T (tt) V d 5.9: To D-FF vi reset bt ng b entity dff_async_reset is port (d, clk, rst: in std_logic; q : out std_logic); end dff_async_reset; architecture a of dff_async_reset is begin process (clk, rst) begin if (rst = 1) then q <= 0; elsif (clkevent and clk = 1) then q <= d; end if; end process; end a;
5. THIT K MCH TUN T (tt) V d 5.10: To D-FF vi reset ng b

entity dff_sync_reset is port (d, clk, rst: in std_logic; q : out std_logic); end dff_sync_reset; architecture a of dff_sync_reset is begin process (clk) begin if (clkevent and clk = 1) then if (rst = 1) then q <= 0; else q <= d; end if; end if; end process; end a;
5. THIT K MCH TUN T (tt) V d 5.11: To thanh ghi dch
5. THIT K MCH TUN T (tt) V d 5.11: To thanh ghi dch (tt)
5. THIT K MCH TUN T (tt) V d 5.11: To thanh ghi dch (tt)
din
dout
5. THIT K MCH TUN T (tt) V d 5.12: To b m ng b 8-bit vi ng ra 3 trng thi (OE), c chn cho php np d liu (LOAD) ng b v cho php m (EN).
library ieee; use ieee.std_logic_1164.all; use ieee. std_logic_unsigned.all; entity counter is port ( clk, load, oe, enable : in std_logic; data : in std_logic_vector(7 downto 0); cnt_out : out std_logic_vector(7 downto 0)); end counter; architecture cnt8 of counter is signal cnt: std_logic_vector(7 downto 0); begin process ( clk) begin
5. THIT K MCH TUN T (tt) V d 5.12: (tt)

if rising_edge(clk) then if load = 1 then cnt <= data; elsif enable = 1 then cnt <= cnt+1; end if; end if; end process; three_state: process(oe,cnt) -- three-state buffers begin if oe = 0 then cnt_out <= (others => Z); else cnt_out <= cnt; end if; end process three_state; end cnt8; Ging vin: Nguyn Hu Chn Thnh 108
5. THIT K MCH TUN T (tt) Bi tp: To mch JK_FF vi ng ra Q o v khng o
5. THIT K MCH TUN T (tt) V d 5.13: Xc nh mch tng hp ca m t VHDL sau:
5. THIT K MCH TUN T (tt) Pht biu vng lp loop: Dng tng qut: [loop_label:] [iteration_scheme] loop {sequential_statement} end loop [loop_label]; C 2 kiu lp (iteration_scheme): (1) for identifier in range (2) while boolean_expression
5. THIT K MCH TUN T (tt) V d 5.14: To thanh ghi dch t tri sang phi tng qut N-bit (mc nh N = 4) vi chn cho php np d liu ng b Load.
ENTITY shift_n IS GENERIC (N : INTEGER := 4 ) ; PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); clk : IN STD_LOGIC; Load, w : IN STD_LOGIC; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0)); END shift_n ; ARCHITECTURE behavior OF shift_n IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Load = '1' THEN Q <= D; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP; Q(N-1) <= w; END IF; END PROCESS; END behavior;
5. THIT K MCH TUN T (tt) Pht biu exit: pht biu tun t lm vic thc thi nhy ra khi vng lp trong cng hay vng lp c ch nh bi mt nhn. Dng tng qut: exit [loop_label] [when condition]; V d 5.15:
Loop_X: loop a_v := 0; Loop_Y: loop exit Loop_X when condition_1; Output_1(a_v) := Input_1(a_v); av := av + 1; exit when condition_2; end loop Loop_Y; Assign_Y: B(i) <= Output_1(i) after 10 ns; exit Loop_X when condition_3; -- nu b qua nhn Loop_X? end loop Loop_X; Assign_X: A <=B after 10 ns;
5. THIT K MCH TUN T (tt) Pht biu next: pht biu tun t ch c th dng trong vng lp cho php b qua cc pht biu cn li trong ln lp hin hnh. Dng tng qut: next [loop_label] [when condition]; V d 5.16:
Loop_X: for count_value in 1 to 8 loop Assign_1: A(count_value) := '0'; k := 0; Loop_Y: loop Assign_2: B(k) := '0'; next Loop_X when condition_1; -- nu b qua nhn Loop_X? Assign_3: B(k + 8) := '0'; k := k + 1; end loop Loop_Y; end loop Loop_X;
5. THIT K MCH TUN T (tt) Cc li thng gp

library ieee; use ieee.std_logic_1164.all; entity term-count is port clock, reset, oe : in bit; data : in std_logic_vector(7 downto 0); cnt_out : out std_logic_vector(7 downto 0); equals : out std_logic;); end term-count; architecture a of term-count signal cnt: std_logic_vector(7 downto 0); begin compare: process begin if data = cnt then equals = 1; end if; end process;
6. THIT K MCH TUN T (tt) Cc li thng gp (tt)

counter: process (clk) begin if reset = 1 then cnt <= 0000; elseif (clockevent and clock=1) cnt <= cnt + 1; end if; end process; cnt_out <= (others <= Z) when oe = 0 else cnt; end a;
6. THIT K MCH TUN T (tt) M VHDL sau khi sa li:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity term_count is port ( clock, reset, oe : in bit; data : in std_logic_vector(7 downto 0); cnt_out : out std_logic_vector(7 downto 0); equals : out std_logic); end term_count; architecture a of term_count signal cnt: std_logic_vector(7 downto 0); begin compare: process (cnt, data) begin if data = cnt then equals <= 1; else equals <= 0; end if; end process; Ging vin: Nguyn Hu Chn Thnh 117
6. THIT K MCH TUN T (tt) M VHDL sau khi sa li: (tt) counter: process (clock, reset) begin if reset = 1 then cnt <= 00000000; elsif (clockevent and clock=1) then cnt <= cnt + 1; -- khai bo thm use ieee.std_logic_unsigned.all; end if; end process; cnt_out <= (others => Z) when oe = 0 else cnt; end a;
6. THIT K MY TRNG THI C nhiu cch khc nhau m t mt my trng thi:
6. THIT K MY TRNG THI (tt) Mt khun dng m t my trng thi (reset bt ng b):
Moore output
6. THIT K MY TRNG THI (tt) Khun dng y :
6. THIT K MY TRNG THI (tt) V d 6.1: M t FSM sau:
6. THIT K MY TRNG THI (tt) Trng hp cn ng ra Mealy ng b c th dng khun dng:

Dng thm 1 tn hiu tm temp cho ng ra
6. THIT K MY TRNG THI (tt) V d 6.2: M t li FSM ca vd 6.1 vi ng ra ng b:
6. THIT K MY TRNG THI (tt) V d 6.3: M t FSM sau:
Ch dng 1 process cho khi logic trng thi k tip v hin ti

To khi logic ng ra ring
6. THIT K MY TRNG THI V d 6.3: (tt) Dng 2 process
6. THIT K MY TRNG THI V d 6.4: M t FSM sau:
Ch dng 1 process cho khi logic trng thi k tip v hin ti
To khi logic ng ra ring
6. THIT K MY TRNG THI Vn gn trng thi:

library IEEE; use IEEE.std_logic_1164.all; library SYNOPSYS; use SYNOPSYS.attributes.all; ... architecture fsmexampe_arch of fsmexamp is type Sreg_type is (INIT, A0, A1, OK0, OK1); attribute enum_encoding of Sreg_type: type is "0000 0001 0010 0100 1000"; signal Sreg: Sreg_type; ...
library IEEE; use IEEE.std_logic_1164.all; ... architecture fsmexampc_arch of fsmexamp is subtype Sreg_type is STD_LOGIC_VECTOR (1 to 4); constant INIT: Sreg_type := "0000"; constant A0 : Sreg_type := "0001"; constant A1 : Sreg_type := "0010"; constant OK0 : Sreg_type := "0100"; constant OK1 : Sreg_type := "1000"; signal Sreg: Sreg_type; ...
7. THIT K PHN CP TRONG VHDL
7. THIT K PHN CP TRONG VHDL (tt) dng mt component trong thit k cn c hai bc: Khai bo component: cho bit tn v cc giao tip ca component. Khi to component: kt hp cc tn hiu vi cc port ca component.
7. THIT K PHN CP TRONG VHDL (tt) C 2 cch c bn khai bo 1 component: Khai bo trong on m chnh ca thit k. Khai bo trong mt PACKAGE.
7. THIT K PHN CP TRONG VHDL (tt) C 2 cch kt hp gia cc tham s hnh thc v tham s thc: Theo v tr: mi tham s thc trong khi to component c nh x theo v tr ca mi port trong khai bo component.
Theo tn: danh sch kt hp c dng: (khng cn theo th t) formal1 => actual1, formal2 => actual2,
7. THIT K PHN CP TRONG VHDL (tt) V d 7.1: Thc hin mch logic nh hnh sau:
7. THIT K PHN CP TRONG VHDL (tt) V d 7.1: (tt)
7. THIT K PHN CP TRONG VHDL (tt) V d 7.1: (tt) Cng c th khai bo component trong 1 PACKAGE nh sau:
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Slide-ch4-Thiet Ke He Thong So Dung VHDL

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Bi ging mn K thut s 2

THIT K S DNG VHDL

Ging vin: Nguyn Hu Chn Thnh

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1. GII THIU (tt) Qu trnh thit k h thng s:

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1. GII THIU (tt) Cc cng c CAD: Nhp yu cu thit k (design entry)

Dng s mch (Graphic Editor) thit k phn cp

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1. GII THIU (tt) Cc cng c CAD: Nhp yu cu thit k (design entry)

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1. GII THIU (tt) Cc cng c CAD: Tng hp (synthesis):

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2. CC CU TRC C BN CA VHDL 2.1. Entity

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2.1. Entity (tt) Kiu d liu:

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a. Full Tree Design

b. Partial Tree Design

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2.3. Danh hiu (tt) V d 2.9: Cc danh hiu no sau y l hp l:

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Mt s thuc tnh ca kiu mng c rng buc:

2.7. Cc thuc tnh (tt) Mt s thuc tnh ca tn hiu:

Cc li thng gp (tt) V d 2.27: (tt)

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3.2. Php gn tn hiu c chn lc (tt) V d 3.7: M t mch gii m 2 4 vi ng ra tch cc mc 1

3.2. Php gn tn hiu c chn lc (tt) V d 3.8: M t mch m ha u tin 4 2

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3.3. Php gn tn hiu theo iu kin (tt) V d 3.14: M t mch m ha u tin 4 2

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3.4. Pht biu khi tr component (tt) V d 3.20:

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4.1. Pht biu if .. then .. else (tt) V d 4.2: M t mch gii m 2 4

4.1. Pht biu if .. then .. else (tt) V d 4.3: M t mch m ha u tin 4 2

ngm nh trng thi (b nh) ni. eq <= 0;

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