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CHNG TRNH SON THO, BIN DCH V NP CHO MSP430 <IAR EMBEDDED WORKBENCH>
1. Gii thiu v MSP430FG4618/F2013 Experimenters Board: 1.1. MSP430FG4618/F2013 Experimenters Board:

KIT MSP-EXP430FG4618 gm 1 Board MSP430FG4618/F2013 nh hnh di v 2 pin AAA 1.5V.

Hnh 1.1: MSP430FG4618/F2013 Experimenters Board

Copyright by [Trc en, virus_lazy, hacker_black_hat] S khi ca Board MSP430FG4618/F2013 nh sau:

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Hnh 1.2: S khi ca MSP430FG4618/F2013 Experimenters Board

Copyright by [Trc en, virus_lazy, hacker_black_hat]

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bi th nghim ny chng ta s tm hiu 2 thnh phn ca chip MSP430FG4618 l I/O port v LCD_A (module iu khin LCD c tch hp sn trn KIT)

Cc dng chip MSP430 l low power nn n hot ng ngun kh thp t 1.8V-3.6V. cc KIT ca TI, thng thng dng ngun 3.5V (c chuyn i t ngun 5V t cng USB) 1.2. Cc khi chc nng chnh trn boad:

1.2.1. Interfaces: 4 mux LCD display: B hin th 4 mux SoftBaugh LCD SBLCDA4 giao tip vi driver ngoi vi LCD ca MSP430FG4618. Mometary On Push Buttons: 2 nt nhn S1 v S2 c kt ni vi I/O port P1 ca MSP430FG4618. Light Emitting Diodes (LEDs): MSP430FG4618/F2013 Experimenters Board c tt c 4 LEDs. Trong , 3 LEDs c ni vi MSP430FG4618 v 1 LED ni vi MSP430F2013. 3 led ni vi MSP430FG4618 qua chn P2.1, P2.2 v P5.1

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Buzzer: Buzzer c ni vi digital I/O port ca MSP430FG4618, c th ngt kt ni bng jump JP1. Capacitive Touch Pad : Touchpad c dng s 4 nm trn board c kt ni n cc I/O port ca MSP430F2013, gm c 16 segments. JTAG Interfaces: 2 header JTAG c sn trn board gm: 4-wire JTAG cho MSP430FG4618 2-wire Spi-Bi-wire cho MSP430F2013

1.2.2. Communication Peripherals: Wireless: Module giao tip wireless c kt ni vi ch truyn USART ca MSP430FG4618 v c cu hnh bi giao thc SPI, h tr cc board CCxxxxEMK ca TI. CC2420EMK dng chun 802.15.4/Zigbee. CC1100EMK c cu hnh lm vic tn s sng mang RF 868 MHz. CC2500EMK/CC2420EMK c cu hnh lm vic tn s sng mang RF 2.4 GHz. RS 232: MSP430FG4618 h tr giao tip ni tip vi PC dng chun RS 232 (9 pins), giao tip thng qua ngoi vi USCI, cu hnh bi ch truyn UART. I2C/SPI: MSP430FG4618 v MSP430F2013 h tr cc giao thc I2C v SPI, s dng cc ngoi vi USCI v USI.

Copyright by [Trc en, virus_lazy, hacker_black_hat] 1.2.3. Analog Signal Chain:

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Hnh 1.3: Analog Signal Chain Microphone: Microphone c kt ni vi MSP430FG4618, c th enable hoc disable thng qua 1 port kt ni. Analog Filter: B lc thng cao tch cc bc 1 (1st-order active High-pass filter HPF) vi tn s ct khong 340Hz c th lc b cc tn s cc thp t microphone. B lc thng thp tch cc bc 2 Sallen-Key (2nd-order Sallen-Key active Low-pass filter LPF) vi tn s ct c 4kHz loi b cc nhiu tn s cao ng ra analog ca b chuyn i DAC.

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Hnh 1.4: Active Analog Filter Setup Analog Output: S dng jack n 3.5 mm ly tn hiu analog ng ra c kt ni vi Op-Amp OA2 tch hp trn board. u vo ca Op-Amp c ly t u ra ca b DAC12 ca MSP430FG4618.

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2. Cch kt ni b KIT vi mch np v mch np vi my tnh. -Kt ni KIT vi mch np nh hnh (kt ni mch np vi KIT qua cng JTAG1):

Copyright by [Trc en, virus_lazy, hacker_black_hat] Thay i cc Jump trn mch:

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Trn mch np, led xanh (Power) bo hiu ngun, led (Mode) bo hiu khi mch c np.

Copyright by [Trc en, virus_lazy, hacker_black_hat] 3. Trnh son tho v bin dch Download IAR Embedded Workbench 5.3 ti: http://www-s.ti.com/sc/techzip/slac050.zip

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Sau khi ci t thnh cng ta khi chy chng trnh (y chnh l trnh son tho, bin dch, np v ng thi l debugger cho KIT).

Icon trn desktop 3.1. To project:

Copyright by [Trc en, virus_lazy, hacker_black_hat]

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Nn to 1 th mc mi qun l ton b project

Copyright by [Trc en, virus_lazy, hacker_black_hat] Khi to project thnh cng th IDE s hin ra nh hnh:

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Copyright by [Trc en, virus_lazy, hacker_black_hat]

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IAR s t ng to mt file main.c v add vo project ca ta, ta s son tho code trn . Ta cng c th add thm file (cc header chng hn) vo project bng cch kch chut phi vo project > Add > Add Files

Copyright by [Trc en, virus_lazy, hacker_black_hat] 3.2. Ty chn cc thng s cho project:

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Copyright by [Trc en, virus_lazy, hacker_black_hat] Chn loi chip ang s dng cho mch l MSP430FG4618

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Copyright by [Trc en, virus_lazy, hacker_black_hat] tab Debugger chn Driver l FET Debugger

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Cc thng s cc tab khc gi nguyn.

Copyright by [Trc en, virus_lazy, hacker_black_hat]

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3.3. Bin dch v np Sau khi code xong ta tin hnh code v bin dch (v np) bng cch bm Ctrl+D hoc bm vo biu tng tam gic mu xanh nh hnh:

Copyright by [Trc en, virus_lazy, hacker_black_hat]

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Khi bin dch v np thnh cng, ta c th tin hnh debugger trc tip trn mch bng cc Step

Copyright by [Trc en, virus_lazy, hacker_black_hat]

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Thng thng ta b qua bc trn (Step) m np thng vo mch bng cch chn Run (nh hnh) (on code n gin bt led sng, gi s led c ni vi cng P1.0 ca chip)

Nh vy ta tin hnh code, bin dch v np thnh cng cho KIT. Nu sau khi np m ta thy mch vn cha chy nh mun th c th kim tra li code hoc debug tng Step li test li.

Copyright by [Trc en, virus_lazy, hacker_black_hat] Ch : y chn Debug ch ko phi Release

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Copyright by [Trc en, virus_lazy, hacker_black_hat] 4. Cu trc mt chng trnh C thng thng cho MSP430 Cc phn trong du <> c th khng c

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Ch : o Trong hm main ta thng thy dng lnh: WDTCTL = WDTPW + WDTHOLD; Stop watchdog timer n khi reset chip. Nu khng c lnh ny (v khng c ty chn khc con WDTCTL) th mch s khng hot ng. o Trong C cho MSP430, th c cc hng s c nh ngha trc ( file header), ta rt hay dng cc hng s ny: BIT0 = 0000 0001

Copyright by [Trc en, virus_lazy, hacker_black_hat] BIT1 = 0000 0010 BIT2 = 0000 0100 . . . BIT7 = 1000 0000

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o Mt chn ca MSP430 thng c nhiu chc nng, ta mun s dng chc nng g th nh ngha cho n. V d: P1DIR = 0xFF; // ton b port1 l Output P1DIR = 0x00; //ton b port1 l Input Nh vy nu mun mt s chn ca port1 l Output v mt s chn ca port1 l Input th lm th no? Khng ging mt s VK khc, MSP430 khng cho php ta tc ng trc tip n 1 chn no ring l, ch c th tc ng ln port (8 chn). Nh vy mun tc ng ln chn ring l no th ta dng php ton OR, AND v XOR. V d: P1DIR |= BIT1; //chn P1.1 s l chn Output, cc chn khc ko b nh hng bi lnh ny P1DIR &= ~BIT1; // chn P1.1 s l chn Input (nu ta ko nh ngha th n mc nh l Input) P2DIR |= BIT0 + BIT1 + BIT3; //chn P2.0, P2.1, P2.3 s l Output Lnh trn cng c th vit li: P2DIR |= 0x0B; // BIT0 + BIT1 + BIT3 = 11d=0Bh P2DIR &= ~(BIT4+BIT5); //P2DIR &=~0x30; //chn P2.4, P2.5 l Input o Xut ra port theo tng bit ring l. Nh vic nh ngha cc chn, MSP430 cng khng cho ta tc ng trc tip n tng chn no, mun xut ra mt bit hay nhiu bit bt k ta s dng cch nh dng vi nh ngha chn.

Copyright by [Trc en, virus_lazy, hacker_black_hat] V d mun cho P1.1=1, P1.3=1, P2.1=0 P1OUT |= BIT1+BIT3 ; //P1.1=1, P1.3=1 P2OUT &=~ BIT1 ; //P2.1=0 Hoc c th o mt bit chn bt k bng ln XOR ^ P1OUT ^= BIT4 ; //chn P1.4 o trng thi

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o Kim tra trng thi mt chn. Ngoi ngt ra ta c th kim tra trng thi mt chn no ang mc thp (0V) hay mc cao (1.8V n 3.6V). V d kim tra chn P1.2 if( (P1IN&BIT2)==0 ) //nu chn P1.2 bng 0 //do anything else //do anything // nu vit if( P1IN&BIT2==0 ), thiu 1 ngoc l sai

CHC CC BN HC TT!