Vi iu khin PIC16F877A

2.1 Khao sat vi iu khin PIC16F877A

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2.2.1 S chn cua vi iu khin PIC16F877A

Hinh 2.6 S chn cua vi iu khin PIC16F877A 2.2.2 Mt s thng s v vi iu khin PIC16F877A y la vi iu khin thuc ho ho PIC16Fxxx vi tp lnh gm 35 lnh co o dai 14 bit. Mi lnh u c thc thi trong mt chu ky xung clock. Tc hoat ng ti a cho phep la 20MHz vi chu ky lnh la 200ns. B nh chng trinh la 8K x 14 bit, b nh d liu la 368x8 byte RAM va b nh d liu EEPROM vi dung lng 256x8 byte. S PORT I/O la 5 vi 33 pin I/O [3]. Cac c tinh ngoai vi bao gm cac khi chc nng sau: Timer0 : B m 8 bit vi b chia tn 8 bit. Timer1 : B m 16 bit vi b chia tn s, co th thc hin chc nng m da vao xung clock ngoai vi ngay khi vi iu khin hoat ng ch sleep. Timer2 : B m 8 bit vi b chia tn s, b postcaler. Hai b Capture/ so sanh/ iu ch rng xung. Cac chun giao tip ni tip SSP ( synchronous Serial Port ), SPI va I2C. Chun giao tip ni tip USART vi 9 bit ia chi. 1 By: Trng Vn Dng K44DVT02

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Cng giao tip song song PSP ( Parallel Slave Port )vi cac chn iu khin RD,WR, CS bn ngoai. Cac c tinh Analog : - 8 knh chuyn i ADC 10bit. - Hai b so sanh Bn canh o la mt vai c tinh khac cua vi iu khin nh : - B nh flash vi kha nng ghi/xoa c 100.000 ln. - B nh EEPROM vi kha nng ghi/xoa c 1000.000 ln. - D liu b nh EEPROM co th lu tr trn 40 nm. - Kha nng t nap chng trinh vi kha nng iu khin cua phn mm. - Nap c chng trinh ngay trn mach in ICSP ( In Circuit SeRial Programming ) thng qua 2 chn.
- Watchdog timer vi b giao ng trong.

- Chc nng bao mt chng trinh. - Ch Sleep - Co th hoat ng vi nhiu dang Oscillator khac nhau. 2.2.3 S khi cua vi iu khin PIC16F877A S khi cua PIC16F877A nh hinh di [4]:

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Vi iu khin PIC16F877A

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Hinh 2.7 S khi cua PIC16F877A 2.2.4 T chc b nh Cu truc b nh cua vi iu khin PIC16F877A gm co b nh chng trinh (Program memory ) va b nh d liu ( Data memory). 2.2.4.1 B nh chng trinh ( program memory) B nh chng trinh cua vi iu khin PIC16F877A la b nh flash, dung lng b nh la 8K word ( 1word = 14 bit ) va c phn thanh nhiu trang ( t page0 n page3). Nh vy b nh chng trinh co kha nng cha c 8*1024 = 8192 lnh ( vi mi lnh sau khi ma hoa co dung lng 1 word = 14 bit [3]. ma hoa c ia chi cua 8K b nh chng trinh thi b m chng trinh phai co dung lng la 13 bit ( PC<12:0>).

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Vi iu khin PIC16F877A

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Khi vi iu khin c reset thi b m chng trinh se chi n ia chi 0000h (Reset vector ). Khi co ngt xay ra thi b m chng trinh se chi m ia chi 0004h ( Interrupt vector ). B nh chng trinh khng bao gm b nh Stack va khng c ia chi hoa bi b m chng trinh. B nh Stack c cp cu th trong phn sau.

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Vi iu khin PIC16F877A

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Hinh 2.8 B nh chng trinh PIC16F877A

2.2.4.2 B nh d liu B nh d liu cua PIC la b nh EEPROM c chia thanh nhiu bank. Vi PIC166F877A b nh d liu c chia la 4 bank. Mi bank co dung lng 128 byte, bao gm cac thanh ghi co chc nng c bit SFR ( Special Function Rigister ) nm vung ia chi thp va cac thanh ghi co muc ich chung GPR (General Purpose Register) nm vung ia chi con lai cua bank. Cac thanh ghi SFR thng xuyn c s dung (vi du nh thanh ghi STATUS ) se c t tt ca cac bank trong b nh d liu giup thun tin cho qua trinh truy xut va giam bt lnh cua chng trinh. S cu th cua b nh d liu cua PIC16F877A nh sau [4]:

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Vi iu khin PIC16F877A

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Hinh 2.9 S b nh d liu cua PIC16F877A a. Thanh ghi chc nng c bit SFR y la cac thanh ghi s dung bi CPU hoc c dung thit lp va iu khin cac khi chc nng c tich hp bn trong vi iu khin. Co th phn thanh ghi SFR thanh hai loai : thanh ghi SFR lin quan n chc nng bn trong ( CPU ) va

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Vi iu khin PIC16F877A

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thanh ghi dung thit lp va iu khin cac khi chc nng bn ngoai ( vi du nh ADC, PWM) [3]. Thanh ghi STATUS ( 03h, 83h, 103h, 183h) : thanh ghi cha kt qua thc hin cac phep toan cua khi ALU, trang thai reset va cac bit chon bank cn c truy xut trong b nh d liu.

Thanh ghi OPTION_REG (81h, 181h) : thanh ghi nay cho phep oc va ghi, cho phep iu khin chc nng pull-up cua cac chn PORTB,xac lp cac tham s v cac xung tac ng, cach tac ng cua ngt ngoai vi va b m TIMER0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh): thanh ghi cho phep oc va ghi, cha cac bit iu khin va cac bit c hiu khi TIMER0 tran va ngt ngoai vi RB0/INT va ngt interrput- on- change tai cac chn cua PORTB.

Thanh ghi PIE1 (8Ch): cha cac bit iu khin chi tit cac ngt cua cac khi chc nng ngoai vi.

Thanh ghi PIR1 (0Ch): cha c ngt cua cac khi chc nng ngoai vi, cac ngt nay c cho phep bi cac bit iu khin cha trong thanh ghi PIE1.

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Vi iu khin PIC16F877A

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Thanh ghi PIE2 (8Dh): cha cac bit iu khin cac ngt cua cac khi chc nng CCP2, SSP bus, ngt cua b so sanh va ngt ghi vao b nh EEPROM.

Thanh ghi PIR2 (0Dh): cha cac c ngt cua cac khi chc nng ngoai vi, cac ngt nay c cho phep bi cac bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cac c hiu cho bit trang thai cua ch reset cua vi iu khin.

b. Thanh ghi muc ich chung GPR Cac thanh ghi nay co th c truy xut trc tip hoc gian tip thng qua thanh ghi FSG ( File Select Register ). y la cac thanh ghi d liu thng thng, ngi s dung co th tuy theo muc ich chng trinh ma co th dung cac thanh ghi nay cha cac bin s, hng s, kt qua hoc tham s phuc vu cho chng trinh [3]. 2.2.5 Stack Stack khng nm trong b nh chng trinh hay b nh d liu ma la mt vung nh c bit khng cho phep oc hay ghi. Khi lnh CALL c thc hin hay khi mt ngt xay ra lam chng trinh bi re nhanh, gia tri cau b m chng trinh PC t ng c vi iu khin ct vao stack. Khi mt trong cac lnh RETURN, RETLW hay RETFIE c thc thi, gia tri PC se t ng c ly ra t trong stack, vi iu khin se thc hin tip chng trinh theo ung quy trinh inh trc. B nh Stack trong vi iu khin PIC ho 16F87xA co kha nng cha c 8 ia chi va hoat ng theo c ch xoay vong. Nghia la gia tri ct vao b nh Stack ln th 9 se ghi e ln gia tri ct vao Stack ln u tin va gia tri ct vao Stacsk ln th 10 se ghi e ln gia tri ct vao Stack ln th 2. 8 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

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Cn chu y la khng co c hiu nao cho bit trang thai Stack, do o ta khng bit c khi nao Stack se tran. Bn canh o tp lnh cua vi iu khin dong PIC cung khng co lnh POP hay PUSH, cac thao tac vi b nh Stack se hoan toan c iu khin bi CPU [3]. 2.2.6 Cac cng xut nhp cua PIC16F877A Cng xut nhp (I/O port) chinh la phng tin ma vi iu khin dung tng tac vi th gii bn ngoai. S tng tac nay rt a dang va thng qua qua trinh tng tac o, chc nng cua vi iu khin c th hin mt cach ro rang. Mt cng xut nhp cua vi iu khin bao gm nhiu chn I/O pin, tuy theo cach b tri va chc nng cua vi iu khin ma s lng cng xut nhp va s lng chn trong mi cng co th khac nhau. Bn canh o, do vi iu khin c tich sn bn trong cac c tinh giao tip ngoai vi nn bn cach chc nng la cng xut nhp thng thng thi mt s chn xut nhp co cac chc nng khac thc hin s tac ng cua cac daewcj tinh ngoai vi nu trn i vi th gii ngoai. Chc nng cua tng chn xut nhp trong mi cng hoan toan co th c xac lp va iu khin thng qua thanh ghi SFR lin quan n cac chn xut nhp o. Vi iu khin PIC16F877A co 5 cng xut nhp la PORTA, PORTB, PORTC, PORTD va PORTE. Cu truc va chc nng tng cng xut nhp c trinh bay cu th trong phn tip theo [3]. 2.2.6.1 PORTA PORTA (RPA ) bao gm 6 I/O pin. y la cac chn 2 chiu (bidirectional pin ) nghia la co th xut va nhp c. Chc nng I/O nay c iu khin bi thanh ghi TRISA ( ia chi 85h ). Mun xac lp chc nng cua mt chn trong PORTA la input, ta set bit iu khin tng ng vi chn o trong thanh ghi TRISA va ngc lai, mun xac lp chc nng cua mt chn trong PORTA la output ta clear bit iu khin vi chn o trong thanh ghi TRISA. Thao tac nay hoan toan tng t i vi cac PORT va cac thanh ghi iu khin tng ng ( i vi PORTA la TRISA, i vi PORTB la TRISB, i vi PORTC la TRISC, i vi PORTD la TRISD, i vi PORTE la TRISE ). Bn canh o, PORTA con la ngo ra cua b ADC, b so sanh, ngo vao analog, ngo vao xung clock cua Timer0 va ngo vao cua b giao tip MSSP (Master Synchronous Serial Port) [3]. 9 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A Chc nng cac chn trong PORTA [4]:

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Hinh 2.10 Chc nng cua cac chn trong PORTA Cac thanh ghi SFR lin quan n PORTA bao gm [3]: - PORTA (ia chi 05h): cha gia tri cua pin trong PORTA. - TRISA ( ia chi 85h): iu khin xut nhp. - CMCON ( ia chi 9Ch): thanh ghi iu khin b so sanh. - CVRCON ( ia chi 9Dh): thanh ghi iu khin b so sanh in ap. - ADCON1 ( ia chi 9Eh): thanh ghi iu khin b ADC. 2.2.6.2 PORTB

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Vi iu khin PIC16F877A

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PORTB (RPB) gm 8 pin I/O. thanh ghi iu khin xut nhp tng ng la TRISB. Bn canh o mt s chn cua PORTB con c s dung trong qua trinh nap chng trinh cho vi iu khin vi cac ch nap khac nhau. PORTB con lin quan n ngt ngoai vi va b Timer0 [3]. Chc nng cu th cua tng chn trong PORTB nh sau [4]:

Hinh 2.11 Chc nng cac chn trong PORTB Cac thanh ghi SFR lin quan n PORTB bao gm [3]: - PORTB ( ia chi 06h, 106h ): cha cac gia tri pin trong PORTB. - TRISB ( ia chi 86h, 186h ): thanh ghi iu khin xut nhp. - OPTION_REG ( ia chi 81h, 181h ): iu khin ngt ngoai vi va b Timer0.
2.2.6.3 PORTC

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Vi iu khin PIC16F877A

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PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng la TRISC. Bn canh o PORTC con cha cac chn chc nng cua b so sanh, Timer1, b PWM va cac chun giao tip ni tip I2C, SPI, SSP, USART [3]. Chc nng cu th cua cac chn trong PORTC nh sau [4]:

Hinh 2.12 Chc nng cac chn trong PORTC Cac thanh ghi iu khin lin quan n PORTC gm [3]: - PORTC ( ia chi 07h): cha gia tri pin trong PORTC. - TRISC ( ia chi 87h ): thanh ghi iu khin xut nhp. 2.2.6.4 PORTD 1 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

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PORTD ( RPD) gm 8n chn I/O. Thanh ghi iu khin xut nhp tng ng la TRISD. Ngoai ra PORTD con la cng xut d kiu cua chun giao tip PSP (Parallel Slave Port) [3]. Chc nng cu th cac chn trong PORTD nh sau [4]:

Hinh 2.13 Chc nng cac chn trong PORTD Cac thanh ghi lin quan n PORTD bao gm [3]: - PORTD : cha gia tri cac pin trong PORTD. - TRISD: thanh ghi iu khin xut nhp. 2.2.6.5 PORTE

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Vi iu khin PIC16F877A

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PORTE ( RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng la TRISE. Cac chn cua PORTE co ngo vao analog. Bn canh o PORTE con la cac chn iu khienr cua chun giao tip PSP.[3] Chc nng cu th cua cac chn trong PORTE nh sau [4]:

Hinh 2.14 Chc nng cac chn trong PORTE Cac thanh ghi lin quan n PORTE bao gm [3]: - PORTE : cha gia tri pin trong PORTE. - TRISE : iu khin xut nhp va xac lp cac thng s cho chun giao tip PSP. - ADCON1 : thanh ghi iu khin khi ADC. 2.2.7 TIMER 2.2.7.1 TIMER0

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Vi iu khin PIC16F877A

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y la mt trong ba b m hoc inh thi cua vi iu khin PIC16F877A, Timer0 la b m 8 bit c kt ni vi b chia tn ( prescaler) 8 bit. Cu truc cua Timer0 cho phep ta la chon xung clock tac ng va canh tich cc cua xung clock. Ngt Timer0 se xut hin khi Timero bi tran. Bit TMR0IE ( INTCON<5>) la bit iu khin cua Timer0. TMR0IE=1 cho phep ngt Timer0 tac ng, TMR0IE=0 khng cho phep Timer0 tac ng. S khi cua Timer0 nh sau [3]:

Hinh 2.15 S khi cua Timer0 Mun Timer0 hoat ng ch Timer ta clear bit TOSC ( OPTION_REG<5>), khi o gia tri thanh TMR0 se tng theo chu ky xung ng h ( tn s vao Timer0 bng tn s oscillator). Khi gia tri thanh ghi TMR0 t FFh tr v 00h thi ngt Timer0 se xut hin mt cach linh ng. Mun Timer0 hoat ng ch counter ta set bit TOSC ( OPTION_REG<5>), khi o xung tac ng ln b m se c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG<4>) cho phep la chon tac ng vao b m. Canh tac ng se la canh ln nu TOSE=0 va canh tac ng se la canh xung nu TOSE=1. Khi thanh 1 By: Trng Vn Dng K44DVT02

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ghi TMR0 bi tran bit TM0IF (INTCON<2>) se c set. y chinh la c ngt cua Timer0. C ngt nay phai c xoa bng chng trinh trc khi b m bt u thc hienjlaij qua trinh m. Ngt Timer0 khng th anh thc vi iu khin t ch sleep. B chia tn s ( presccaler ) c chia se gia Timer0 va WDT ( Watchdog Timer). iu o co nghia la nu prescaler c s dung cho Timer0 thi WDT^ se c h tr cua prescaler va ngc lai. Prescaler c iu khin bi thanh ghi OPTION_REG. Bit PSA (OPTION_REG<3>) xac inh i tng tac ng cua prescaler. Cac bit PS2:PS0 (OPTION_REG<2:0> ) xac inh ti s chia tn s cua prescaler. Xem lai thanh ghi OPTION_REG xac inh lai mt cach chi tit v cac bit iu khin trn[3]. Cac thanh ghi iu khin lin quan n Timer0 bao gm [3]: TMR0 ( ia chi 01h, 101h ): cha gia tri m cua Timer0. INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18bh): cho phep ngt hoat ng (GIE va PEIE). OPTION_REG ( ia chi 81h, 181h ): iu khin prescaler. 2.2.7.2 TIMER1 Timer1 la b inh thi 16 bit, gia tri cua Timer1 se c lu lai trong hai thanh ghi (TMR1H:TMR1L). C ngt cua Timer1 la bit TMR1IF ( PIR1<0>). Bit iu khin cua Timer1 la TMR1IE ( PIE<0>). Tng t nh Timer0, Timer1 cung co hai ch hoat ng: ch inh thi (Timer) vi xung kich la xung clock cua oscillator ( tn s cua Timer bng tn s cua oscillator) va ch m ( Counter) vi xung kich la xung phan anh cac s kin cn m ly t bn ngoai thng qua chn RC0/T1OSO/T1CKI ( canh tac ng la canh ln). Vic la chon xung tac ng ( tng ng vi vic la chon ch hoat ng la Timer hay Counter ) c iu khin bi TMR1CS ( T1CON<1>) [3]. S khi cua Timer1 [4]:

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Vi iu khin PIC16F877A

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Hinh 2.16 S khi cua Timer1 Ngoai ra Timer1 con co hai chc nng reset input bn trong iu khin bi mt trong hai khi CCP (Capture/Compare/PWM). Khi bit T1OSCEN (T1CON<3>) c set, Timer1 se ly xung clock t hia chn RC1/T1OSI/CCP2 va RC0/T1OSO/T1CKI lam xung m. Timer1 se bt u m sau canh xung u tin cua xung ngo vao. Khi o PORTC se bo qua s tac ng cua hai bit TRISC<1:0> va PORTC<2:1> c gan gia tri 0. Khi clear bit T1OSCEN Timer1 se ly xung t oscillator hoc t chn RC0/T1OSO/T1CKI. Timer1 co hai ch m la ng b (Synchronous) va bt ng b (Asynchronous). Ch m c quyt inh bi bit iu khin T 1SYNC (T1CON<2>). Khi T 1SYNC = 1 xung m ly t bn ngoai se khng c ng b vi xung clock bn trong, Timer1 se tip tuc qua trinh m khi vi iu khin ch sleep va ngt do Timer1 tao ra khi bi tran co kha nng anh thc vi iu khin . Khi T 1SYNC =0 xung m vao Timer1 se c ng b hoa vi xung clock bn trong. ch nay Timer1 se khng hoat ng khi vi iu khin ang ch sleep.[3]. Cac thanh ghi lin quan n Timer1 bao gm [3]: INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18Bh ): cho phep ngt hoat ng (GIE va PEIE). PIR1 ( ia chi 0Ch ): cha c ngt Timer1 ( TMR1IF). 1 By: Trng Vn Dng K44DVT02

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PIE1 ( ia chi 8Ch): cho phep ngt Timer1 ( TMR1IE). TMR1H ( ia chi 0Eh ): cha gia tri 8 bit thp cua b m Timer1. TMR1L ( dia chi 0Eh): cha 8 bit cao cua b m Timeer1. T1CON ( ia chi 10h): xac lp cac thng s cho Timer1. 2.2.7.3 TIMER2 Timer2 la b inh thi 8 bit va c h tr bi hai b chia tn prescaler va potscaler. Thanh ghi cha gia tri m cua Timer2 la TMR2. Bit cho phep ngt Timer2 tac ng la TMR2ON ( T2CON<2>). C ngt cau Timer2 la bit TMR2IF (PIR1<1>). Xung ngo vao ) tn s bng tn s oscillator) c a qua b chia tn prescaler 4 bit ( vi cac ty s chia tn s la 1:1, 1:4, 1:16 va c iu khin bi cac bit T2CKPS1:T2CKPS0(T2CON<1:0>)) [3]. S khi cua Timer2:

Hinh 2.17 S khi cua Timer2 Timer2 con c h tr bi thanh ghi PR2. Gia tri m trong thanh ghi TMR2 se tng t 00h n gia tri cha trong thanh ghi PR2, sau o c reset v 00h. khi reset thanh ghi PR2 nhn c gia tri mc inh FFh. Ngoai ra ngo ra cua Timer2 con c kt ni vi khi SSp do o Timer2 con ong vai tro tao ra xung clock ng b cho khi giao tip SSP. Cac thanh ghi lin quan n Timer2 bao gm : 1 By: Trng Vn Dng K44DVT02

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INTCON ( ia chi 0Bh, 8Bh, 10Bh, 18Bh): cho phep hoat ng toan b cac ngt (GIE va PEIE). PIR1( ia chi 0Ch) : cha c ngt Timer2 ( TMR2IF). PIE1 ( ia chi 8Ch ) : cha bit iu khin Timer2 ( TMR2IE). TMR2 ( ia chi 11h) : cha gia tri m cua Timer2. T2CON ( ia chi 12h) : xac lp ca thng s cua Timer2. PR2 ( ia chi 92h) : thanh ghi h tr cho Timer2. 2.2.8 ADC ADC (Analog to Digital Converter) la b chuyn i tin hiu t tng t sang s. PIC16F877A co 8 ngo vao analog (RA4:RA0 va RE2:RE0). Hiu in th chun VREF co th c la chon la VDD, VSS hay hiu in th chun c xac lp trn hai chn RA2 va RA3. Kt qua chuyn i tin hiu t tng t sang s la 10 bit s tng ng va c lu trong hai thanh ghi ADRESH:ADRESL. Khi khng s dung b chuyn i ADC cac thanh ghi nay co th c s dung nh cac thanh ghi thng thng khac. Khi qua trinh chuyn i hoan tt, kt qua se c lu vao hai thanh ghi ADRESH : ADRESL, bit ADCON0<2> c xoa v 0 va c ngt ADIF c set. Quy trinh chuyn i tin hiu t tng t sang s bao gm cac bc sau: Thit lp cac thng s cho b chuyn i ADC:

Chon ngo vao analog, chon in ap mu ( da trn cac thng s cua thanh ghi ADCON1). Chon knh chuyn i AD ( thanh ghi ADCON0). Chon xung clock cho knh chuyn i AD ( thanh ghi ADCON0). Cho phep b chuyn i AD hoat ng (thanh ghi ADCON0). - Thit lp cac c ngt cho b AD: Clear bit ADIF. Set bit ADIE. 1 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A Set bit PEIE. Set bit GIE

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- i cho ti khi qua trinh ly mu hoan tt.

-Bt u qua trinh chuyn i ( set bit GO / DONE ).

- i cho ti khi qua trinh chuyn i hoan tt bng cach: Kim tra bit GO / DONE , nu GO / DONE =0 thi qua trinh chuyn i hoan tt. Kim tra c ngt.
-oc kt qua chuyn i va xoa c ngt, set bit GO / DONE ( nu cn tip tuc

chuyn i). - Tip tuc thc hin cac bc 1 va 2 cho cac qua trinh chuyn i tip theo [3].

Hinh 2.18 S khi b chuyn i ADC 2 By: Trng Vn Dng K44DVT02

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Cac thanh ghi lin quan n b chuyn i ADC bao gm [3]: INTCON ( ia chi ch 0Bh, 8Bh, 10Bh, 18Bh): cho phep cac ngt cac bit GIE, PEIE PIR1 ( ia chi 0Ch): cha c ngt AD ( ADIF). PIE1 ( ia chi 8Ch): cha bit iu khin AD( ADIE). ADRESH ( ia chi 1Eh) va ADRESL ( ia chi 9Eh): cac thanh ghi cha kt qua chuyn i AD. ADCON0 ( iac chi 1Fh) va ADCON1 ( ia chi 9Fh): xac lp cac thng s cua b chuyn i AD. PORTA ( ia chi 05h) va TRISA ( ia chi 85h): lin qun n cac ngo vao analog PORTA. PORTE ( ia chi 09h) va TRISE ( iac hi 89h): lin quan n cac ngo vao analog PORTE. 2.2.9 TRUYN THNG NI TIP 2.2.9.1 USART USART ( Universal Synchronous Asynchronous Receiver Transmitter) l mt trong hai chun giao tip. USART cn c gi l giao din giao tip ni tip ni tip SCI (Serial Communication Interface). C th s dng giao din ny cho cc giao tip vi thit b ngoi vi, vi cc vi iu khin khc hay vi my tnh. Cc dng ca giao din ngoi vi bao gm: - Bt ng b (Asynchronous) - ng b _ Master mode - ng b _ Slave mode Hai pin dng cho giao din ny l RC6/TX/CK v RV7/RX/DT, trong RC6/TS/CK dng truyn xung clock (baud rate) v RC7/RX/DT dng truyn data. Trong trng hp ny ta phi set bit TRISC <7:6> v SPEN (RCSTA<7> cho php giao din USART.

2 By: Trng Vn Dng K44DVT02

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Pic16F877A c tch hp sn b to tc baud BRG ( Baud Rate Genetator) 8 bit dng cho giao din USART. BRG thc cht l mt b m c th s dng cho c hai dng ng b v bt ng b v c iu khin bi thanh ghi PSBRG. dng bt ng b, BRG cn c iu khin bi bit BRGH (TXSTA<2>). dng ng b tc ng ca bit BRGH c b qua. Tc baud do BRG to ra c tnh theo cng thc sau:

Trong X l gi tr ca thanh ghi RSBRG ( X l s nguyn v 0<X<255) Cc thanh ghi lin quan n BRG bao gm: - TXSTA ( a ch 98h): chn ch ng b hay bt ng b ( bit SYNC) v chn mc tc baud (bit BRGH).
- RCSTA (a ch 18h): cho php hot ng cng ni tip ( bit SPEN).

- RSBRG ( a ch 99h): quyt nh tc baud.

2.2.9.1.1 USART Bt ng B ch ny USART hot ng theo chun NRZ (None-Return-to-Zero), ngha l cc bit truyn i s bao gm 1 bit start, 8 hay 9 bit d liu ( thng thng l 8 bit ) v 1 bit stop. Bit LSB s c truyn i trc. Cc khi truyn v nhn data c lp vi nhau s dng chung tn s tng ng vi tc baud cho qu trnh truyn d liu ( tc baud gp 16 hay 64 ln tc dch d liu ty theo gi tr ca bit BRGH), v m bo tnh hiu qu ca d liu th hai khi truyn v nhn phi dng chung mt nh dng d liu. a. Truyn D Liu Qua Chun Giao Tip USART Bt ng B Thnh phn quan trng nht ca khi truyn d liu l thanh ghi dch d liu TSR ( Transmit Shift Register). Thanh ghi TSR s ly d liu t thanh ghi m dng cho qu trnh truyn d liu TXREG. D liu cn truyn phi c a trc 2 By: Trng Vn Dng K44DVT02

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vo thanh ghi TXREG. Ngay sau khi bit Stop ca d liu cn truyn trc c truyn xong, d liu t thanh ghi TXREG s c a vo thanh ghi TSR, thanh ghi TXREG b rng, ngt xy ra v c hiu TXIF ( PIR1<4>) c set. Ngt ny c iu khin bi bit TXIE (PIE1<4>). C hiu TXIF vn c set bt chp trng thi ca bit TXIE hay tc ng ca chng trnh ( khng th xa TXIF bng chng trnh ) m ch reset v 0 khi c d liu mi c a vo thanh ghi TXREG.

Hnh 1.19 S khi ca khi truyn d liu USART Trong khi c hiu TXIF ng vai tr ch th trng thi thanh ghi TXREG th c hiu TRMT ( TXSTA<1>) c nhim v th hin trng thi thanh ghi TSR. Khi thanh ghi TSR rng, bit TRMT s c set. Bit ny ch c v khng c ngt no c gn vi trng thi ca n. Mt im cn ch na l thanh ghi TSR khng c trong b nh d liu v ch c iu khin bi CPU. Khi truyn d liu c cho php hot ng khi bit TXEN (TXSTA<5>) c set. Qu trnh truyn d liu ch thc s bt u khi c d liu trong thanh ghi TXREG v xung truyn baud c to ra. Khi khi truyn d liu c khi ng ln u tin, thanh ghi TSR rng. Ti thi im , d liu a vo thanh ghi TXREG ngay lp tc c load vo thanh ghi TSR v thanh ghi TXREG b rng. Lc ny ta c th hnh thnh mt chui d liu lin tc cho qu trnh truyn d liu. Trong qu trnh truyn d liu nu bit TXEN b set v 0, qu trnh truyn kt thc, khi truyn d liu c reset v pin RC6/TX/CK chuyn n trng thi highimpedance.

2 By: Trng Vn Dng K44DVT02

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Trong trng hp d liu cn truyn l 9 bit, bit TX9 ( TXSTA<6>) c set v bit d liu th 9 s c lu trong bit TX9D (TXSTa<0>). Nn ghi bit d liu th 9 vo trc, v khi ghi 8 bit d liu vo thanh ghi TXREG trc c th xy ra trng hp ni dung thanh ghi TXREG s c load vo thanh ghi TSG trc, nh vy d liu truyn i s b sai khc so vi yu cu. Tm li, truyn d liu theo giao din USART bt ng b, ta cn thc hin tun t cc bc sau: - To xung truyn baud bng cch a cc gi tr cn thit vo thanh ghi RSBRG v bit iu khin mc tc baud BRGH. - Cho php cng giao din ni tip ni tip bt ng b bng cch clear bit SYNC v set bit PSEN. - Set bit TXIE nu cn s dng ngt truyn. - Set bit TX9 nu nh dng d liu cn truyn l 9 bit. - Set bit TXEN cho php truyn d liu ( lc ny bit TXIF cng c set ) - Nu nh dng d liu l 9 bit, a d liu th 9 vo bit TX9D. - a 8 bit d liu cn truyn vo thanh ghi TXREG. - Nu s dng ngt truyn, cn kim tra li cc bit GIE v PEIE ( thanh ghi INTCON ). Cc thanh ghi lin quan n qu trnh truyn d liu bng giao din USART bt ng b: - Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cho php tt c cc ngt. - Thanh ghi PIR1 ( a ch 0Ch): cha c hiu TXIF. - Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt truyn TXIE. - Thanh ghi RCSTA ( a ch 18h): cha bit cho php cng truyn d liu ( hai pin RC6/TX/CK v RV7/RX/DT. - Thanh ghi TXREG ( a ch 19h): thanh ghi cha d liu cn truyn. - Thanh ghi TXSTA ( a ch 98h): xc lp cc thng s cho giao din. 2 By: Trng Vn Dng K44DVT02

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- Thanh ghi SPBRG ( a ch 99h): quyt nh tc baud. b. Nhn D Liu Qua Chun Giao Tip USART Bt ng B D liu c a vo chn RC7/RX/DT s kch hot khi phc hi d liu. Khi phc hi d liu thc cht l mt b dch d liu tc cao v c tn s hot ng gp 16 ln hoc bng 64 ln tn s baud. Trong khi tc dch ca thanh ghi nhn d liu s bng vi tn s baud hoc tn s ca oscillator.

Hnh 2.20 S khi ca khi nhn d liu USART. Bit iu khin cho php khi nhn d liu l bit RCEN ( RCSTA<4>). Thnh phn quan trng nht ca khi nhn d liu l thanh ghi nhn d liu RSR ( Receive Shift Register). Sau khi nhn din bit Stop ca d liu truyn ti, d liu nhn c trong thanh ghi RSR s c a vo thanh ghi RCGER, sau c hiu RCIF (PIR1<5>) s c set v ngt nhn c kch hot. Ngt ny c iu khin bi bit RCIE ( PIE1<5>). Bit c hiu RCIF l bit ch c v khng th c tc ng bi chng trnh. RCIF ch reset v 0 khi d liu nhn vo thanh ghi RCREG c c v khi thanh ghi RCREG rng. Thanh ghi RCREG l thanh ghi c b m kp ( double-buffered-register) v hot ng theo c ch FIFO (Fist In First Out) cho php nhn 2 byte v byte th 3 tip tc c a vo thanh ghi RSR. Nu sau khi nhn c bit Stop ca byte d liu th 3 m thanhg ghi RCREG vn cn y, c hiu bo trn d liu ( Overrun Error bit) OERR( RCSTA<1>) s c set, d liu trong thanh ghi RSR s b mt i v trong qu trnh a d liu t thanh ghi 2 By: Trng Vn Dng K44DVT02

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RSR vo thanh ghi RCREG s b gin on. Trong trng hp ny cn ly ht d liu thanh ghi RSREG vo trc khi tip tc nhn byte d liu tip theo. Bit OERR phi c xa bng phn mm v thc hin bng cch clear bit RCEN ri set li. Bit FERR ( RCSTA<2>) s c set khi pht hin bit Stop ca d liu nhn vo. Bit d liu th 9 s c a vo bit RX9D ( RCSTA<0>). Khi c d liu t thanh ghi RCREG, hai bit FERR RX9D s nhn cc gi tr mi. Do cn c d liu t thanh ghi RCSTA trc khii c d liu t thanhg ghi RCREG trnh b mt d liu. Tm li, khi s dng giao din nhn d liu USART bt ng b cn tin hnh tun t cc bc sau: 1. Thit lp tc baud ( a gi tr thch hp vo thanh ghi SPBRG v bit BRGH. 2. Cho php cng giao tip USART bt ng b ( clear bit SYNC v set bit SPEN). 3. Nu cn s dng ngt nhn d liu, set bit RCIE. 4. 5. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. Cho php nhn d liu bng cch set bit CREN.

6. Sau kkhi d liu c nhn, bit RCIF s c set v ngt c kch hot ( nu bit RCIE c set). 7. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu trnh nhn d liu c b li khng. 8. 9. 10. c 8 bit d liu t thanh ghi RCREG. Nu qu trnh truyn nhn c li xy ra, xa li bng cch xa bit CREN. Nu s dng ngt nhn cn set bit GIE v PEIE ( thanh ghi INTCON).

Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART bt ng b: - Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cha cc bit cho php ton b cc ngt ( bit GIER v PEIE). 2 By: Trng Vn Dng K44DVT02

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- Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. - Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt RCIE. Thanh ghi RCSTA ( a ch 18h): xc nh cc trng thi trong qu trnh nhn d liu. - Thanh ghi RCREG ( a ch 1Ah): cha d liu nhn c. - Thanh ghi TXSTA ( a ch 98h): cha cc bit iu khin SYNC v BRGH. - Thanh ghi SPBRG ( a ch 99h): iu khin tc baud. 2.2.9.1.2 USART ng B Giao din USART ng b c kch hot bng cch set bit SYNC. Cng giao tip ni tip vn l hai chn RC6/TX/CK v RV7/RX/DT v c cho php bng cch set SPEN. USART cho php hai ch truyn nhn d liu l Master mode v Slave mode. Master mode c kch hot bng cch set bit CSRC ( TXSTA<7> ), Slave mode c kch hot bng cch clear bit CSRC. im khc bit duy nht gia hai ch ny l Master mode s ly xung clock ng b t b to xung baud BRG cn Slave mode ly xung clock ng b t bn ngoi qua chn RC6/TX/CK. iu ny cho php Slave mode hot ngay c khi vi iu khin ang ch sleep. a. TRUYN D LIU QUA CHUN GIAO TIP USART NG B MASTER MODE Tng t nh giao din USART bt ng b, thnh phn quan trng nht ca khi truyn d liu l thanh ghi dch TSR (Transmit Shift Register). Thanh ghi ny ch c iu khin bi CPU. D liu a vo thanh ghi TSR c cha trong thanh ghi TXREG. C hiu ca khi truyn d liu l bit TXIF ( ch th trng thi thanh ghi TXREG), c hiu ny c gn vi mt ngt v bit iu khin ngt ny l TXIE. C hiu ch th trng thi thanh ghi TSR l bit TRMT. Bit TXEN cho php hay khng cho php truyn d liu Cc bc cn tin hnh khi truyn d liu qua giao tip USART ng b Master mode: 1. To xung truyn baud bng cch ua cc gi tr cn thit vo thanh ghi RSBRG v bit iu khin mc tc baud BRGH. 2 By: Trng Vn Dng K44DVT02

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2. Cho php cng giao din ni tip ni tip ng b bng cch set bit SYNC, PSEN v CSRC. 3. Set bit TXIE nu cn s dng ngt truyn. 4. Set bit TX9 nu nh dng d liu cn truyn l 9 bit. 5. Set bit TXEN cho php truyn d liu. 6. Nu nh dng d liu l 9 bit, a bt d liu th 9 vo bit TX9D. 7. a 8 bit d liu cn truyn vo thanh ghi TXREG. 8. Nu s dng ngt truyn, cn kim tra li cc bit GIE v PEIE ( thanh ghi INTCON) Cc thanh ghi lin quan n qu trnh truyn d liu bng giao din USART ng b Master mode. Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cho php tt c cc ngt. Thanh ghi PIR1 ( a ch 0Ch); cha c hiu TXIF. Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt truyn TXIE.

- Thanh ghi RCSTA ( a ch 18h): cha bit cho php cng truyn d liu ( hai pin RC6/TX/CK v RC7/RX/DT). Thanh ghi TXREG ( a ch 19h): thanh ghi cha d liu cn truyn . Thanh ghi TXSTA ( a ch 98h): xc lp cc thng s cho giao din. Thanh ghi SPBRG ( a ch 99h): quyt nh tc baud.

b. NHN D LIU QUA CHUN GIAO TIP USART NG B MASTER MODE Cu trc khi nhn d liu l khng i so vi giao din bt ng b, k c cc c hiu, ngt nhn v cc thao tc trn cc thnh phn . im khc bit duy nht l giao din ny cho php hai ch nhn d liu, l ch nhn 1 word d liu ( set bit SCEN) hay nhn mt chui d liu ( Set bit CREN) cho ti khi ta cleaar bit CREN. Nu c hai bit u c set, bit iu khin CREN s c u tin.

2 By: Trng Vn Dng K44DVT02

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Cc bc cn tin hnh khi nhn d liu bng giao din USART ng b Master mode: 1. Thit lp tc baud ( a gi tr thch hp vo thanh ghi SPBRG v bit BRGH). 2. Cho php cng giao tip USART bt ng b ( set bit SYNC,SPEN va CSRC). 3. Clear bit CREN v SREN. 4. Nu cn s dng ngt nhn d liu, set bit RCIE. 5. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 6. Nu ch nhn 1 word d liu, set bit SREN, nu nhn 1 chui word d liu, set bit CREN. 7. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot ( nu bit RCIE c set) 8. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu trinh nhn d liu c b li khng. 9. c 8 bit d liu t thanh ghi RCREG. 10. Nu qu trinh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 11. Nu s dng ngt nhn cn set bit GIE v PEIE ( thanh ghi INTCON) Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART ng b Master mode: - Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cha cc bit cho php ton b cc ngt ( bit GIER v PEIE). - Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. - Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt RCIE. - Thanh ghi RCSTA ( a ch 18h): xc nh cc trng thi trong qu trnh nhn d liu. - Thanh ghi RCREG ( a ch 1Ah): cha d liu nhn c. 2 By: Trng Vn Dng K44DVT02

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- Thanh ghi TXSTA ( a ch 98h): cha cc bit iu khin SYNC v BRGH. - Thanh ghi SPBRG ( a ch 99h): iu khin tc baud. c. TRUYN D LIU QUA CHUN GIAO TIP USART NG B SLAVE MODE Qu trnh ny khng c s khc bit so vi Master mode khi vi iu khin hot ng ch bnh thng. Tuy nhin khi vi iu khin ang trng thi sleep, s khc bit c th hin r rng. Nu c hai word d liu c a vo thanh ghi TXREG trc khi lnh sleep c thc thi th qu trinh sau s xy ra: 1. Word d liu u tin s ngay lp tc c a vo thanh ghi TSR truyn i 2. Word d liu th 2 vn nm trong thanh ghi TXREG. 3. C hiu TXIF s khng c set. 4. Sau khi word d liu u tin dch khi thanh ghi TSR, thanh ghi TXREG tip tc truyn word th hai vo thanh ghi TSR v c hiu TXIF c set. 5. Nu ngt truyn c cho php hot ng, ngt ny s nh thc vi iu khin v nu ton b cc ngt c cho php hot ng, b m chng trnh s ch ti a ch cha chng trnh ngt ( 0004h). Cc bc cn tin hnh khi truyn d liu bng giao din USART ng b Slave mode: 1. Set bit SYNC, SPEN v clear bit CSRC. 2. Clear bit CREN v SREN. 3. Nu cn s dng ngt, set bit TXIE. 4. Nu nh dng d liu l 9 bit, set bit TX9. 5. Set bit TXEN. 6. a bit d liu th 9 vo bit TX9D trc ( nu nh dng d liu l 9 bit). 7. a 8 bit d liu vo thanh ghi TXREG. 8. Nu ngt truyn c s dng, set bit GIE v PEIE ( thanh ghi INTCON). 3 By: Trng Vn Dng K44DVT02

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Cc thanh ghi lin quan n qu trnh truyn d liu bng giao din USART ng b Slave mode: Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cho php tt c cc ngt. Thanh ghi PIR1 ( a ch 0Ch); cha c hiu TXIF. Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt truyn TXIE.

- Thanh ghi RCSTA ( a ch 18h): cha bit cho php cng truyn d liu ( hai pin RC6/TX/CK v RC7/RX/DT). Thanh ghi TXREG ( a ch 19h): thanh ghi cha d liu cn truyn . Thanh ghi TXSTA ( a ch 98h): xc lp cc thng s cho giao din. Thanh ghi SPBRG ( a ch 99h): quyt nh tc baud.

d. NHN D LIU QUA CHUN GIAO TIP USART NG B SLAVE MODE S khc bit ca Slave mode so vi Master mode ch th hin r rng khi vi iu khin hot ng ch sleep. Ngoi ra ch Slave mode khng quan tm ti bit SREN. Khi bit CREN ( cho php nhn chui d liu ) c set trc khi lnh sleep c thc thi, mt word d liu vn c tip tc nhn, sau khi nhn xong bit thanh ghi TSR s chuyn d liu vo thanh ghi RCREG v bit RCIF c set. Nu bit RCIE ( cho php ngt nhn) c set trc , ngt s c thc thi v vi iu khin c nh thc, b m chng trnh s ch n a ch 0004h v chng trinh ngt s c thc thi. Cc bc cn tin hnh khi nhn d liu bng giao din USART ng b Slave mode: 1. Cho php cng giao tip USART ng b (set bit SYNC, SPEN clear bit CSRC). 2. Nu cn s dng ngt nhn d liu, set bit RCIE. 3. Nu d liu truyn nhn c nh dng l 9 bit, set bit RX9. 4. Set bit CREN cho php qu trnh nhn d liu bt u. 3 By: Trng Vn Dng K44DVT02

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5. Sau khi d liu c nhn, bit RCIF s c set v ngt c kch hot ( nu bit RCIE c set). 6. c gi tr thanh ghi RCSTA c bit d liu th 9 v kim tra xem qu trnh nhn d liu c b li khng. 7. c 8 bit d liu t thanh ghi RCREG. 8. Nu qu trinh truyn nhn c li xy ra, xa li bng cch xa bit CREN. 9. Nu s dng ngt nhn cn set bit GIE v PEIE ( thanh ghi INTCON ). Cc thanh ghi lin quan n qu trnh nhn d liu bng giao din USART ng b Slave mode: - Thanh ghi INTCON ( a ch 0Bh,8Bh,10Bh,18Bh): cha cc bit cho php ton b cc ngt ( bit GIER v PEIE). - Thanh ghi PIR1 (a ch 0Ch): cha c hiu RCIE. - Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt RCIE. - Thanh ghi RCSTA ( a ch 18h): xc nh cc trng thi trong qu trnh nhn d liu. - Thanh ghi RCREG ( a ch 1Ah): cha d liu nhn c. - Thanh ghi TXSTA ( a ch 98h): cha cc bit iu khin SYNC v BRGH. - Thanh ghi SPBRG ( a ch 99h): iu khin tc baud.

2.2.9.2 MSSP MSSP ( Master Synchronous Serial Port ) l giao din ng b ni tip dng giao tip vi cc thit b ngoi vi ( EEPROM, ghi dch, chuyn i ADC,) hay cc vi iu khin khc. MSSP c th hot ng di hai dng giao tip:

3 By: Trng Vn Dng K44DVT02

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I2C: Inter- Intergrated Circuit SPI: Serial Pheripheral Interface Cc thanh ghi iu khin giao din chun giao tip ny bao gm thanh

ghi trng thi SSPSTAT v hai thanh ghi iu khin S khi MSSP ( giao Ty SPI) Hnh 2.21 SSPSON v SSPSON2. din theo chun giao tip c s dng ( SPI hay I2c) m chc nng cc thanh ghi ny th hin khc nhau. 2.2.9.2.1 SPI Chun giao tip SPI cho php truyn nhn ng b. Ta cn s dng 4 pin cho chun giao tip ny : RC5/SDO: ng ra d liu dng ni tip ( Serial Data Output). RC4/SDI/SDA: ng vo d liu dng ni tip ( Serial Data Input). RC3/SCK/SCL: xung ng b ni tip ( Serial Clock).

- RA5/AN4/SS/C2OUT: chn i tng giao tip ( Serial Select) khi giao tip ch Slave mode. Cc thanh ghi lin quan n MSSP khi hot ng chun giao tip SPI bao gm: Thanh ghi iu khin SSPCON, thanh ghi ny cho php c v ghi Thanh ghi trng thi SSPSTAT, thanh ghi ny ch cho php c v ghi 2 bit trn, 6 bit cn li ch cho php c. Thanh ghi ng vai tr l buffer truyn nhn SSPBUF, d liu truyn i hoc nhn c s c a vo thanh ghi ny. SSPBUF khng c cu trc m hai lp ( doubled-buffer), do d liu ghi vo thanh ghi SSPBUF s lp tc c ghi vo thanh ghi SSPSR. Thanh ghi dich d liu SSPSR dng dch d liu vo hoc ra. Khi 1 byte d liu c nhn hon chnh, d liu s t thanh ghi SSPSR chuyn qua thanh ghi SSPBUF v c hiu c set, ng thi ngt s xy ra. 2.2.9.3 I2C

3 By: Trng Vn Dng K44DVT02

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y l mt dng khc ca MSSP. Chun giao tip I2C cng c hai ch Master, Slave v cng c kt ni vi ngt. I2C s s dng 2 pin truyn nhn d liu: RC3/SCK/SCL: chn truyn dn xung clock RC4/SDI/SDA: chn truyn dn d liu

Cc khi c bn trong s khi ca I2C khng c nhiu khc bit so vi SPI. Tuy nhin I2C cn c thm khi pht hin bit Start v bit Stop ca d liu * Start ang Stop bit detect ) v khi xc nh a ch ( Match detect). Cc thanh ghi lin quan n I2C bao gm:
- Thanh ghi SSPCON v SSPCON2: iu

khin MSSP. - Thanh ghi SSPSTAT: thanh ghi cha cc trng thi hot ng ca MSSP. - Thanh ghi SSPBUF: buffer truyn nhn ni tip. - Thanh ghi SSPSR: thanh ghi dch dng truyn nhn d liu. - Thanh ghi SSPADD: thanh ghi cha a ch ca giao din MSSP. Cc thanh ghi SSPCON, SSPCON2 cho php c v ghi. Thanh ghi SSPSTAT ch cho php c v ghi 2 bt u,6 bit cn li ch cho php c. Thanh ghi SSPBUF cha d liu s c truyn i hoc nhn c v ng vai tr nh mt thanh ghi m cho thanh ghi dch d liu SSPSR. Thanh ghi SSPADD cha a ch ca thit b ngoi vi cn truy xut d liu ca I2c khi hot ng Slave mode. Khi hot ng Master mode, thanh ghi SSPADD cha gi tr to ra tc baud cho xung clock dng truyn nhn d liu. 3 By: Trng Vn Dng K44DVT02

Hnh 2.22 S khi MSSP (I2C Slave Mode)

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Trong qu trnh nhn d liu, sau khi nhn c 1 byte d liu hon chnh, thanh ghi SSPSR s chuyn d liu vo thanh ghi SSPBUF. Thanh ghi SSPSR khng c v ghi c, qu trinh truy xut thanh ghi ny phait thong qua thanh ghi SSPBUF. Trong qu trinh truyn d liu, d liu cn truyn khi c a vo thanh ghi SSPBUF cng s ng thi a vo thanh ghi SSPSR. I2C c nhiu ch hot ng v c iu khin bi cc bit SSPCON <3:0>, bao gm:
- I2C Master mode, xung clock = fosc / 4* (SSPADD+1).

- I2C Slave mode, 7 bit a ch - I2C Slave mode, 10 bit a ch - I2C Slave mode, 7 bit a ch, cho php ngt khi pht hin bit Start v bit Stop. - I2C Slave mode, 10 bit a ch, cho php ngt khi pht hin bit Start v bit Stop. - I2c Firmware Control Master mode. a ch truyn i s bao gm cc bit a ch v 1 bt R/W xc nh thao tc ( c hay ghi d liu) vi i tng cn truy xut d liu. Khi la chn giao din I2C va khi set bit SSPEN, cc pin SCL v SDA s trng thi cc thu h. Do trong trng hp cn thit ta phi s dng in tr ko ln bn ngoi vi iu khin, bn cnh cn n nh cc gi tr ph hp cho cc bit TRISC<4:3>( bit iu khin xut nhp cc chn SCL v SDA) [3]. 2.2.9 CNG GIAO TIP SONG SONG PSP ( PARALLEL SLAVE PORT) Ngoai cac cng ni tip va cac giao din ni tip c trinh bay phn trn, vi iu khin PIC16F877A con c h tr mt cng giao tip sng va chun giao tip song song thng qua PORTD va PORTE. Do cng song song chi hoat ng ch Slave mode nn vi iu khin khi giao tip qua giao din nay se chiu s iu khin cua thit bi ngoai thng qua cac pin cua PORTE, trong khi d liu se c oc hoc ghi theo dang bt ng b thng qua 8 pin cua PORTD.

3 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

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Bit iu khin PSP la PSPMODE ( TRISE<4>). PSPMODE c set khi thit lp chc nng cac pin cua PORTE la cac pin cho phep oc d liu RD ( RE 0 / RD / AN 5 ) cho phep ghi d liu WR ( RE1 / WR / AN 6 ) va cac pin chon vi iu khin CS (
RE 2 / CS / AN 7 ) phuc vu cho vic truyn nhn d liu song song thng qua bus d

liu 8 bit cua PORTD. PORTD luc nay ong vai tro la thanh ghi cht d liu 8 bit, ng thi s tac ng cua thanh ghi TRISD cung se bo qua do PORTD luc nay chiu s iu khin cua thit bi ngoai. PORTE vn chiu s tac ng cua thanh ghi TRISE, do o cn xac lp trang thai cac pin PORTE la input bng cach set cac bit TRISE<2:0>. Ngoai ra cn a gia tri thich hp cho cac bit PCFG3:PCFG0 ( thanh ghi ADCON1<3:0>) n inh cac pin cua PORTE la cac pin I/O dang digital ( PORTE con la cac pin chc nng cua khi ADC) [3]. Khi cac pin CS va WR cung mc thp d liu t bn ngoai se c ghi ln PORTD. Khi mt trong hai pin c chuyn ln mc logic cao, c d liu trong Buffer a y BIF (TRISE<7>) c set va c ngt PSPIF (PIR1<7>) c set bao hiu kt thuc ghi d liu. Bit BIF chi c xoa v 0 khi d liu va nhn c PORTD c oc vao. Bit bao hiu d liu trong buffer bi tran IBOV (TRISE<5>) se c set khi vi iu khin nhn tip d liu tip theo trong khi cha oc vao d liu a nhn c trc o [3]. Cn chu y la ngt SSPIF c diu khin bi bit PSPIE ( PIE<7>) va c xoa bng chng trinh. Cc thanh ghi lin quan n PSP bao gm: Thanh ghi PORTD ( a ch 08h): cha d liu cn c hoc ghi. Thanh ghi PORTE ( a ch 09h): cha gi tr c pin PORTE. Thanh ghi TRISE ( a ch 89h): cha cc bit iu khin PORTE v PSP. Thanh ghi PIR1( a ch 0Ch): cha c ngt PSPIF. 3 By: Trng Vn Dng K44DVT02

Hnh 2.23 S khi cua PORTD va PORTE khi hoat ng ch PSP Slave mode

Vi iu khin PIC16F877A

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Thanh ghi PIE1 ( a ch 8Ch): cha bit cho php ngt PSP. Thanh ghi ADCON1 ( a ch 9Fh): iu khin khi ADC ti PORTE.
2.2.10 NGT (INTERRUPT)

PIC16F877A c n 15 ngun to ra hot ng ngt c iu khin bi thanh ghi INTCON (GIE). Bn cnh mi ngt cn c mt bit iu khin v c ngt ring. Cc c ngt vn c set bnh thng khi tha mn iu kin ngt xy ra bt chp trng thi ca bit GIE, tuy nhin hot ng ngt vn ph thuc vo bit GIE v cc bit iu khin khc. Bit iu khin ngt RB0/INT v TMR0 nm trong thanh ghi INTCON, thanh ghi ny cn cha bit cho php ngt ngoi vi PEIE. Bit iu khin cc ngt nm trong thanh ghi PIE1vaf PIE2. C ngt ca cc ngt nm trong thanh ghi PIR1 v PIR2. i vi cc ngt ngoi vi nh ngt t chn INT hay ngt t s thay i trng thi cc pin ca PORTB (PORTB Interrupt on change), vic xc nh ngt no xy ra cn ba hoc bn chu k lnh ty thuc vo thi im xy ra ngt. Cn ch rng trong qu trnh thc thi ngt ch c gi tr ca b m chng trnh c ct vo Stack, trong khi mt s thanh ghi quan trng s khng c ct v c th b thay i gi tr trong qua trnh thc thi chng trnh ngt. iu ny nn c x l bng chng trnh trnh hin tng trn xy ra [3].

3 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

i hc k thut cng nghipTN

Hnh 2.24 S logic ca tt c cc ngt trong vi iu khin PIC16F877A Ngt INT Ngt ny da trn s thay i trng thi ca pin RB0/INT. Cnh tc ng gy ra ngt c th la cnh ln hay cnh xung v c iu khin bi bit INTEDG ( thanh ghi OPTION_REG <6>). Khi c tc ng thch hp xut hin ti pin RB0/INT, c ngt INTF c set bt chp trng thi cc bit iu khin GIE v PEIE. Ngt ny c kh nng nh thc vi iu khin ch Sleep nu bit cho php ngt c set trc khi lnh Sleep c thc thi. Ngt do s thay i trng thi cc pin trong PORTB Cc pin PORTB<7:4> c dng cho ngt ny v iu khin bi bit RBIE ( thanh ghi INTCON<4>). C ngt ca ngt ny l bit RBIF ( INTCON<0>) [3]. 2.2.11 CC C TNH CA OSCILLATOR PIC16F877A c kh nng s dng mt trong bn loi Oscillator, l: LP: Low Power Crystal. XT (Xtal): thch anh bnh thng. HS: High Speed Crystal. 3 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

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RC: Resister/Capacitor dao ng do mch RC to ra. i vi cc loi oscillator LP,HS,XT oscillator c gn vo vi iu khin thng qua cc pin OSC1/CLKI v OSC2/ CLKO. i vi cc ng dng khng cn cc loi oscillator tc cao ta c th dng mch dao ng RC lm ngun cung cp xung hot ng cho cc vi iu khin. Tn s to ra ph thuc vo cc gi tr in p, gi tr in tr v t in. Bn cnh l s nh hng ca cc yu t nh nhit , cht lng ca cc linh kin. Hnh 2.25 RC Oscillator Cc linh kin s dng trong mch RC oscillator phi m bo cc gi tr sau: 3K< REXT<100K. CEXT>20pF. 2.2.12 CC CH RESET C nhiu ch reset vi iu khin, bao gm: Power-on Reset POR (Reset khi cp ngun hot ng cho vi iu khin).
MCLR MCLR

reset trong qu trnh hot ng. t ch sleep.

WDT reset ( reset do khi WDT to ra trong qu trnh hot ng). WDT wake up t ch Sleep. Brown out reset ( BOR). vi iu khin hot ng c t khi cp ngun cn tri qua cc bc sau [3]: - POR tc ng.
- PWRT ( nu c cho php hot ng ) to ra khong thi gian Delay TPWRT

n nh ngun cung cp.

3 By: Trng Vn Dng K44DVT02

Vi iu khin PIC16F877A

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- OST ( nu c cho php ) to ra khong thi gian Delay bng 1024 chu k xung ca Oscillator n nh tn s ca Oscillator. - n thi im ny vi iu khin mi bt u hot ng bnh thng. Thanh ghi iu khin v ch th trng thi ngun cung cp cho vi iu khin l thanh ghi PCON.

Hnh 2.26 S cc ch reset ca PIC16F877A

4 By: Trng Vn Dng K44DVT02