3. PLC Siemens S7-300 3.1.

Gii thiu PLC S7-300 PLC S7-300 l sn phm PLC mnh, tc x l cao, kh nng qun l b nh tt, kt ni mng cng nghip. V tnh nng, S7- 300 c nhiu ci tin so vi S7-200. Dung lng b nh ln hn, tc truy nhp nhanh hn. Cc module c ni vi nhau qua khe cm. Ngn ng lp trnh a dng phong ph ngoi 3 ngn ng chnh thng,cn c cc ngn ng ha(mng SFC), ngn ng bc cao Kh nng qun l cc module m rng ln hn. Thc hin cc php ton logic v biu thc logic vi ngn ng STL c ci tin cho ph hp vi cch vit thng thng hn. S7- 300 cn s dng 2 thanh ghi dc bit lm con tr AR1v AR2, s dng hai thanh ghi trung gian ACCU1 v ACCU2 lu kt qu khi lm vic vi cc lnh byte, word, double word. T chc chng trnh trong S7- 300 rng hn v cht ch hn, vi cc khi chng trnh v d liu c th.

Mt s thng s k thut ca S7- 300 ca CPU 3xx CPU 312 CPU 313 IMF Vng 6kB nh thc thi Vng 20Kb, nh Ram, chng Eeprom trnh ng dng Kch 32 byte thc b m 12kB CPU314 24kB CPU 314 CPU IMF 315 24kB 48kB CPU 315 2DP

20Kb Ram

40Kb, Ram

40Kb, Ram, Eeprom

20Kb Ram

128 byte

128 byte

128 byte

128 byte

Cc module m rng ca S7- 300 CPU 3xx Ngun cp(PS) Tn hiu(SM) Ghp (IM) 2A DI 5A DO 10A AI (2, 4, 8, 15) Vo xoay chiu, ra 24 VDC AO(2, 4) AI/AO(4/2)

(4, 8, 16, 32) (8, 6, 32) ni IM 360 IM365

Chc nng(FM) Truyn thng(CP)

L cc module iu khin chuyn dng (ng c bc, ng c senvo, PID, fuzzy logic. ASI Profibus Industrial Ethemet

Hnh 3.1 S cu trc S7-300 3.2 Module CPU Cc module CPU khc nhau theo hnh dng chc nng, vn tc x l lnh. Loi 312IFM, 314IFM khng c th nh. Loi 312IFM, 313 khng c pin nui. Loi 315-2DP, 3162DP, 318-2 c cng truyn thng DP. Cc n bo c ngha sau: SF (): li phn cng hay mm. BATF (): li pin nui. DC5V (l cy): ngun 5V bnh thng. FRCE (vng ): force request tch cc.

RUN (l cy): CPU mode RUN ; LED chp lc start-up w. 1 Hz; mode HALT w. 0.5 Hz. STOP mode (vng) CPU mode STOP hay HALT hay start-up; LED chp khi memory reset request. BUSF (): li phn cng hay phn mm giao din PROFIBUS.

Hnh 3.2: ngha ca cc cng v n bo hiu trn PLC. Trong kha mode c 4 v tr: RUN-P ch lp trnh v chy. RUN ch chy chng trnh. STOP ngng chy chng trnh. MRES reset b nh. Th nh c th c dung lng t 16KB n 4MB, cha chng trnh t PLC chuyn qua v chuyn chng trnh ngc tr li cho CPU.

Pin nui gip nui chng trnh v d liu khi b mt ngun (ti a 1 nm), ngoi ra cn nui ng h thi gian thc. Vi loi CPU khng c pin nui th cng c mt phn vng nh c duy tr. Thng qua cng truyn thng MPI (MultiPoint Interface) c th ni: my tnh lp trnh, mn hnh OP, cc PLC c cng MPI (S7-300, M7-300, S7-400, M7-400, C7-6xx), S7200, vn tc truyn n 187.5kbps (12Mbps vi CPU 318-2, 10.2 kbps vi S7-200 3.3. T chc vng nh v a ch vng nh 3.3.1. T chc vng nh Vng nh cc thanh ghi: Gm cc thanh ghi sau, ACCU1, ACCU2, AR1, AR2, DI(instance), startus reg. Vng nh h thng(system): L vng nh bao gm cc a ch nh I, Q, M, T v C. Vng nh chng trnh ng dng (load): L vng nh lu li ni dng m chng trnh c son ra do ngi lp trnh. Tuy theo CPU, vng nh ny c th m rng ti 512Kb. Vng nh thc thi(work): L vng nh cha cc d liu ang thc thi bi CPU, vng nh ny lin tc b h iu hnh thay i ni dung mi khi np mt khi chng trnh mi.

3.3.2. a ch vng nh B m vo s: I0.0 n I127.7 (128 byte) B m ra s: Q0.0 n Q127.7 (128 byte) Vng nh bt: M0.0 n M255.7 Vng nh timer: T0 n T255 Vng nh counter: C0 n C255 Vng nh khi d liu(share): DIx0.0 n DIx65535.7 Vng nh a phng: L0.0 n 65535.7 Vng nh u vo tng t: PIB65535 Vng nh u ra tng t: PIQ65535

3.4 Truy nhp d liu ti cc vng nh ca S7-300 3.4.1 Truy nhp trc tip DB (khi d liu share) DI(khi d liu instance) Truy cp theo tng bt

Truy cp theo tng byte Truy cp theo tng word Truy cp theo tng double word

3.4.2. Truy cp gin tip thng qua con tr i vi S7-300 ngoi vng b nh M c lm con tr, S7300 cn s dng hai thanh ghi chuyn dng AR1 v AR2 kch thc 32 bt lm con tr.

3.5. Ngn ng lp trnh Ngn ng STL Ngn ng LAD Ngn ng FBD Ngn ng Graph(SFC) Ngn ng Hi-Graph Ngn ng SCL

3.6 Cc kiu d liu S7-300 s dng mt s kiu d liu sau y: BOOL: vi dung lng mt bit v c gi tr l 1 hoc 0 (tc ng hoc sai). y l kiu d liu cho bin hai tr. Byte: gm 8 bit, thng c s dng biu din s nguyn dng t 0 n 255 hoc l m ASSCI ca mt k t. Word: gm 2 byte, c dng biu din s nguyn t 0 n 65535. Int: gm 2 byte, c dng biu din s nguyn t -32768 n +32767. Dint: gm 4 byte, c dng biu din s nguyn t -2147483648 n +2147483647. Real: gm 4 byte, c dng biu din s thc c du phy ng. S5T: bin thi gian c tnh hh/mm/ss/ms. TOD: biu din gi tr thi gian tnh theo gi/pht/giy. Date: biu din gi tr thi gian tnh theo nm/thng/ngy. Char: biu din mt hay nhiu k t (Ti a 4 k t).

3.7 Mt s lnh c bn trong ngn ng lp trnh Ladder cho S7-300 3.7.1 Lnh tip im thng m. + K hiu:
( Address )

Thng s

Kiu DL

Vng nh

M t

< Address >

BOOL

I, Q, M, L, D, T, C

Kim tra bt

+ M t: N ng khi gi tr ca bt c lu tr ti ni quy nh <address> bng 1. Khi tip im ng, trn s hnh thang c dng nng lng chy qua tip im v kt qu ca php logic (RLO) = 1. Ngc li, nu trng thi tn hiu ti ni quy nh <address> bng 0 , th tip im l m. Khi tip im m, dng nng lng khng chy qua tip im v kt qu ca php logic (RLO) = 0. 3.7.2 Lnh tip im thng ng. + K hiu:
(Address )

+ Thng s Kiu DL Vng nh M t

< Address >

BOOL

I, Q, M, L, D, T, C

Kim tra bt

+ M t. N ng khi gi tr ca bt c lu tr ti ni quy nh < address > bng 0. Khi tip im ng, trn s hnh thang c dng NL chy ngang qua tip im v kt qu ca php logic (RLO) = 1.

Ngc li, nu trng thi tn hiu ti ni quy nh < address > bng 1, th tip im s m. Khi tip im m, s khng c dng NL chy qua tip im v kt qu ca php logic (RLO) = 0. 3.7.3 Lnh XOR bit. Chc nng ca php XOR, mt network cn phi c cc tip im thng m v thng ng c to ra nh hin th pha di. + Biu tng.
<address 1> <address 2>

<address 1> <address 2>

Thng s <address 1> <address 2>

Kiu DL BOOL BOOL

Vng nh I, Q, M, L, D, T, C I, Q, M, L, D, T, C

M t Qut bt Qut bt

+ M t XOR ( Bit Exclusive OR ) s to ra mt RLO mang gi tr 1 nu trng thi tn hiu ca hai bt ch nh l khc nhau. 3.7.4 Lnh o ngc. + Biu tng.
NOT

3.7.5 Biu din u ra. + Biu tng.

<address>

+ Thng s Kiu DL Vng nh M t

< Address >

BOOL

I, Q, M, L, D

gn gi tr ti bt

+ M t. N lm vic ging nh mt cun dy trong mt s relay logic. Nu nhng dng in ti cun dy th cc bit ti v tr < address > s c thit lp ln 1. Nu khng c nhng dng in ti cun dy th cc bt ti v tr <address> s c thit lp v 0. u ra ca mt cun dy ch c th t cui cng pha bn phi ca mt bc thang ladder. 3.7.6 Xa gi tr ca cun dy u ra. + Biu tng.
<address>

----(R)
Thng s Kiu DL Vng nh M t

< Address >

BOOL

I, Q, M, L, D, T, C

Xa bt

+ M t. ---(R). N ch thc hin nu trng thi RLO ca cc hin th trc bng 1 (c dng in n cun dy). Nu c dng in n cun dy th ti ni quy nh <address> cc phn t s c xa v 0. Nu khng c dng in n cun dy th cu lnh khng c tc dng v trng thi ca cc phn t ti a ch quy nh s khng thay i. 3.7.7 Thit lp gi tr ca cun dy u ra. + Biu tng.
<address>

----(S)

Thng s

Kiu DL

Vng nh

M t

< Address >

BOOL

I, Q, M, L, D

Thit lp bt

+ M t. ---(S). N ch c thc hin nu trng thi RLO ca cc hin th trc bng 1 (c dng in chy n cun dy). Nu RLO = 1 th ti ni quy nh <address> ca cc phn t s c thit lp ln 1. Cn nu RLO = 0 th lnh khng c tc dng v trng thi hin ti ca cc phn t ti a ch quy nh vn khng thay i. 3.7.8 Lnh pht hin xung sn xung. + Biu tng.
<address1> NEG Q <address2>
M_BIT

Thng s < Address1 > < Address1 >

Kiu DL BOOL BOOL

Vng nh I, Q, M, L, D I, Q, M, L, D

M t Tn hiu qut M_BIT bt nh theo sn, lu gi trng thi trc ca <address1> nh u ra (One shot output)

BOOL

I, Q, M, L, D

+ M t.

NEG so snh trng thi tn hiu ca <address1> vi trng thi tn hiu ca ln qut trc, sau s lu kt qu vo <address2>. Nu trng thi hin ti ca RLO bng 1 v trng thi trc n l 0, th bit RLO s ln 1 sau lnh ny. 3.7.9 Lnh pht hin xung sn ln. + Biu tng.
<address1> POS Q <address2>

+ Thng s < Address1 > < Address1 > Kiu DL BOOL BOOL

M_BIT

Vng nh I, Q, M, L, D I, Q, M, L, D

M t Tn hiu qut M_BIT bt nh theo sn, lu gi trng thi trc ca <address1> nh u ra (One shot output)

BOOL

I, Q, M, L, D

+ M t. POS. So snh trng thi tn hiu ca <address1> vi trng thi tn hiu ca ln qut trc, sau lu kt qu vo <address2>. Nu trng thi hin ti ca RLO bng 1 v trng thi trc bng 0,th bt RLO s ln 1 sau lnh ny. 3.7.10 B Timer On-Delay + Biu Tng.
T S_ODT

TV

BI

BCD

Thng s T no. S TV R BI BCD Q + M t.

Kiu DL TIMER BOOL S5TIME BOOL WORD WORD BOOL

Vng nh T I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

M t M s xc nh ca b Timer, ph thuc vo fm vi ca CPU. u vo Start (bt u kch hot cho Timer hot ng). Gi tr thi gian c t sn. Reset u vo. Gi tr thi gian cn li, nh dng theo kiu integer. Gi tr thi gian cn li, nh dng theo kiu BCD. Trng thi ca b Timer.

S_ODT. B Timer bt u hot ng nu c xung tn hiu tch cc ti u vo Start (S). l mt tn hiu lun lun cn thit cho php b Timer hot ng. B Timer s chy i vi khong thi gian c thit lp sn ti u vo TV min l c trng thi xung tn hiu tch cc ti u vo S. Trng thi tn hiu ti u ra Q bng 1 khi trong qu trnh thc hin khng c li v trng thi tn hiu u vo S vn cn mc logic 1. Khi trng thi tn hiu ti u vo thay i t 1 xung 0 trong khi b Timer vn ang chy, th b Timer s chuyn sang ch STOP. Trong lc ny trng thi tn hiu ti u ra Q bng 0. B Timer reset nu u vo Reset (R) thay i t 0 ln 1 ngay c khi b Timer ang chy. Khi thi gian tc thi v thi gian thit lp cng s bng 0. 3.7.11 B Timer gi On-Delay + Biu Tng.
T S_ODTS

TV

BI

BCD

Thng s T no.

Kiu DL TIMER

Vng nh T

M t M s xc nh ca b Timer, ph thuc vo fm vi ca CPU u vo Start (bt u kch hot cho Timer hot ng) Gi tr thi gian c t sn. Reset u vo. Gi tr thi gian cn li, nh dng theo kiu integer. Gi tr thi gian cn li, nh dng theo kiu BCD. Trng thi ca b Timer.

S TV R BI BCD Q + M t.

BOOL S5TIME BOOL WORD WORD BOOL

I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

S_ODTS. B Timer bt u hot ng nu c xung tn hiu tch cc ti u vo Start (S). l mt tn hiu lun lun cn thit cho php b Timer hot ng. B Timer s chy i vi khong thi gian c thit lp sn ti u vo TV ngay c khi nu trng thi tn hiu ti u vo S thay i v 0 trc khi khong thi gian thit lp ban u c chy ht. Trng thi tn hiu ti u ra Q bng 1 khi b Timer chy xong thi gian t ban u m khng quan tm n trng thi tn hiu ti u vo S. B Timer s khi ng li gi tr thi gian ( chy c) nu trng thi tn hiu ti u vo thay i t 0 ln 1 ngay c trong lc b Timer ang chy. B Timer reset nu u vo Reset (R) thay i t 0 ln 1 m khng quan tm n RLO ti u vo S. Th trng thi tn hiu ti u ra Q sau bng 0. 3.7.12 B Timer Off-Delay + Biu Tng.
T S_OFFDT

TV

BI

BCD

Thng s T no.

Kiu DL TIMER

Vng nh T

M t M s xc nh ca b Timer, ph thuc vo fm vi ca CPU u vo Start (bt u kch hot cho Timer hot ng) Gi tr thi gian c t sn. Reset u vo. Gi tr thi gian cn li, nh dng theo kiu integer. Gi tr thi gian cn li, nh dng theo kiu BCD. Trng thi ca b Timer.

S TV R BI BCD Q

BOOL S5TIME BOOL WORD WORD BOOL

I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D I, Q, M, L, D

+ M t. S_OFFDT. B Timer bt u hot ng nu c xung tn hiu tch cc ti u vo Start (S). l mt tn hiu lun lun cn thit cho php b Timer hot ng. Trng thi tn hiu ti u ra Q bng 1 nu trng thi tn hiu ti u vo S bng 1 hoc trong lc b Timer ang chy (Timer is running). B Timer s Reset khi trng thi tn hiu u vo S i t 0 ln 1 trong lc b Timer ang chy. B Timer s khng khi ng li cho n khi trng thi tn hiu u vo S thay i mt ln na t 1 xung 0. B Timer reset nu u vo Reset (R) thay i t 0 ln 1 trong lc b Timer ang chy.