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O
O
O
O
O
<=
<=
<=
<=
<=
I0;
I1;
I2;
I3;
"ZZZ";
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else
O <=
I0 when
I1 when
I2 when
I3 when
"ZZZ";
statement
S="00" else
S="01" else
S="10" else
S="11" else
end behv2;
---------------------------------------------------- n-bit Comparator
--------------------------------------------------entity Comparator is
generic(n: natural :=2);
port(
A:
in std_logic_vector(n-1 downto 0);
B:
in std_logic_vector(n-1 downto 0);
less:
out std_logic;
equal:
out std_logic;
greater:
out std_logic
);
end Comparator;
--------------------------------------------------architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
-------------------------------------------------- 2:4 Decoder (ESD figure 2.5)-- decoder is a kind of inverse process
-- of multiplexor
------------------------------------------------entity DECODER is
port(
I:
in std_logic_vector(1 downto 0);
O:
out std_logic_vector(3 downto 0)
);
end DECODER;
------------------------------------------------architecture behv of DECODER is
begin
-- process statement
process (I)
begin
-- use case statement
case I is
when "00" => O
when "01" => O
when "10" => O
when "11" => O
when others =>
end case;
<= "0001";
<= "0010";
<= "0100";
<= "1000";
O <= "XXXX";
end process;
end behv;
architecture when_else of DECODER is
begin
-- use when..else statement
O <=
end when_else;
"0001" when
"0010" when
"0100" when
"1000" when
"XXXX";
I
I
I
I
=
=
=
=
"00"
"01"
"10"
"11"
else
else
else
else
A:
B:
Sel:
Res:
);
end ALU;
--------------------------------------------------architecture behv of ALU is
begin
process(A,B,Sel)
begin
-- use case statement to achieve
-- different operations of ALU
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;
------------------------------------------------------------------------------------------------------------ Example of doing multiplication showing
-- (1) how to use variable with in process
entity D_latch is
port(
data_in:
enable:
data_out:
);
end D_latch;
in std_logic;
in std_logic;
out std_logic
in std_logic;
in std_logic;
in std_logic;
out std_logic
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
------------------------------------------------------------------------------------------------------ 3-bit Shift-Register/Shifter
-- (ESD book figure 2.6)
-- by Weijun Zhang, 04/2001
--- reset is ignored according to the figure
--------------------------------------------------library ieee ;
use ieee.std_logic_1164.all;
--------------------------------------------------entity shift_reg is
port(
I:
clock:
shift:
Q:
);
end shift_reg;
in std_logic;
in std_logic;
in std_logic;
out std_logic
end process;
-- concurrent assignment
Q <= S(0);
end behv;
-------------------------------------------------------------------------------------------------------- VHDL code for n-bit counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
--- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
---------------------------------------------------library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------entity counter is
generic(n: natural :=2);
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q:
out std_logic_vector(n-1 downto 0)
);
end counter;
---------------------------------------------------architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
---------------------------------------------------------------------------------------------------------
in std_logic;
in std_logic;
in std_logic;
out std_logic
end if;
when S1 => x <= '0';
if a='0' then
next_state <= S1;
elsif a='1' then
next_state <= S2;
end if;
when S2 => x <= '0';
if a='0' then
next_state <= S2;
elsif a='1' then
next_state <= S3;
end if;
when S3 => x <= '1';
if a='0' then
next_state <= S3;
elsif a='1' then
next_state <= S0;
end if;
when others =>
x <= '0';
next_state <= S0;
end case;
end process;
end FSM;
------------------------------------------------------------------------------------------------------------------- a simple 4*4 RAM module (ESD book Chapter 5)
-- by Weijun Zhang
--- KEYWORD: array, concurrent processes, generic, conv_integer
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------entity SRAM is
generic(
width:
depth:
addr:
port(
Clock:
Enable:
Read:
Write:
Read_Addr:
Write_Addr:
Data_in:
Data_out:
);
integer:=4;
integer:=4;
integer:=2);
in std_logic;
in std_logic;
in std_logic;
in std_logic;
in std_logic_vector(addr-1 downto 0);
in std_logic_vector(addr-1 downto 0);
in std_logic_vector(width-1 downto 0);
out std_logic_vector(width-1 downto 0)
end SRAM;
-------------------------------------------------------------architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
------------------------------------------------------------------------------------------------------------------------------ 32*8 ROM module (ESD Book Chapter 5)
-- by Weijun Zhang, 04/2001
--- ROM model has predefined content for read only purpose
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port(
Clock
: in std_logic;
Reset
: in std_logic;
Enable : in std_logic;
Read
: in std_logic;
begin
process(Clock, Reset, Read, Address)
begin
if( Reset = '1' ) then
Data_out <= "ZZZZZZZZ";
elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then
if( Read = '1' ) then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;
end if;
end if;
end process;
end Behav;
---------------------------------------------------------------------------------------------------------------------- Simple Microprocessor Design
--- Microprocessor composed of
-- Ctrl_Unit, Data_Path and Memory
-- structural modeling
-- microprocessor.vhd
-------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.constant_lib.all;
entity microprocessor is
port(
cpu_clk:
in std_logic;
cpu_rst:
in std_logic;
cpu_output:
out std_logic_vector(15 downto 0)
);
end microprocessor;
architecture structure of microprocessor is
component datapath is
port(
clock_dp:
in std_logic;
rst_dp:
in std_logic;
imm_data:
in std_logic_vector(15 downto 0);
mem_data:
in std_logic_vector(15 downto 0);
RFs_dp:
in std_logic_vector(1 downto 0);
RFwa_dp:
in std_logic_vector(3 downto 0);
RFr1a_dp:
in std_logic_vector(3 downto 0);
RFr2a_dp:
in std_logic_vector(3 downto 0);
RFwe_dp:
in std_logic;
RFr1e_dp:
in std_logic;
RFr2e_dp:
in std_logic;
jp_en:
in std_logic;
ALUs_dp:
in std_logic_vector(1 downto 0);
oe_dp:
in std_logic;
ALUz_dp:
out
std_logic;
RF1out_dp:
out std_logic_vector(15 downto 0);
ALUout_dp:
out std_logic_vector(15 downto 0);
bufout_dp:
out
std_logic_vector(15 downto 0)
);
end component;
component ctrl_unit is
port(
clock_cu:
in std_logic;
rst_cu:
in std_logic;
PCld_cu:
in std_logic;
mdata_out:
in std_logic_vector(15 downto 0);
dpdata_out:
in std_logic_vector(15 downto 0);
maddr_in:
out std_logic_vector(15 downto 0);
immdata:
out std_logic_vector(15 downto 0);
RFs_cu:
out
std_logic_vector(1 downto 0);
RFwa_cu:
out
std_logic_vector(3 downto 0);
RFr1a_cu:
out
std_logic_vector(3 downto 0);
RFr2a_cu:
out
std_logic_vector(3 downto 0);
RFwe_cu:
out
std_logic;
RFr1e_cu:
out
std_logic;
RFr2e_cu:
out
std_logic;
jpen_cu:
out std_logic;
ALUs_cu:
out
std_logic_vector(1 downto 0);
Mre_cu:
out std_logic;
Mwe_cu:
out std_logic;
oe_cu:
out std_logic
);
end component;
component memory is
port ( clock
:
rst
Mre
in std_logic;
:
:
in std_logic;
in std_logic;
Mwe
address :
data_in :
data_out:
:
in std_logic;
in std_logic_vector(7 downto 0);
in std_logic_vector(15 downto 0);
out std_logic_vector(15 downto 0)
);
end component;
signal
downto
signal
signal
signal
signal
signal
signal
addr_bus,mdin_bus,mdout_bus,immd_bus,rfout_bus: std_logic_vector(15
0);
mem_addr: std_logic_vector(7 downto 0);
RFwa_s, RFr1a_s, RFr2a_s: std_logic_vector(3 downto 0);
RFwe_s, RFr1e_s, RFr2e_s: std_logic;
ALUs_s, RFs_s: std_logic_vector(1 downto 0);
IRld_s, PCld_s, PCinc_s, PCclr_s: std_logic;
Mre_s, Mwe_s, jpz_s, oe_s: std_logic;
begin
mem_addr <= addr_bus(7 downto 0);
Unit0: ctrl_unit port map(
cpu_clk,cpu_rst,PCld_s,mdout_bus,rfout_bus,addr_bus,
immd_bus,
RFs_s,RFwa_s,RFr1a_s,RFr2a_s,RFwe_s,
RFr1e_s,RFr2e_s,jpz_s,ALUs_s,Mre_s,Mwe_s,oe_s);
Unit1: datapath port map(
cpu_clk,cpu_rst,immd_bus,mdout_bus,
RFs_s,RFwa_s,RFr1a_s,RFr2a_s,RFwe_s,RFr1e_s,
RFr2e_s,jpz_s,ALUs_s,oe_s,PCld_s,rfout_bus,
mdin_bus,cpu_output);
Unit2: memory port map(
cpu_clk,cpu_rst,Mre_s,Mwe_s,mem_addr,mdin_bus,mdout_bus);
end structure;
------------------------------------------------------------------------- Simple Microprocessor Design (ESD Book Chapter 3)
-- Copyright Spring 2001 Weijun Zhang
--- Control Unit composed of Controller, PC, IR and multiplexor
-- VHDL structural modeling
-- ctrl_unit.vhd
-----------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ctrl_unit is
port(
clock_cu:
rst_cu:
PCld_cu:
mdata_out:
dpdata_out:
maddr_in:
immdata:
RFs_cu:
RFwa_cu:
in
in
in
in
in
out
out
out
out
std_logic;
std_logic;
std_logic;
std_logic_vector(15 downto 0);
std_logic_vector(15 downto 0);
std_logic_vector(15 downto 0);
std_logic_vector(15 downto 0);
std_logic_vector(1 downto 0);
std_logic_vector(3 downto 0);
RFr1a_cu:
RFr2a_cu:
RFwe_cu:
RFr1e_cu:
RFr2e_cu:
jpen_cu:
ALUs_cu:
Mre_cu:
Mwe_cu:
oe_cu:
out
out
out
out
out
out
out
out
out
out
);
end ctrl_unit;
architecture struct of ctrl_unit is
component controller is
port(
clock:
in std_logic;
rst:
in std_logic;
IR_word:
in std_logic_vector(15
RFs_ctrl:
out std_logic_vector(1
RFwa_ctrl:
out std_logic_vector(3
RFr1a_ctrl:
out std_logic_vector(3
RFr2a_ctrl:
out std_logic_vector(3
RFwe_ctrl:
out std_logic;
RFr1e_ctrl:
out std_logic;
RFr2e_ctrl:
out std_logic;
ALUs_ctrl:
out std_logic_vector(1
jmpen_ctrl:
out std_logic;
PCinc_ctrl:
out std_logic;
PCclr_ctrl:
out std_logic;
IRld_ctrl:
out std_logic;
Ms_ctrl:
out std_logic_vector(1
Mre_ctrl:
out std_logic;
Mwe_ctrl:
out std_logic;
oe_ctrl:
out std_logic
);
end component;
component IR is
port(
IRin:
IRld:
dir_addr:
IRout:
);
end component;
downto
downto
downto
downto
downto
0);
0);
0);
0);
0);
downto 0);
downto 0);
component PC is
port(
PCld:
in std_logic;
PCinc: in std_logic;
PCclr: in std_logic;
PCin:
in std_logic_vector(15 downto 0);
PCout: out std_logic_vector(15 downto 0)
);
end component;
component bigmux is
port(
Ia:
in std_logic_vector(15 downto 0);
Ib:
in std_logic_vector(15 downto 0);
Ic:
in std_logic_vector(15 downto 0);
Id:
in std_logic_vector(15 downto 0);
Option: in std_logic_vector(1 downto 0);
begin
IR2mux_a <= "00000000" & IR_sig(7 downto 0);
IR2mux_b <= "000000000000" & IR_sig(11 downto 8);
immdata <= IR2mux_a;
U0: controller port map(
clock_cu,rst_cu,IR_sig,RFs_cu,RFwa_cu,
RFr1a_cu,RFr2a_cu,RFwe_cu,RFr1e_cu,
RFr2e_cu,ALUs_cu,jpen_cu,PCinc_sig,
PCclr_sig,IRld_sig,Ms_sig,Mre_cu,Mwe_cu,oe_cu);
U1: PC port map(PCld_cu, PCinc_sig, PCclr_sig, IR2mux_a, PC2mux);
U2: IR port map(mdata_out, IRld_sig, IR2mux_a, IR_sig);
U3: bigmux port map(dpdata_out,IR2mux_a,PC2mux,IR2mux_b,Ms_sig,maddr_in);
end struct;
http://esd.cs.ucr.edu/labs/tutorial/#comb_logic
http://en.wikipedia.org/wiki/Reliability_engineering