VHDL Programs

-----------------------------------------------------------------------1.
VHDL code for ENCODER

-----------------------------------------------------------------------ENTITY ENCODER8_3 IS
PORT ( ENABLE : IN STD_LOGIC;
D_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );
END ENCODER8_3;
-----------------------------------------------------------------------ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS
BEGIN
PROCESS(ENABLE,D_IN)
BEGIN
IF ( ENABLE = '1') THEN
D_OUT <= "000";
ELSE
CASE D_IN IS
WHEN "00000001" => D_OUT <= "000";
WHEN "00000010" => D_OUT <= "001";
WHEN "00000100" => D_OUT <= "010";
WHEN "00001000" => D_OUT <= "011";
WHEN "00010000" => D_OUT <= "100";
WHEN "00100000" => D_OUT <= "101";
WHEN "01000000" => D_OUT <= "110";
WHEN 10000000 => D_OUT <= "111";
WHEN OTHERS => NULL";
END CASE;
END IF;
END PROCESS;
END ENCODER_ARCH;
--------------------------------------------------------------------------2. -- VHDL code for 4:1 multiplexor
--------------------------------------------------------------------------entity Mux is
port(
I3:
I2:
I1:
I0:
S:
O:
);
end Mux;
in std_logic_vector(2 downto 0);

out std_logic_vector(2 downto 0)
------------------------------------------------architecture behv1 of Mux is

begin
process(I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
O
O
O
O
O
<=
<=
<=
<=
<=
I0;
I1;
I2;
I3;
"ZZZ";
end process;
end behv1;
architecture behv2 of Mux is
begin
-- use when.. else
O <=
I0 when
I1 when
I2 when
I3 when
"ZZZ";
statement
S="00" else
S="01" else
S="10" else
S="11" else
end behv2;
---------------------------------------------------- n-bit Comparator
--------------------------------------------------entity Comparator is
generic(n: natural :=2);
port(
A:
in std_logic_vector(n-1 downto 0);
B:
less:
out std_logic;
equal:
out std_logic;
greater:
out std_logic
);
end Comparator;
--------------------------------------------------architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end behv;
-------------------------------------------------- 2:4 Decoder (ESD figure 2.5)-- decoder is a kind of inverse process
-- of multiplexor
------------------------------------------------entity DECODER is
port(
I:
O:
);
end DECODER;
------------------------------------------------architecture behv of DECODER is
begin
-- process statement
process (I)
begin
-- use case statement
case I is
when "00" => O
when "01" => O
when "10" => O
when "11" => O
when others =>
end case;
<= "0001";
<= "0010";
<= "0100";
<= "1000";
O <= "XXXX";
end process;
end behv;
architecture when_else of DECODER is
begin
-- use when..else statement
O <=
end when_else;
"0001" when
"0010" when
"0100" when
"1000" when
"XXXX";
I
I
I
I
=
=
=
=
"00"
"01"
"10"
"11"
else
else
else
else
---------------------------------------------------- Simple ALU Module (ESD book Figure 2.5)

-- by Weijun Zhang, 04/2001
--- ALU stands for arithmatic logic unit.
-- It perform multiple operations according to
-- the control bits.
-- we use 2's complement subraction in this example
-- two 2-bit inputs & carry-bit ignored
--------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--------------------------------------------------entity ALU is
port(
A:
B:
Sel:
Res:

);
end ALU;
--------------------------------------------------architecture behv of ALU is
begin
process(A,B,Sel)
begin
-- use case statement to achieve
-- different operations of ALU
case Sel is
when "00" =>
Res <= A + B;
when "01" =>
Res <= A + (not B) + 1;
when "10" =>
Res <= A and B;
when "11" =>
Res <= A or B;
when others =>
Res <= "XX";
end case;
end process;
end behv;
------------------------------------------------------------------------------------------------------------ Example of doing multiplication showing
-- (1) how to use variable with in process
-- (2) how to use for loop statement

-- (3) algorithm of multiplication
--- by Weijun Zhang, 05/2001
-------------------------------------------------------library ieee;
-- two 4-bit inputs and one 8-bit outputs
entity multiplier is
port(
num1, num2:
product:
);
end multiplier;
architecture behv of multiplier is
begin
process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);
variable product_reg: std_logic_vector(5 downto 0);
begin
num1_reg := '0' & num1;
product_reg := "0000" & num2;
-- use variables doing computation
-- algorithm is to repeat shifting/adding
for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;
-- assign the result of computation back to output signal
product <= product_reg(3 downto 0);
end process;
end behv;
--------------------------------------------- Simple D Latch (ESD book Chapter 2.3.1)
--- latch is simply controlled by enable bit
-- but has nothing to do with clock sigal
-- notice this difference from flip-flops
-------------------------------------------library ieee ;
--------------------------------------------
entity D_latch is
port(
data_in:
enable:
data_out:
);
end D_latch;
in std_logic;
in std_logic;
out std_logic
-------------------------------------------architecture behv of D_latch is

begin
-- compare this to D flipflop
process(data_in, enable)
begin
if (enable='1') then
-- no clock signal here
data_out <= data_in;
end if;
end process;
end behv;
------------------------------------------------------------------------------------------ JK Flip-Flop with reset
-- (ESD book Chapter 2.3.1)
--- the description of JK Flip-Flop is based
-- on functional truth table
-- concurrent statement and signal assignment
-- are using in this example
---------------------------------------------library ieee;
---------------------------------------------entity JK_FF is
port ( clock:
J, K:
reset:
Q, Qbar:
);
end JK_FF;
in std_logic;
in std_logic;
in std_logic;
out std_logic
----------------------------------------------architecture behv of JK_FF is

-- define the useful signals here
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin
-- combine inputs into vector
input <= J & K;

p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;
---------------------------------------------------------------------------------------------------- n-bit Register (ESD book figure 2.6)
--- KEY WORD: concurrent, generic and range
--------------------------------------------------library ieee ;
--------------------------------------------------entity reg is
port(
I:
clock: in std_logic;
load:
in std_logic;
clear: in std_logic;
Q:
out std_logic_vector(n-1 downto 0)
);
end reg;
---------------------------------------------------architecture behv of reg is
signal Q_tmp: std_logic_vector(n-1 downto 0);
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
------------------------------------------------------------------------------------------------------ 3-bit Shift-Register/Shifter
-- (ESD book figure 2.6)
--- reset is ignored according to the figure
--------------------------------------------------library ieee ;
--------------------------------------------------entity shift_reg is
port(
I:
clock:
shift:
Q:
);
end shift_reg;
in std_logic;
in std_logic;
in std_logic;
out std_logic
--------------------------------------------------architecture behv of shift_reg is

-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
-------------------------------------------------------------------------------------------------------- VHDL code for n-bit counter (ESD figure 2.6)
--- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
---------------------------------------------------library ieee ;
---------------------------------------------------entity counter is
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q:
out std_logic_vector(n-1 downto 0)
);
end counter;
---------------------------------------------------architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
---------------------------------------------------------------------------------------------------------
-- VHDL FSM (Finite State Machine) modeling

-- (ESD book Figure 2.7)
--- FSM model consists of two concurrent processes
-- state_reg and comb_logic
-- we use case statement to describe the state
-- transistion. All the inputs and signals are
-- put into the process sensitive list.
----------------------------------------------------library ieee ;
----------------------------------------------------entity seq_design is
port(
a:
clock:
reset:
x:
);
end seq_design;
in std_logic;
in std_logic;
in std_logic;
out std_logic
----------------------------------------------------architecture FSM of seq_design is

-- define the states of FSM model
type state_type is (S0, S1, S2, S3);
signal next_state, current_state: state_type;
begin
-- cocurrent process#1: state registers
state_reg: process(clock, reset)
begin
if (reset='1') then
current_state <= S0;
elsif (clock'event and clock='1') then
current_state <= next_state;
end if;
end process;
-- cocurrent process#2: combinational logic
comb_logic: process(current_state, a)
begin
-- use case statement to show the
-- state transistion
case current_state is
when S0 => x <= '0';
if a='0' then
next_state <= S0;
elsif a ='1' then
next_state <= S1;
end if;
when S1 => x <= '0';
if a='0' then
next_state <= S1;
elsif a='1' then
next_state <= S2;
end if;
when S2 => x <= '0';
if a='0' then
next_state <= S2;
elsif a='1' then
next_state <= S3;
end if;
when S3 => x <= '1';
if a='0' then
next_state <= S3;
elsif a='1' then
next_state <= S0;
end if;
when others =>
x <= '0';
next_state <= S0;
end case;
end process;
end FSM;
------------------------------------------------------------------------------------------------------------------- a simple 4*4 RAM module (ESD book Chapter 5)
-- by Weijun Zhang
--- KEYWORD: array, concurrent processes, generic, conv_integer
-------------------------------------------------------------library ieee;
-------------------------------------------------------------entity SRAM is
generic(
width:
depth:
addr:
port(
Clock:
Enable:
Read:
Write:
Read_Addr:
Write_Addr:
Data_in:
Data_out:
);
integer:=4;
integer:=4;
integer:=2);
in std_logic;
in std_logic;
in std_logic;
in std_logic;
in std_logic_vector(addr-1 downto 0);
in std_logic_vector(addr-1 downto 0);
in std_logic_vector(width-1 downto 0);
out std_logic_vector(width-1 downto 0)
end SRAM;
-------------------------------------------------------------architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section
process(Clock, Read)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
-- Write Functional Section
process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;
------------------------------------------------------------------------------------------------------------------------------ 32*8 ROM module (ESD Book Chapter 5)
--- ROM model has predefined content for read only purpose
-------------------------------------------------------------library ieee;
entity ROM is
port(
Clock
: in std_logic;
Reset
: in std_logic;
Enable : in std_logic;
Read
: in std_logic;
Address : in std_logic_vector(4 downto 0);

Data_out: out std_logic_vector(7 downto 0)
);
end ROM;
-------------------------------------------------------------architecture Behav of ROM is
type ROM_Array is array (0 to 31)
of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "00000001",
1 => "00000010",
2 => "00000011",
3 => "00000100",
4 => "00000101",
5 => "00000110",
6 => "00000111",
7 => "00001000",
8 => "00001001",
9 => "00001010",
10 => "00001011",
11 => "00001100",
12 => "00001101",
13 => "00001110",
14 => "00001111",
OTHERS => "11111111"
);
-- Suppose ROM has

-- prestored value
-- like this table
--------------
begin
process(Clock, Reset, Read, Address)
begin
if( Reset = '1' ) then
Data_out <= "ZZZZZZZZ";
elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then
if( Read = '1' ) then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;
end if;
end if;
end process;
end Behav;
---------------------------------------------------------------------------------------------------------------------- Simple Microprocessor Design
--- Microprocessor composed of
-- Ctrl_Unit, Data_Path and Memory
-- structural modeling
-- microprocessor.vhd
-------------------------------------------------------library ieee;
use work.constant_lib.all;
entity microprocessor is
port(
cpu_clk:
in std_logic;
cpu_rst:
in std_logic;
cpu_output:
);
end microprocessor;
architecture structure of microprocessor is
component datapath is
port(
clock_dp:
in std_logic;
rst_dp:
in std_logic;
imm_data:
mem_data:
RFs_dp:
RFwa_dp:
RFr1a_dp:
RFr2a_dp:
RFwe_dp:
in std_logic;
RFr1e_dp:
in std_logic;
RFr2e_dp:
in std_logic;
jp_en:
in std_logic;
ALUs_dp:
oe_dp:
in std_logic;
ALUz_dp:
out
std_logic;
RF1out_dp:
out std_logic_vector(15 downto 0);
ALUout_dp:
bufout_dp:
out
std_logic_vector(15 downto 0)
);
end component;
component ctrl_unit is
port(
clock_cu:
in std_logic;
rst_cu:
in std_logic;
PCld_cu:
in std_logic;
mdata_out:
dpdata_out:
maddr_in:
immdata:
RFs_cu:
out
std_logic_vector(1 downto 0);
RFwa_cu:
out
RFr1a_cu:
out
RFr2a_cu:
out
RFwe_cu:
out
std_logic;
RFr1e_cu:
out
std_logic;
RFr2e_cu:
out
std_logic;
jpen_cu:
out std_logic;
ALUs_cu:
out
Mre_cu:
out std_logic;
Mwe_cu:
out std_logic;
oe_cu:
out std_logic
);
end component;
component memory is
port ( clock
:
rst
Mre
in std_logic;
:
:
in std_logic;
in std_logic;
Mwe
address :
data_in :
data_out:
:
in std_logic;
);
end component;
signal
downto
signal
signal
signal
signal
signal
signal
addr_bus,mdin_bus,mdout_bus,immd_bus,rfout_bus: std_logic_vector(15
0);
mem_addr: std_logic_vector(7 downto 0);
RFwa_s, RFr1a_s, RFr2a_s: std_logic_vector(3 downto 0);
RFwe_s, RFr1e_s, RFr2e_s: std_logic;
ALUs_s, RFs_s: std_logic_vector(1 downto 0);
IRld_s, PCld_s, PCinc_s, PCclr_s: std_logic;
Mre_s, Mwe_s, jpz_s, oe_s: std_logic;
begin
mem_addr <= addr_bus(7 downto 0);
Unit0: ctrl_unit port map(
cpu_clk,cpu_rst,PCld_s,mdout_bus,rfout_bus,addr_bus,
immd_bus,
RFs_s,RFwa_s,RFr1a_s,RFr2a_s,RFwe_s,
RFr1e_s,RFr2e_s,jpz_s,ALUs_s,Mre_s,Mwe_s,oe_s);
Unit1: datapath port map(
cpu_clk,cpu_rst,immd_bus,mdout_bus,
RFs_s,RFwa_s,RFr1a_s,RFr2a_s,RFwe_s,RFr1e_s,
RFr2e_s,jpz_s,ALUs_s,oe_s,PCld_s,rfout_bus,
mdin_bus,cpu_output);
Unit2: memory port map(
cpu_clk,cpu_rst,Mre_s,Mwe_s,mem_addr,mdin_bus,mdout_bus);
end structure;
------------------------------------------------------------------------- Simple Microprocessor Design (ESD Book Chapter 3)
-- Copyright Spring 2001 Weijun Zhang
--- Control Unit composed of Controller, PC, IR and multiplexor
-- VHDL structural modeling
-- ctrl_unit.vhd
-----------------------------------------------------------------------library ieee;
entity ctrl_unit is
port(
clock_cu:
rst_cu:
PCld_cu:
mdata_out:
dpdata_out:
maddr_in:
immdata:
RFs_cu:
RFwa_cu:
in
in
in
in
in
out
out
out
out
std_logic;
std_logic;
std_logic;
RFr1a_cu:
RFr2a_cu:
RFwe_cu:
RFr1e_cu:
RFr2e_cu:
jpen_cu:
ALUs_cu:
Mre_cu:
Mwe_cu:
oe_cu:
out
out
out
out
out
out
out
out
out
out

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic
);
end ctrl_unit;
architecture struct of ctrl_unit is
component controller is
port(
clock:
in std_logic;
rst:
in std_logic;
IR_word:
in std_logic_vector(15
RFs_ctrl:
out std_logic_vector(1
RFwa_ctrl:
RFr1a_ctrl:
RFr2a_ctrl:
RFwe_ctrl:
out std_logic;
RFr1e_ctrl:
out std_logic;
RFr2e_ctrl:
out std_logic;
ALUs_ctrl:
jmpen_ctrl:
out std_logic;
PCinc_ctrl:
out std_logic;
PCclr_ctrl:
out std_logic;
IRld_ctrl:
out std_logic;
Ms_ctrl:
Mre_ctrl:
out std_logic;
Mwe_ctrl:
out std_logic;
oe_ctrl:
out std_logic
);
end component;
component IR is
port(
IRin:
IRld:
dir_addr:
IRout:
);
end component;
downto
downto
downto
downto
downto
0);
0);
0);
0);
0);
downto 0);
downto 0);

in std_logic;
component PC is
port(
PCld:
in std_logic;
PCinc: in std_logic;
PCclr: in std_logic;
PCin:
PCout: out std_logic_vector(15 downto 0)
);
end component;
component bigmux is
port(
Ia:
Ib:
Ic:
Id:
Option: in std_logic_vector(1 downto 0);
Muxout: out std_logic_vector(15 downto 0)

);
end component;
signal
signal
signal
signal
signal
IR_sig: std_logic_vector(15 downto 0);

PCinc_sig, PCclr_sig, IRld_sig: std_logic;
Ms_sig: std_logic_vector(1 downto 0);
PC2mux: std_logic_vector(15 downto 0);
IR2mux_a, IR2mux_b: std_logic_vector(15 downto 0);
begin
IR2mux_a <= "00000000" & IR_sig(7 downto 0);
IR2mux_b <= "000000000000" & IR_sig(11 downto 8);
immdata <= IR2mux_a;
U0: controller port map(
clock_cu,rst_cu,IR_sig,RFs_cu,RFwa_cu,
RFr1a_cu,RFr2a_cu,RFwe_cu,RFr1e_cu,
RFr2e_cu,ALUs_cu,jpen_cu,PCinc_sig,
PCclr_sig,IRld_sig,Ms_sig,Mre_cu,Mwe_cu,oe_cu);
U1: PC port map(PCld_cu, PCinc_sig, PCclr_sig, IR2mux_a, PC2mux);
U2: IR port map(mdata_out, IRld_sig, IR2mux_a, IR_sig);
U3: bigmux port map(dpdata_out,IR2mux_a,PC2mux,IR2mux_b,Ms_sig,maddr_in);
end struct;
http://esd.cs.ucr.edu/labs/tutorial/#comb_logic
http://en.wikipedia.org/wiki/Reliability_engineering

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-----------------------------------------------------------------------1.

VHDL code for ENCODER

in std_logic_vector(2 downto 0);

------------------------------------------------architecture behv1 of Mux is

---------------------------------------------------- Simple ALU Module (ESD book Figure 2.5)

in std_logic_vector(1 downto 0);

-- (2) how to use for loop statement

-------------------------------------------architecture behv of D_latch is

----------------------------------------------architecture behv of JK_FF is

input <= J & K;

--------------------------------------------------architecture behv of shift_reg is

-- VHDL FSM (Finite State Machine) modeling

----------------------------------------------------architecture FSM of seq_design is

Address : in std_logic_vector(4 downto 0);

-- Suppose ROM has

std_logic_vector(3 downto 0);

in std_logic_vector(15 downto 0);

Muxout: out std_logic_vector(15 downto 0)

IR_sig: std_logic_vector(15 downto 0);

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