CPU registers and status flags explained

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Chapter 3 page 1-42

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CPU REGISTERS AND STATUS FLAGS
The CPU registers and status flags for the laO may be illustrated as follows:
Alternate Flags
Flags
Sign
Zero
Auxiliary Carry
Parity10verfiow
Subtract
Carry
Stack Pointer
Program Counter
ndex Register
Index Register
nterrupt Vector Register
Refresh Register
Accumulator
} Secondary Data Counters
Primary Data Counter
Alternate Accumulator
}
Alternate Secondary
Data Counters
Alternate Primary Data Counter
~
ro-
, ,r
I
r r
S I Z I IAct IPloi N Ic
A
B C
0 E
H L
S'I z'l lAd IP!c)'1 N'I C'
A'
B' C'
0' E'
H' L'
SP
PC
IX I
IV
I I
R
Secondary {
Accumulators
Alternate {
Secondary
Accumulators
The Accumulator is the primary source and destination for one-operand and two-
operand instructions. For example, the shortest and fastest data transfers between the
CPU and 1/0 devices are performed through the Accumulator, In addition, more Memo-
ry Reference instructions move data between the Accumu later and memory than bet-
ween any other register and memory All 8-bit arithmetic and Boolean instructions take
one of the operands from the Accumulator and return the result to the Accumulator. An
instruction must therefore load the Accumulator before the laO can perform any a-
bit arithmetic or Boolean operations.
The B. C. D. E. H. and L registers are all secondary registers. Data stored in any of
these six registers may be accessed with equal ease: such data can be moved to any
other register or can be used as the second operand In two-operand instructions.
There are, however, some important differences in the functions of Registers B, C. D. E.
H. and L
Registers Hand L are the primary Data Pointer for the laO. That is to say. you will
normally use these two registers to hold the 16-bit memory address of data being ac-
cessed. Data may be transferred between any registers and the memory location ad-
dressed by Hand L Since HL is the primary Data Pointer, It ohen takes fewer bytes of
object code and less instruction cycles to perform operations with it. The Z80 program-
mer should try to address data memory via Registers Hand L whenever possible.
Within your program logic. always reserve Registers Hand L to hold a data memo-
ryaddress.
3-2
Registers B. C. D. and E provide secondary data storage; frequently. the second
operand for two-operand instructions is stored in one of these fou r registers. (The first
operand is stored in the Accumulator. which is also the destination for the result.)
There are a limited number of instructions that treat Registers Band C. or D and E.
as 16-bit Data Pointers. But these instructions move data between memory and the
Accumulator only.
In your program logic you should normally use Registers B. C. D. and E as tempor-
ary storage for data or addresses.
Registers IX and IV are index registers. They provide a limited indexing capability of
the type described in An Introduction to Microcomputers: Volume 1 for short instruc-
tions.
The alternate registers F'. A'. B'. C'. 0'. E
/
H'. and L' provide a duplicate set of
general purpose registers. Just two single-byte Exchange instructions select and
deselect all alternate registers; one instruction exchanges AF and the alternate AF'
as a register pair. and one instruction exchanges BC. DE. and HL with the alternate BC'.
DE'. and HL' Once selected. all subsequent register operations are performed on the ac-
tive set until the next exchange selects the inactive set. The alternate registers can be
reserved for use when a fast interrupt response is required. Or. they may be used in
any desired way by the programmer.
There are a number of instructions that handle 16 bits of data at a time. These in-
structions refer to pairs of CPU registers as follows:
F
B
D
H
F'
B'
D'
H'
~
High-
order
byte
and
and
and
and
and
and
and
and
A
C
E
L
A'
C'
E'
L'
~
Low-
order
byte
The combination of the Accumulator and flags. treated as a 16-bit unit. is used only for
Stack operations and alternate register switches Arithmetic operations access Band C.
D and E. or Hand L as 16-bit data units.
The Carry status flag holds carries out of the most significant bit in any arithmetic
operation. The Carry flag is also included in Shift instructions: it is reset by Boolean in-
structions.
The Subtract flag is designed for internal use during decimal adjust operations, This
flag is set to 1 for all Subtract instructions and reset to 0 for all Add instructions.
The Parity/Overflow flag is a multiple use flag. depending on the operation being
performed. For arithmetic operations, it is an overflow flag. For input. rotate. and
Boolean operations, it is a parity flag. with 1 = even parity and 0 = odd parity. Dur-
ing block transfer and search operations. it remains set until the byte counter decre-
ments to zero: then it is reset to zero It is also set to the current state of the interrupt
enable flip-flop (IFF2) when a LD A.I or LD A.R instruction is executed.
The Zero flag is set to 1 when any arithmetic or Boolean operation generates a
zero result. The Zero status is set to 0 when such an operation generates a non-
zero result.
3-3
The Sign status flag acquires the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction.
The Auxiliary Carry status flag holds any carry from bit 3 to 4 resulting from the
execution of an arithmetic instruction. The purpos'e of this status flag is to simplify
Binary-Coded-Decimal (BCD) operations; this is the standard use of an Auxiliary Carry
status flag as described in An Introduction to Microcomputers: Volume 1, Chapter 3.
All of the above status flags keep their current value until an instruction that modifies
them is executed. Merely changing the value of the Accumulator will not necessarily
change the value of the status flags. For example. if the Zero flag is set. and a load im-
mediate to the Accumulator is executed. that causes the Accumulator to acquire a non-
zero value: the value of the Zero flag remains unchanged.
The 16-bit Stack Pointer allows you to Implement a Stack anywhere in addressa-
ble memory. The size of the Stack is limited only by the amount of addressable memory
present In reality you will rarely use more than 256 bytes of memory for your Stack.
You should use the Stack for accessing subroutines and processing interrupts. Do not
use the Stack to pass parameters to subroutines. This is not very efficient within the
limitations of the zao instruction set. The zao Stack is started at its highest address. A
Push decrements the Stack Pointer contents; a Pop increments the Stack Pointer con-
tents
The Interrupt Vector register and the Refresh register are special-purpose
registers not normally used by the programmer.
The Interrupt Vector register is used to store the page address of an interrupt response
routine: the location on the page is provided by the interrupting device. This scheme
allows the address of the interrupt response routine to be changed while still providing
a very fast response time for the interrupting device.
The Refresh register contains a memory refresh counter in the low-order seven bits.
This counter is incremented automatically after each instruction fetch and provides the
next refresh address for dynamic memories. The high-order bit of the Refresh register
will remain set or reset. depending on how it was loaded at the last LD RA instruction.
lao MEMORY ADDRESSING MODES
The zeo provides extensive addressing modes. These Include:
Implied
Implied Block Transfer with Auto-Increment/Decrement
Implied Stack
Indexed
Direct
Program Relative
Base Page
Register Indirect
Immediate
3-4
Implied
In implied memory addressing. the Hand L registers hold the address of the
memory location being acces.ed. Data may be moved between the identified memo-
ry location and anyone of the seven CPU registers A. B. C. D. E, H, or L. For example, the
instruction
LD C.(HU
loads the C register with the contents of the memory location currently pointed to by
HL. This is illustrated as follows:
Data
q
mmmm
mmm+ 1
1----.. mmrnm + 2
1- .. mmmm + 3
Memory
r
yy
1
-
pp qq
mmmm
~ m m m + ~
Program
Memory
I 4E
I m
s Z AcP/O N C
Fc:::I:IJ:I:]
A
S.C
D.E
H.l
SP
PC
IX
IV
I
R
LD C. (HU
~
76543210
EE:EE:EEEEl
1:1 [------Load Implied via HL
C Register
3-5
A limited number of instructions use Registers Band C or 0 and E as the Data
Pointer. These instructions move data between the Accumu lator and the memory loca-
tion addressed by Registers Band C or Registers D and E. The instruction
LD (BCLA
stores the contents of A into the memory location currently addressed by Register Pair
Be. This is illustrated as follows:
SZACPONC Data
Q
mmm
mmm+1
mmmm+2
1-----4mmmm + 3
CIIIIIl
Memorv
vv -
ppq
pp qql
1
j
- ~ V
Program
mmmm ~ m m m + 1
MemOry
I
02 m
I
m
F
A
B.C
O.E
H.L
SP
PC
IX
IY
I
R
LD (BCl.A
---
"",._...",.A....~ __...
r, 6 S:-4 3 2 1 0'
~
-..... J
T Store Implioed from A via BC
3-6
ED mmmm
...-----==80;-..... mmmm + 1
mmmm+2
1----1 mmmrri +3
Implied Block Transfer With Auto-Increment/Decrement
Block Transfer and Search instructions operate on a block of data whose size is
set by the programmer as the contents of the BC register pair. In this form of ad-
dressing. a byte of data is moved from the memory location addressed by HL to
the memory location addressed by DE; then HL and DE are incremented and Be is
decremented. Data transfer continues until BC reaches zero. at which point the In-
struction is terminated. Variations include allowing other instructions to follow
each data transfer. with the programmer supplying the loopback; auto-decrement-
ing HL and DE instead of auto-incrementing; and a complementary set of Block
Search instructions that compare the memory byte addressed by HL with the con-
tents of the A register. setting a flag if a match is found.
The Load. I ncrement. and Repeat instruction
LDIR
is illustrated as follows:
Set if BC- 1- o.eS8t otherwise
S Z AcP'ON C
Fo:::EI:E:I2IJ
Ar-__...-__..... .......
B.CI-__ .......__.."
D,E 1-__
.L
Spt- .....
PC mmmm
IX ...------...;..------....
IV ....... 4111........--_
I
R
LOIR
...+o....-+.....-.-..O-+-:... } load. Increment, and Repeat instruction
A similar group of Input/Output instructions is provided. allowing a block of data
to be input or output between memory and an I/O device. The I/O port nu mber is
taken as the contents of the C register. with the sing Ie B reg ister used as the byte
counter. Memory is addressed by HL.
3-7
Implied Stack
Since the Stack is part of ReadIWrite memory, we must consider Stack instructions as
Memory Reference instructions. Pu.h and Pop in.truction. move two byt of data
b.twn a r.gl.t.r pair and the .ddrd Stack Polnt.r location. i,e., current top-
of-stack, The Z80 Stack address is decremented with each Push and incremented with
each Pop. The instruction
PUSH DE
5 ZAcP/ON C
Data
ssss - 2
ssss - 1
ssss
mmmm
mmmm+ 1
...- oImmmm + 2
I- -tmmmm + 3
r::IJ:IJ:IJ
Memorv
-
C
qq
I
JA ssss-2 ~ -
pp I
pp qq
/'/'
ssss
~ - ~ ~
mmmm
:mmm+l
Program
Memory
I 05
I
F
A
B.C
D.E
H,l
SP
PC
IX
IV
,
R
PUSH DE
~ X ,
76543210
~ ~ , o , o , ~ _
-- PUSH instruction
---Register Pair DE
3-8
The laO allo hal instructions that exchange the two top-of-stack bytes with a
16-blt register - HL or one of the two index registers. The instruction
EX (SPl,HL
S Z Ac Pia N C
Data
ssss
ssss + 1
ssss + 2
mmmm
mmmm+ 1
mmmm+2
.....-----t
mmmm
+ 3
DIIIIJ
Memory
-
---
:
qq
pp
M"
xx yy
ssss
-" :v
mmmm mmmm +'
Program
Memory
I E3
I
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
3-9
Indexed
Th. zao ha. two 16-bit Ind.x r.gl.t.rs, call.d IX and IV. They may be used in-
terchangeably, All memory reference operations for which (HU can be specified can
alternatively be specified as an indexed operation, The difference between implied ad-
dressing using HL and indexed addressing using IX and IY is that the ind.x op.rand
includ a di.plac.m.nt valu. that i. add.d to the ind.x addr. ln the instruction
ADD A. (IX+40H)
the memory address is the sum of the contents of the IX register and 40
16
, This may be
illustrated as follows:
40
m
m+ 1
m+2
m+3
Data
IMemory J

ppqq
xx XX+YY
--
,
yy
; ppqQj
I
-

Program
mmmm
ppqq
-
Memory
I DO mmm
I 86

mmm
40 mmm
JI' -
.:L
mmm
ADD A,OX + 40)
S Z Ac P/O N C

A
B,C
D.E
H,l
SP
PC
IX
IV
,
R
3-10
Direct
Direct addressing can be used to load the Accumulator with any 8bit value from
memory, load BC, DE, HL, SP, IX, or IV with any 16-bit memory value, and jump or
call subroutines direct at any memory location. The 16-bit direct address is stored in
the last two bytes of the instruction. in low-byte high-byte order (this is the reverse of
the standard high-low schemel.
The i nstructi on
LD A.(NETX)
loads the A register with the contents of the memory location addressed by the label
NETX. The instruction
LD HL.l1 FFH)
loads the L register with the contents of memory location 01 FF16 and the H register
with the contents of memory location 0200
16
. This may be illustrated as follows:
Data
OIFF
0200
mmmm
) mmmm+ t
1 01 mmmm+2
1-----1 mmmm + 3
Memory
YV
xx
6
,
xx YV
- '"
Program
mmmm mmmm + 3
- "-
Memory
I 2A
I FF
'-,
S Z Ac P/O N C
FCIIIID
A
S,C
D.E
H.L
SP
PC
IX
IV
I
R
LD HL.!IFFH)
76543210
0 0
,
0 1 0
,
0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
Load HL Direct instruction
Direct address - low byte
Direct address - High byte
The direct Jump instructions provide jumps and jumps-to-subroutines, both un-
conditional and conditional. These are all 3-byte instructions. with the direct address
stored in the second and third bytes of the instruction. as shown above for Load Direct.
There are three additional addressing modes used by zao Branch instruc-
tions: program relative. base page. and register indirect. In general. they are shorter
and/or faster than direct jumps but may have more limited addressing capabilities.
3-11
Program Relative
Jump Re.etlve instructions pro'ltde pregrem re.etive eddre.slng In the renge -128,
+129 byte. from the first byte of Relative instruction. These instructions
are all 2-byte instructions, with 1'fte signed displacement value stored in the second
byte of the instruction. There .... uaaonditlonel end conditioneI re.etive jump., e.
well Decrement end Jump " Not Zero in.truction (DJNZ) thet fecllltete. loop
control.
Given the instruction
JR SRCH
assume that SRCH is a label alltdressing a location 5A
16
bytes up in memory from the
JR op-code byte. The operati.on may be illustrated as follows:
5 Z AcP/O N C
FCIIIIIJ
Data
Memory
A
B.C
D,E
H,L
SP
PC
IX
IV
I
R
- 'mmmm:f)
Program
mmmm
"""- SA
Memory

I 18
I SA
--.
JR SRCH
mmmm
mmmm+l
mmmm+2
mmmm+3
Jump Relative iAStruction

o Displacement
...."'--"'--"'--"""-"'--.....
3-12
Base Page
The Z80 has a modified base page addressing mode for the Restart instruction. This is
a special Call instruction that allows a single-byte instruction to jump to one of
eight subroutines located at specific points in lower core. The effective address is
calculated from a 3-bit code stored in the instruction. as follows:
Lower Core Address 3-Bit Code
OOH
08H
10H
18H
20H
28H
30H
38H
000
001
010
all
100
101
110
111
The decoded address value is loaded into the low-order byte of the Program Counter;
the high-order byte of the Program Counter is set to zero. For example. the instruction
RST OOH
s Z AcP/O N C Data
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
CIII:ID
Memory
,
mm+l
fl
mm
t:. ssss - 2
----..........
ssss
mmmm
Program
Memory
I
......-....
C7
000
I
ssss - 2
ssss - 1
ssss
mmmm
mmmm+ 1
mmmm+2
mmmm+3
RST OOH
76543210
-ccT--_Rest8rt instruction
code
3-13
Data
Memory
Register Indirect
In standard indirect addressing. a memory location contains the effective address. and
the instruction specifies the address of the memory location containing the effective
address. In register indirect addressing. a register contains the effective address. and
the instruction specifies which of the registers contains the effective address Note that
for a Load, for instance. this is just another way of describing implied addressing.
However. the l80 has Jump instructions that allow a jump to the memory location
whose address is contained in the specified register. This is a form of indirect ad-
dressing. and is described separately because. while most microcomputers have im-
plied addressing. very few have register indirect jumps.
The instruction
JP (HL)
directs that a jump is to be taken to the memory location whose address is contained in
HL This may be illustrated as follows:
S Z AC P/O N C
FCCIIIIJ
A
B,C
D.E
H.L
SP
PC
IX
IV
I
R
pp qq
D
mmmm
I
I
JP (HLl
--:x..-
.... ----...... :0-.
76543210

3-14
Program
Memory
E9 mmmm
1-__...... mmmm + ,
mmmm+2
1---...... mmmm + 3
Immediate
Some texts identify Immediate instructions as Memory Reference instructions. An Im-
mediate instruction is a 2-. 3-. or 4-byte instruction in which the last one or two bytes
hold fixed data that is loaded into a register or memory location. The Z80 provides Im-
mediate instructions to:
load 8-bit data into any of the 8-bit registers.
load 16-bit data into any of the register pairs or 16bit registers.
store 8-bit data into any memory location using implied or indexed addressing.
perform arithmetic and logical operations using the Accumulator and 8-bit im-
mediate data.
The instruction
LD BC.OBCH
loads the immediate data value BC16 into Register Pair BC. This may be illustrated as
follows:
S Z AcP/O N C
FCD:IIIJ
Data
Memory
A
B.C
D.E
H.l
SP
PC
IX
IV
I
R
...
mmmm
Program
Memory
I
01
I BC
'- 00
mmmm
mmmm + 1
mmmm+2
mmmm+3
LD BC. 08CH
76543210
'4T """ Om"""'... M ROO' "',

Pair BC
76543210
1 0 1 1 1 1 0
o I
0 0 0 0 0 0 0
o I
Immediate data - low-order byte
Immediate data - high-order byte
3-15
Table 3-1. Frequently Used Instructions of the zeo
Instruction Code Meaning
ADC A Add with Carry to Accumulator
ADD Add
AND Logical AND
CALL addr Call Subroutine
CALL cond,addr Call Conditional
CP Compare
DEC Decrement
DJNZ Decrement and Jump If Not Zero
IN Input
INC Increment
JR Jump Relative
JR cond.addr Jump Relative Conditional
LD reg.(HL) Load Register
LD A,(addr) Load Accumulator Direct
LD data Load Immediate
LD (HL).reg Store Register
LD (addrl.A Store Accumulator Direct
LD dst.src Move Register-ta-Register
OUT Output
POP Pop from Stack
PUSH Push to Stack
RET Return from Subroutine
RET cond Return Conditional
RLA Rotate Accumulator Left Through Carry
RRA Rotate Accumulator Right Through Carry
SLA Shift Left Arithmetic
SRL Shift Right Logical
SUB Subtract
3-16
Table 3-2. Occasionally Used of the laO
BIT Test Bit
CPD,CPDR Compare. Decrement. (Repeat)
CPI, CPIR Compare, Increment. (Repeat)
CPL Complement A<:cumulator
DAA Decill11itl Adj ust Accumu lator
01 IMerrupts
EI Enable Interrupts
EX Exchange
HALT Halt
IND.INDR Input. [)ecrement. (Repeat)
IN!. INIR Input. IncremtiHlt. (Repeat)
JP addr Jump
JP cond,addr Jump Conditional
LD A, (BC) or (DE) Load Accumulator Secondary
LD HL.(addd Load Hl Direct
LD reg, (xy+disp) Load Register Indexed
LD rp.(addr) Load Pair Direct
LD xy,(addr) Load Index Register Direct
LD (BC) or (DE),A Store Accu mu lator Secondary
LD (addr),HL Store Hl Direct
LD (xy+disp).reg Store Regfster Indexed
LD (addr),rp Store R-egis1'er Pair Direct
LD (addd,xy Store Index Register Direct
LD (HL),data Store Immediate to Memory
LD {xy+displ.data Store Immediate to Memory Indexed
LDD. LDDR Load, Decrement. (Repeat)
LD!. LDIR Load. Increment. (Retlleat)
NEG Negate (Twos Complement) Accumulator
NOP No Operation
OR Logical OR
OUTD.OTDR Output. Decrement. lRepeat)
OUTI. OTIR Output. Increment. (l\epeat)
RES Reset !i'it
RETI Retu rn from Interrupt
RL Rotate Left ThrouQh Carry
RLC Rotate Left Circular
RLCA Rotate Accumulator Left Circular
RR Rotate Right Throullh Carry
RRC Rotate RiQt1t Circll'tar
RRCA Rotate Accumu"tor Right Circular
SET Set Bit
SRA Shift Right Arithmetic
XOR Exclursi-ve OR
3-17
Table 3-3 Seldom Used Instructions of the Z80
ADC HLrp Add Register Pair with Carry to HL
CCF Complement Carry Flag
EXX Exchange Register Pairs and Alternatives
1M n Set Interrupt Mode
RETN Return from Non-Maskable Interrupt
RLD Rotate Accumulator and Memory Left Decimal
RRD Rotate Accumulator and Memory Right Decimal
RST Restart
SSC Subtract with Carry (Borrow)
SCF Set Carry Flag
LD AI Load Accumulator from Interrupt Vector Register
LD AR Load Accumulator from Refresh Register
LD I.A Store Accu mu lator to Interru pt Vector Register
LD R.A Store Ac{'u mu lator to Refresh Register
LD SP.HL Move HL to Stack Pointer
LD SP.xy Move Index Register to Stack Pointer
ABBREVIATIONS
Program Counter
An 8-bit I/O port address
data
data16
These are the abbreviations used in this chapter:
A.F.B.C.D,E.H.L The 8-bit registers. A is the Accumulator and F is the Flag Word.
AF'.BC'.DE'.HL' The alternate register pairs
addr A 16-bit memory address
x(b) Bit b of 8-bit register or memory location x
cond Condition for program branching. Conditions are:
NZ - Non-Zero (Z = 0)
Z -Zero(Z=l)
NC - Non-carry (C = 0)
C - Carry (C = 1)
PO - Parity Odd (P = 0)
PE - Parity Even (P = 1)
P - Positive Sign (S = 0)
M - Negative Sign (S = 1)
An 8-bit binary data unit
A 16-bit binary data unit
An 8-bit signed binary address displacement
The high-order 8 bits of a 16-bit quantity xx
Interrupt Vector register (8 bits)
The Index registers (16 bits each)
A 16-bit instruction memory address
The low-order 8 bits of a 16-bit quantity xx
Least Sig nificant Bit (B it 0)
Most Significant Bit (Bit 7)
port
IX IY
label
disp
xx(HI)
I
xx(LO)
LSB
MSB
PC
3-18
pr
R
reg
rp
SP
xy
Object Code
Any of the following register pairs:
BC
DE
HL
AF
The Refresh register (8 bits)
Any of the following registers:
A
B
C
D
E
H
L
Any of the following register pairs:
BC
DE
HL
SP
Stack Pointer (16 bits)
Either one of the Index registers (IX or lY)
bbb Bit number 000 (LSB) to 111 (MSB)
eec Condition code 000 = non-zero
001 = zero
010 = no carry
011 = carry
100 = parity odd
101 = parity even
110 = positive sign
111 =negative sign
ddd Destination register - same coding as rrr
ppqq A 16-bit memory address
rrr Register 111 = A
000 = B
001 = C
010 =D
011 = E
100 = H
101 = L
sss Source register - same coding as rrr
x Index reg ister 0 = IX
1 =IY
xx Register pair 00 = BC
01 = DE
10 = HL
11 =SP (rp) or AF (pr)
xxx Restart code (000 to 111)
yy An 8-bit binary data unit
yyyy A 16-bit binary data unit
3-19
Statuses
[[ ]]
[]
A
V
41-
---+
The l80 has the following status flags:
C - Carry status
l - lero status
S - Sign status
P/O - Parity/Overflow status
AC - Auxiliary Carry status
N - Subtract status
The following symbols are used in the status columns:
X - flag is affected by operation
(blank) - flag is not affected by operation
1 - flag is set by operation
o - flag is reset by operation
U - flag is unknown after operation
P - flag shows paritY status
o - flag shows overflow status
I - flag shows interrupt enabled/disabled status
Memory addressing: 1) the contents of the memory location
whose address is contained in the designated register. 2) an
I/O port whose address is contained in the designated register.
The contents of a register or memory location.
For example:
([HLll +- [[HLll + 1
indicates that the contents of the memory location addressed by
the contents of HL are incremented. whereas:
[HL] +- [HL] + 1
indicates that the contents of the HL register itself are incre-
mented.
Logical AND
Logical OR
Logical Exclusive-OR
Data is transferred in the direction' of the arrow
Data is exchanged between the two locations designated on either
side of the arrows.
3-20
INSTRUCTION MNEMONICS
Table 3-4 summarizes the leO instruction set. The MNEMONIC column shows the
instruction mnemonic UN, OUT, LD). The OPERAND column shows the operands,
if any. used with the instruction mnemonic.
The fixed part of an assembly language instruction is shown In UPPER CASE. The
variable part (Immediate data. I/O device number, register name. label or address)
is .hown in lower case.
are:
For closely related operands, each type is listed separately
mnemonic. For instance, examples of the format entry
LD rp,(addr)
xy,(addr)
LD BC.(DAT2)
LD IX,(MEM)
INSTRUCTION OBJECT CODES
without repeating the
The object code a"d instruction length in byte. are shown in Table 3-4 for each
instruction variation. Table 3-5 lists the object codes in numerical order.
For instruction bytes without variations. object code. are represented as two
hexadecimal digits (e.g 3F).
For instruction bytes with variations in one of the two digits, the object code is
shown as one 4-bit binary digit and one hexadecimal digit le.g. 11 x 1 D) in Table
3-5. For other instruction bytes with variation., the object code is .hown as eight
binary digits (e.g., 0118.001).
INSTRUCTION EXECUTION TIMES
Table 3-4 lists the instruction execution times in clock periods. Real time can be
obtained by dividing the given number of clock periods by the clock frequency. For
example. for an instruction that requires 7 clock periods. a 4 MHz clock will result in a
1.75 microsecond execution time.
When two possible execution times are shown (j.e., 5/11), it indicates that the
number of clock periods depends on condition flags. The first time is for "condi-
tion not met," whereas the second is for "condition met."
STATUS
The six status flags are stored in the Flag register (F) as follows:
--+-...--t--+--......--These bits are not used
......--Carry status (carry out of bi,t 7)
......---- Subtract stetus
(, aftar subtract operation. 0 otharwise)
""------ Parity/Overflow
(for logical operations. 1 for ellen. 0 for odd parity.
For arithmetic, 1 for overflow)
10.- Auxiliary Carry status (carry out of bit 3)
.....------------Zero status (1 for zero, 0 for nonzero)
.....-------------Sign status (vatue of bit 7)
3-21
In the individual instruction descriptions. the effect of instruction execution on
status is illustrated as follows:
s Z AC Pia N C
171 !ll
x
l
o
l
x
l
~ l j ~ ~ ~ I
Modified to reflect results of execution
Unconditionally reset to 0
Unconditionally set to 1
Unchanged
Unknown
An X identifies a status that is set or reset. A 0 identifies a status
that is always cleared. A 1 identifies a status that is always set. A
blank means the status does not change. A question mark (?)
means the status is not known.
3-22
STATUS
CHANGES
WITH
INSTRUCTION
EXECUTION
Address Bus: AO-A7: [e)
AS-A1S: [B)
Taole 3-4. A Summary of the zao Instruction Set
(,J
I
""
(,J
Clock
Status
Type Mnemonic Operend Object Code Bytes Operation Performed;
Cycles
C Z S PIO AC N
IN A,(portl DB yy 2 10 [AJ- [pertJ
Input to Accumulator from directly addressed 1/0 port.
Address Bus: AO-A7: port
AS-A15 [AI
IN reg,ICl ED 01dddOOO 2 11 X X P X 0 [regl- [[ Cll
Input to register from 1/0 port addressed by the contents of C."
ED B2 2 20/15" 1
] ] 1
If second byte is 70
16
only the flags will be affected.
INIR ? Repeat until [ BJ = 0:
[[ HLI)- [(Cll
[BJ-[Bl- 1
[ HLI - [HLI + 1
Transfer a block of data from 1/0 port addressed by contents of C
to memory location addressed by contents of HL, going from low
addresses to high. Contents of B serve as a count of bytes remain-
ing to be transferred."
0 INDR ED BA 2 20/15" 1 7 ]
? 1 Repeat until [ BJ =0:
::.
[[HL1J-[[Cll
[B)-[B]- 1
[ HLJ - [HLJ - 1
Transfer a block of data from 1/0 port addressed by contents of C
to memory location addressed by contents of HL, going from high
addresses to low. Contents of B serve.as a count of bytes remaining
to be transferred."
INI ED A2 2 15 X ?
]
? 1 [[ HLI- [[ C]]
[B)-[BJ - 1
[ HLI - [ HLI + 1
Transfer a byte of data from 1/0 port addressed bv contents of C to
memory location addressed by contents of HL Decrement byte
count and increment destination address."
Address Bus: AO-A7: IC]
A8-A1S: IB)
Table 3-4. A Summary of the zao Instruction Set (Continued)
Co)
I
~
Clock
Statu.
Typa, Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO A
C
N
INO EDAA 2 15 X ?
]
? I [[ HU] - [[ CII
(BJ - [BI- I
t HL] - [HLI - I
Transfer a byte of data from I/O port addressed by contents of C to
memory location addressed by contents of HL. Decrement both
byte count and destination address."
OUT (portl.A 03 yy 2 II [port] - [A]
Output from Accumulator to directly addressed I/O port.
Address Bus: AO-A7: port
A8-A1S: [Al
OUT (Cl.reg EO 01555001 2 12 11 C])- [reg]
Output from register to I/O port addressed by the contents of C."
OTIR ED B3 2 20/15 1
]
?
]
1 Repeat until ( BI =0:
'ij
([C])-([HL])
[8]- [BI - 1
::>
.5 (HU-[HU+ 1
e
Transfer a block of date from memory location addressed by con- 0
~
tents of HL to I/O port addressed by contents of C. going from low
g
memory to high. Contents of B serve as a count of bytes remaining
to be transferred.
OTOR ED BB 2 20/15 I 7 7 ? 1 Repeat until [BI = 0:
[[C])-[[HL])
[BI-IBJ -,
[ HLI - I HU - ,
Transfer a block of data from memory location addressed by con-
tents of Hl to I/O port addressed by contents of C. going from high
memory to low. Contents of B serve as a count of bytes remaining
to be transferred.
.. Address Bus: AO-A7; (C)
AS-A15: [B)
w
N
C1l
Clock
Status
Type Mnemonic Operand Object Code Bytes
Cycles
Operation Performed
C Z S PIO
AC N
OUli ED A3 2 15 X ? 7 7 1 [[ClI - [[HLlJ
[Bl- [BI- 1
[HLJ - [HLl + 1
'ii
Transfer a byte of data from memory location addressed by con-
tents of Hl to 1/0 port addressed by contents of C. Decrement byte :::I
c
....
count and increment source address.
c
0
OUTD ED AB 2 15 X 7 7 7 1 [[C)]-[(HL)]
H
[B]- [Bl - 1
g
[HLl-[HLl-1
Transfer a byte of data from memory location addressed by con-
tents of HL to 110 port addressed by contents of C. Decrement both
byte count and source address.
LD A,(addd 3A ppqq 3 13 [Al- [addrl
load Accumulator from directly addressed memory location.
LD HL,(addd 2A ppqq 3 16 [ HI - [ addr + 1l. [ Ll - [ addrl
load Hl from directly addressed memory.
LD rp,laddd ED 01xx1011 ppqq 4 20 [ rplHIlJ - I addr + 1l. [ rpllOI) - [ addrl or
xy,(addrl 1hl11012Appqq 20 [ xy(HIl] - [ addr + 1L [xy(LOII - [ addrl

u
4
c
Load register pair or Index register from directly addressed memo-
...
ry. a
II:
LD laddd,A 32 ppqq 3 13 [addrl- [AI
>-
Ii
Store Accumulator contents in directly addressed memory location.
E
II LD !addd,HL 22 ppqq 3 16 [ addr + 1] - [Hl. [addrl - ( L]
~
Store contents of Hl to directly addressed memory location.
>-
..
LD laddrl,rp ED 01xxOOll ppqq 4 20 [ addr + 1] - [rp(HIlI. [addrl - [ rplLO)] or II
,
(addd,xy 1hl1101 22 ppqq 4 20 [ addr + 11 - [ xy(HIIl. [addr] - [ xy(lOll
.t
Store contents of register pair or Index register to directly ad-
dressed memory.
LD A,IBC) OA 1 7 [ Al - [[ BC]l or [ Al - [[ DEli
A,IDEI 1A 1 7 load Accumulator from memory location addressed by the con-
tents of the specified register pair.
Co)
I
!'oJ
(J)
Clock
Status
Type Mnemonic Operand Object Code Byte.
Cycle.
Operation Performed
C Z S PIO A
C
N
LD reg.(HU 01ddd110 1 7 I reg] - I[ HLII
to
Load register from memory location addressed by contents of HL.
...
LD (Bel,A 02 1 II BClI - I Alar [[ DEll - [ A) ~ 7
!
(DEl,A 12 1 7 Store Accumulator to memory location addressed by the contents to
'0_
of the specified register pair.
11:-0
>
LD (HLl,reg 01110sss 1 7 [I HLII - I reg)
6 . ~
E .. Store register contents to memory location addressed by the con-
.~
tents of HL.
~ ~
~
LD reg.(xy+disp 11x1110101ddd110 3 19 [ reg] - [[ xy] + disp]
'"
disp Load register from memory location using base relative addressing.
E
~
LD xy +displ,reg 11x1110101110sss 3 19 [[ xy] + displ - I reg]
disp Store register to memory location addressed relative to contents of
Index regi ster.
LDIR ED BO 2 20116 0 0 0 Repeat until [ BCl ~ 0:
[[ DEll - [[ HLl]
I DEI - I DEI + 1
I HLI - I HLl + 1
~
[ BC] - [ BC] - 1
!!
'"
Transfer a block of data from the memory location addressed by
III
the contents of HL to the memory location addressed by the con-
-0
~
tents of DE. going from low addresses to high. Contents of BC
'"
0-
serve as a count of bytes to be transferred.
-!
LDDR ED B8 2 20/16 0 0 0 Repeat until [ BC] = 0:
~
~
I[ DEll - [[ HLl]
~ I DEl - [ DE) - 1
u
IHLl-IHLl-1
0
iii
[ BC] - [BCl - 1
Transfer a block of data from the memory location addressed by
tents of DE. going from high addresses to low. Contents of BC
serve as a count of bytes to be transferred.
Co)
I
N
.....
Table 3-4. A Summary of the Z80 Instruction Set (Continued)
Clock
Status
Type Mnemonic Operand Object Code Bytes Operation Performed
Cycles
C Z S PIO
AC N
LDI EO AO 2 16 X 0 0 [[ DEll [[ HLlI
[ DEl [DEI + 1
[ HLI [HLI + 1
[ BCI [ BCI - 1
Transfer one byte of data from the memory location addressed by
tents of DE. Increment source and destination eddresses and decre-
ment byte count.
LDD ED AS 2 16 X 0 0 [[ DEll
'ii [ DE] - [ DEI - 1
:l
[ BCI [ BCI - 1
c
0
Transfer one byte of data from the memory location addressed by
.t:. Ihe conlents of HL to Ihe memory location addressed by the con-

l,)
Iii tents of DE. Decrement source and destination addresses and byte
II)
count.
'C
CPIR ED B1 2 20/16" X X X X Repeat until [AI =[[ HLll or [ BCI =0: c: 1
II
I A] - [[ HLll (only flags are affected)
.!
.. [ HLI [HLI + 1
c:
l! [ BCI [BCI - 1
I-
Compare contents of Accumulator with those of memory block ad-
'"
u
dressed by contents of HL. going from low addresses to high. Stop
.S!
III
when a match is found or when the byte count becomes zero.
CPDR ED B9 2 20/16" X X X X 1 Repeat until [AI =[[ HLll or [ BCI =0:
[A] - [[ HLlI (only flags are affected)
[ HLl [ HLI - 1
IBCI 1
Compare contents of Accumulator with those of memory block ad-
dressed by contents of HL. going from high addresses to low. Stop
when a match is found or when the byte count becomes zero.
CtJ
I
N
CD
Table 3-4. A Summary of the lSO Instruction Set (Continued)
Clock
Stetus
Cycles
Operation Performed
C Z S PIO
AC
N
CPI ED Al 2 16 X X X X 1 rAl - II HLIl (onlV flags are affected)
[ HLl - [HLl + 1
..,- I BC) - ! Bel - 1
t: '0
~
Compare contents of Accumulator with those of memory location
~ t:
.-
addresslid bv contllnts of HL. Increment addrllss and dllcrement ....
t: C 0 byte count.
! ! ~
".r.
CPO ED A9 2 16 X X X X 1 I Al - [[ HLII (onlV flags are affectedI
~ u
[ HL] - [HLl - 1 u ~
o - .
[ BCI - [ BCI - 1
CIIU1
Compare contents of Accumulator with those of memory location
addressed bV contents of HL. Decrement address and byte count
ADD A.(HLI 86 1 7 X X X 0 X D [ Al - [AI + II HLlI or [ Al - ( Al + [( xvI + disp]
A.(xV +disp) l1xll101 86 disp 3 19
.
Add to Accumulator using implied addressing or base relative ad-
dressing.
ADC A.IHLI 8E 1 7 X X X 0 X 0 [ Al - [AJ + II HLlJ + C or [ AI - ( Al + [[ xvi + disp! + C
A,(xV +disp) l1xl11018Edisp 3 19 Add with Carry using implied addressing or base relative address-
u ing.
t:
i
SUB IHLI 96 1 7 X X X 0 X I I Al - rAI - II HLlI Or I Al - [ AI - [( xvI + displ
(XV + disp) l1xl1101 96 disp 3 19 Subtract from Accumulator using implied addressing or base rela-
IZ:
tive addressing.
~
SBC A.IHLI 9E 1 7 X X X 0 X 1 I Al - [ Al - [I i'lL]) - C or [ Al ~ [A] II xvi + disp] - C
0
e
A,(xV+disp) llxl11D19Edisp 3 19 SUbtract with Carry using implied addressing or base relative ad-
:! dressing.
>-
AND IHLI A6 1 7 0 X X P 1 0 [ Al - I Al A [[ HLlI or ( Al ~ [AI A [[ xvi + displ
lii
'0
(XV + d i s p ~ l1xl1101 A6 disp 3 19 AND with Accumulator using implied addressing or base relative e:
0
addressing. u
UI
OR (HL) 86 1 7 0 X X
...
I 0 rAl - [ Al V II HLlJ or [AI ~ [ Al V rr xyJ + disp!
(XV + displ l1x11101 B6 disp 3 19 OR with Accumulator using implied addressing or base relative ad-
dressing.
ff
~
Table 3-4. A Summary of the Z80 Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operend Object Code Byte.
Cycle.
Operation Performed
C Z S P/O
AC N
XOR IHU AE 1 7 0 :,( X P 1 0 I A] - I AI :!J-II HlJl or ( Al - I Al :!J- [[ xy] + displ
>-'ii (XV + disp) 1h1 1101 AE disp 3 19 Exclusive-OR with Accumulator usin9 implied addressing or base
.. .
relative addressing.
o :I
E .=
..
CP (HU BE 1 7 X X X 0 X 1 [ Al - [[ HlJl or [ Al - [[ XV) + disp]
::i S
>-y
(XV + disp) 11x11101 BE disp 3 19 Compare with Accumulator using implied addressing or base rela-
..
tive addressing. Onlv the flags are affected.

" ... c c
INC (HU 34 1 11 X X 0 X 0 II Hlll -II HlJl + 1 or II XV] + disp) - II xy) + disp) + 1
o
u ..
(xy + disp) 11x1110134disp 3 23 Increment using implied addressing or base relative addressing.

Ul';
DEC (HU 35 1 11 X X 0 X 1 [[ Hlll - II HLII - 1 or II xvI + disp] - [( XV) + disp] - 1 II:
(XV + disp) 11x1110135disp 3 23 Decrement using implied addressing or base relative addressing.
&y
7 oj:] RlC (HU CB 06 2 15 X X X P 0 0
~
(XV + disp) 11x11101 CB disp 4 23
II Hlll or [[ XV] + displ
06 Rotate contents of memory location (implied or base relative address-
ing) left with branch Carry
..
LEJ..
oJ:]
..
I7
0
II:
Rl (Hll CB 16 2 15 X X X P 0 0 ..
"
c
(xy + disp) 11x11101 CBdisp 4 23

II Hl)J or [I xvI + disp]
::
16
:c Rotate contents of memory location left through Carry.
Ul
>-
lj
.. o ~
Ii
E
RRC (Hll CB OE 2 15 X X X P 0 0 7
::i
{XV + disp} 11xl1101 CB disp 4 23
[( Hl)J or [( XV] + dispJ
OE
Rotate contents of memory location right with branch Carry.
W
I
W
o
Table 3-4. A Summary of the laO Instruction Set (Continued)
Clock
Statu.
Type Mnemonic Operlnd Object Code Bytes
Cyc'e.
Operation Performed
C 2 S P/O AC N
l:f7
EJJ
o f
RR IHLI CB1E 2 15 X X X P 0 0 ~
Ixy + displ lhlll0l CBdisp 4 23
[[ HLlI or [[ xv1 + disp]
IE
Rolale conlenls of memory location right through Carry
SLA (HLI CB 26 2 15 X X X P 0 0
EJ.. I7
-4 O ~ O
'i;
(XV + disp) lhlll0l CB disp 4 23 II
::I [[ HLll or [[ xvI + disp]
.5
26
IShift contenlS of memory location lefl and clear LSB !Arithmelic ;:
0
g
Shift)
:l
.:l
o I 0
SRA (HLI CB 2E 2 15 X X X P 0 0 7 .- C
II:
I
...
(XV + disp) 1hll101 CB disp 4 23
c
[( HLlI or [( XV] + disp)
co
:: 2E
:E
I/)
>- Shift contents of memory location right and preserlle MSB
;;
E
(Arithmetic Shift).
II
~
SAL (HLl CB 3E 2 15 X X X
p
0 0
o -.J 7 ... 0 I
-8
(xV + disp) llxll101 CBdisp 4 23
[( HLlJ or I[ xvI + disp)
3E
Shift contents of memory location right and clear MSB (logical Shift)
W
I
W
Clock
Status
Cycles
Operation Performed
C Z S PIO A
C
N
LD reg.data OOdddllO VV 2 1 [reg] -data
load immediate into register.

..
LD rp.data16 OOxxOOOl yyyy 3 10 (rp) - datal 6 or [xy] - datal 6 01
'ij
xv.data16 1hlll0l 21 Vyyy 4 14 load 16 bits of immediate data into register pair or Index register.
E
lD (HLI.data 36 yy 2 10 II HLl] - data or [[ xy] + disp] - data
E
-
(xy+ displ. 1h11l01 36 disp VY 4 19 load immediate into memory location using implied or base relative
data addressing
JP label C3 ppqq 3 10 .
I PC) -label
a.
Jump to instruction at address represented by label.
E JR disp 18Idisp-2) 2 12 I PC] - I PCI + 2 + (disp-2)
:::I
Jump relative to p ~ e s e n t contents of Program Counter.
..,
JP (HLI E9 1 4 I PC] - I HLI or [PC) - I XV]
(xy) 1hlll01 E9 2 8 Jump to address contained in Hl or Index register.
CAll label CD ppqq 3 17 [[SP] -l)-[PCIHU]
II SP) - 2) - [ PC(lOI]
[ SP] - [SP] - 2
c:
[PCl -label
..
Jump to subroutine starting at address represented by label. :::I
..
CAll cond.label 11 cccl 00 ppqq 3 10/17 Jump to subroutine if condition is satisfied; otherwise. continue in
a:
"
sequence.
c:
III
RET C9 1 10 [ PCILO)) - I[ SPJI
..
[PCIH1lJ - [[ SP] + 1]
0
[ SP] - I SPJ + 2
. ~
Return from subroutine.
S
~
RET cond 11 cccOOO 1 5/11 Return from subroutine if condition is satisfied; otherwise. continue
:::I
in sequence.
ell
c.>
I
to)
N
Clock
Status
Cycles
Operation Performed
C Z S PIO A
C
N
ADD A,data C6 yy 2 7 X X X 0 X 0 ( Al ~ I A] + data
Add immediate to Accumulator.
ADC A,data CE yy 2 7 X X X 0 X 0 { Al ~ I A] + data + C
Add immediate with Carry,
SUB data 06 yy 2 7 X X X 0 X 1 [ A] - I A] - data
I>
...
Subtract immediate from Accumulator .
~
SBC 0 X [ A] ~ I A] - data - C I> A,data DE yy 2 7 X X X 1
a.
0
Subtract immediate with Carry.
I>
[ A] ~ I A] A data
...
AND data E6 yy 2 7 0 X X P 1 0
:s
AND immediate with Accumulator
I>
E
OR data F6 yy 2 7 0 X X P 1 0 [ A] ~ { A] V data
.5
OR immediate with Accumulator.
XOR data EE yy 2 7 0 X X P 1 0 [A] ~ I A] -Odata
Exclusive-OR immediate with Accumulator.
CP data FE yy 2 7 X X X 0 X 1 [AI - data
Compare immediate data with Accumulator contents; only the
flags are affected.
JP cond,label 11 cccO10 ppqq 3 10 If cond, then I PCI ~ label
Jump to instruction at address represented by label if the condition
is true.
JR C,disp 38 (disp-21 2 7/12 If C = 1, then (PCI ~ (PC) + 2 + (disp - 2)
c
Jump relative to contents of Program Counter if Carry flag is set.
:8
:s
JR NC,disp 30 (disp-21 2 7/12 If C =0, then (PC) - (PC) + 2 + Idisp -2)
c
Jump relative to contents of Program Counter if Carry flag is reset.
0
0
JR Z,disp 28 (disp-2) 2 7/12 If Z = 1, then I PCI ~ [PCl + 2 + (disp -2)
c
0
Jump relative to contents of Program Counter if Zero flag is set.
a.
E JR NZ,disp 20 (disp-2) 2 7/12 If Z = O. then I PCI ~ [PC] + 2 + (disp -2)
:::l
... Jump relative to contents of Program Counter if Zero flag is reset.
DJNZ disp 10 {disp-2l 2 8/13 IB] ~ ( B I - 1
If [B] ." 0, then (PC] + 2 + (disp -21
Decrement contents of B and Jump relative to contents of Program
Counter if result is not O.
W
I
W
W
Clock
Status
Type Mnemonic Operand Object Code Bytes Operation Performed
Cycles
C Z S P/O A
c
N
lD dstsrc 01 dddsss 1 4 [ dstl - [ srcl
Move contents of source register to destination register. Register
designations src and dst may each be A, B, C, 0, E, H or L.
LD A,I ED 57 2 9 X X I 0 0 [AJ-II]
Move contents of Interrupt Vector register to Accumulator.
LD A,R ED SF 2 9 X X I 0 0 [AI-[R)
Move contents of Refresh register to Accumulator.
LD I,A ED 47 2 9 [Il-[A)
Load Interrupt Vector register from Accumulator.
LD R,A ED 4F 2 9 [R)-[A]
Load Refresh register from Accumulator.
LD SP,HL F9 1 6 [SP)- [HLl
..
Move contents of HL to Stack Pointer. >
0
:E LD SP.xy 11x11101 F9 2 10 [SP]- [xy]
;; Move contents of Index register to Stack Pointer.
..
EX OE,HL EB 1 4 [DEI- ~ [HLl
'iii
..
Exchange contents of DE and HL,
~
EX AF,AF' 08 1 4 [ AF] - ~ [ AF'I
..
..
Exchange program status and alternate program status.
..
'iii
.. EXX 09 1 4
CBC) CBC')
Cl:
[DEl - ~ [ DE'l
[ HLl [HL')
Exchange register pairs and alternate register pairs.
Co)
I
Co)
~
Clock
Status
Cycles
Operation Performed
C Z 5 PIO AC
N
ADD A.reg 10000rrr 1 4 X X X 0 X 0 l AI - [AI + [reg]
Add contents of register to Accumulator.
AOC A.reg 10001 rrr 1 4 X X X 0 X 0 [ AI - [AI + [ reg] + C
Add contents of register and Carry to Accumulator.
SUB reg 10010", 1 4 X X X 0 X 1 [ AI - [ AI - [ reg]
Subtract contents of register from Accumulator.
SBC A.reg 10011", 1 4 X X X 0 X 1 [ AI - [ Al - [ reg] - C
Subtract contents of register and Carry from Accumulator.
AND reg 10000rrr 1 4 0 X X P 1 0 [ Al - [AI A [ regl
AND contents of register with contents of Accumulator.
OR reg 10110rrr 1 4 0 X X P 1 0 [ Al - [ AI V [ reg]
..
OR contents of register with contents of Accumulator.
..
XOR reg 10101", 1 4 0 X X P 1 0 [A] - [AI--[ reg]
hclusive-OR contents of register with contents of Accumulator.

Q.
0
CP reg 10111rrr 1 4 X X X 0 X 1 [A] - [reg]
..
! Compare contents of register with contents of Accumulator. Only
..
'0. the flags are affected.
..
~
ADD HL.rp 00nl00l 1 11 X
}
0 [ HLl - [ HLl + [rpl
16-bit add register pair contents to contents of Hl.

..
..
ADC HL.rp [ HLl - [ HLl + [rp] + C
'0. ED Olxxl0l0 2 15 X X X 0
}
0
..
16-bit add with Carry register pair contents to contents of HL. a:
SBC HL.rp ED Olxx0010 2 15 X X X 0
}
1 [ HLl - [ HLl - [rp] - C
16-bit subtract with Carry register pair contents from contents of
HL.
ADD IX.pp DO 00xxl00l 2 15 X ? 0 [ IX] - [ IX) + [ pp]
16-bit add register pair contents to contents of Index register IX
(pp ~ BC. DE. IX, SPI
ADD IV." FD 00nl00l 2 15 X ? 0 [ IV] - [ IV] + [ rrl
1B-bit add register pair contents to contents of Index register IV
(n ~ BC. DE. IV. SPI
Co)
,
Co)
U1
Clock
5t.tu.
Type Mnemonic Operand Object Code Byte. Oper.tion Performed
Cycle.
C Z 5 PIO AC
N
DAA 27 1 4 X X X P X Decimal adjust Accumulator, assuming that Accumulator contents are
the sum or difference of BCD operands.
CPL 2F 1 4 1 1 [A)-[AJ
II
Complement Accumulator (ones complement).
..
NEG ED 44 2 8 X X X 0 X
,
[A)-[AJ +' II
..
II
Negate Accumulator (twos complement).
a.
0
INC OOm'OO 1 4 X X 0 X 0 [ regl - [ reg] + 1
reg
.. Increment register contents.
II
'iiI
INC rp OOxxOO'1 1 6 ( rpJ - [ rp) + , or [ XV] - ( XV) + ,
II
II:
xy '1xlll0l 23 2 10 Increment contents of register or Index register.
DEC reg OUrrr101
,
4 X X 0 X 1 ! reg] - [ reg) - 1
Decrement register contents.
DEC rp 00xx10'1 1 6 [rp] - [rpl - , or! xVJ - [xy] - ,
xv llxl11012B 2 10 Decrement contents of register pair or Index register.
&y7 op
RLCA 07 1 4 X 0 0 4
II
[A]
..
Rotate Accumulator left with branch Carry.
..
..
0
II:
LE]4
oj:] ""
I7
c
RLA 17 1 4 X 0 0
..
:::
:c [AJ
qj
i
Rotate Accumulator left through Carry
..
II
q7 o ~
'co
II
II:
RRCA OF 1 4 X 0 0 ...
[AJ
Rotate Accumulator right with branch Carry.
W
I
Co)
0)
Clock
Statu.
-
Operation Performed
Cycle.
C Z S Ip/O
"c
N
l:f7
:J
oI
RRA IF 1 4 X 0 0 ..
(AJ
'Rotate Accumulator right through Carry.
&y
17
of:J
RlC reg CB OOOOOrrr 2 8 X X X P 0 0 ..
~ I [ reg]
IRotate contents of register left with branch Carry. ~

c
;::
L].
oiJ
g
t7
9
CB 00010rrr 2 B X X X P 0 0

Rl reg
..
~
0 [ reg]
II:
'I::J Rotate contents of register left through Carry,
c
l:j7
O ~
i:
.l:
RRC reg C8 o o 1 rrr 2 8 X X X P 0 0
C/)
..
..
[ reg)
'a.
Rotate contents of register right with branch Carry.
II:
l:j7
oI
.E}J RR reg CB 0001 1m 2 8 X X X p 0 0 ...
[ reg!
Rotate contents of register right through Carry.
SlA reg CB 00100rrr 2 8 X X X P 0 0
El-
I7
...
o J.- 0
[reg]
Shift contents of register left and clear lSB (Arithmetic ShiftJ.
W
I
W
.....
Clock
Statu.
Cycle.
Operation Performed
C Z S PIO
Ac
N
Cj
o I
"0
SRA reg CB 00101rrr 2 8 X X X P 0 0 ...
[ reg]
Shift contents of register right and preserve MSB (Arithmetic Shift).
SRL reg CB 00111rrr 2 8 X X X P 0 0 0
-.1
7
...
o I
--EJ
;;
[ reg]
Shift contents of register right and clear MSB (Logical Shiftl.

:::I
c:
;::
I
c:
0
tJ
-
I 7 4 I 3 o I I 7 4 I 3 o I
RLD ED 6F 2 18 X X P 0 0
..
..
I
~
0 [Al
a::
'tl
c:
:::
Rotate one BCD digit left between the Accumulator and memory loca-
:c
tion (implied addressingl.Contents of the upper half of the Accumula-
III
a
tor are not affected.
J I
I
RRD ED 67 2 18 X X P 0 0
I 7 4 I 3 o I I 7 4 I 3 o I
[AI
[[ HLlJ I
Rotate one BCD digit right between the Accumulator and memory
location (implied addressingl.Contents of the upper half of the Ac-
cumulator are not affected.
to)
I
(0)
co
Table 3-4. A Summary of the zao Instruction Set (Continuedl
Clock
Statu.
Cycle.
Operation Performed
C Z S PIO
Ac
N
BIT b,reg CB 01bbbrrr 2 8 X ? ? 1 0 Z - reglbl
Zero flag contains complement of the selected register bit.
BIT b.IHlI CB 01bbbllO 2 12 X ? ? 1 0 Z - [[ HLlJlbl or Z - [[ xvI + displlb)
b.(xV" disp) 1lx11101 CB disp 4 20 Zero flag contains complement of selected bit of the memory loca-
e:
01bbb110 tion (implied addressing or base relative addressing).
.g
SET b.reg CB 11 bbbrrr 2 8 reglbl - 1
.!
Set indicated register bit.
:::l
a.
SET b.(HU CB 11bbb1 10 2 15 [( HLlJlb) - 1 or [[ XV] + dispJlb) - 1
'i:
II
b.lxV +disp) 1h11101 CB disp 4 23 Set indicated bit of memory location (implied addressing or
~
..
11bbb110
base relative addressing/.
iii
RES b.reg CB 10bbbrrr 2 8 reg(b) - 0
Reset indicated register bit.
RES b.(HU CB 10bbbll0 2 15 [[ HLlJlbl - 0 or [[ XV] + dispJlbl - 0
b.(xV + displ 1lx11 101 CB disp 4 23 Reset indicated bit in memory location limplied addressing or base
10bbb110 relative addressing).
PUSH pr 1'u0101 1 11 ([ SP]-ll - [ pdHIIl
xv 1h11101 E5 2 15 (( SPl-21- [ pr(LOl]
[ SP)- [ SPl-2
Put contents of register pair or Index register on top of Stack and
decrement Stack Pointer.
POP pr lhxOO01 1 10 [ pr(LOll - [[ SPII
.;0: xv 1h11101 E1 2 14 [ pr(HIlI - [[ SPI + 1I
u
[ SP] - [SP] + 2 II
..
(/)
Put contents of top of Stack in register pair or Index register and
increment Stack Pointer.
EX ISPl.HL E3 1 19 [ HI - - [[ SP] + 1]
(SPl,xv llxlllOl E3 2 23 [Ll -- [[ SPII
Exchange contents of HL or Index register and top of Stack.
CAl
,
CAl
CD
Status
Clock
Operetion Performed
Cycles
C Z S P/O
Ac
N
01 F3 1 4 DiSable interrupts,
EI FB 1 4 Enable interrupts.
RST n 1lxxx1 11 1 11 [[ SP)-1] - [PCIHIIl
[[ SP)-2J - [ PCILOI)
..
[ SP] - [ SPI-2
a.
[PCl -18.nl,6
i
Restart at designated location.
S
RETI ED 40 2 14 Return from interrupt.
RETN ED 45 2 14 Return from nonmaskable interrupt.
1M 0 ED 46 2 B Set interrupt mode O. 1. or 2.
1 ED 56 2 B
2 ED 5E 2 B
SCF 37 1 4 1 0 0 C-1
Set Carry flag.
a
II CCF 3F 1 4 X ? 0 C-C
et)
Complement Carry flag.
NOP 00 1 4 No operation - volatile memories are refreshed,
HALT 76 1 4 CPU halts. executes NOPs to refresh volatile memories.
"Execution time shown is for one iteration.
Table 3-5. Instruction Object Codes in Numerical Order
OBJECT CODE INSTRUCTION
00 NOP
01 yyyy LD BC.data16
02 LD (BCl.A
03 INC BC
04
INC B
05
DEC B
06 VV
LD B,data
07 RLCA
08 EX Af.AF
09 ADD HL,BC
OA LD A,lBC)
OB DEC BC
DC INC C
DO DEC C
OEvv
LO C,data
OF RRCA
10 disp-2 OJNZ disp
II yyyy Lo oE,data16
12 LO (DEI,A
13 INC DE
14 INC 0
15
DEC 0
16 vv
to o,data
17 RLA
18 disp-2 JR disp
19 ADD HL,OE
lA LD A,(OE)
18 DEC DE
lC INC E
10 DEC E
IE vv
LO E,data
1f RRA
20 disp-2 JR NZ,disp
21 yyyy LO HL,datal
22 ppqq LO (addr),HL
23 INC HL
24 INC H
25 DEC H
26 vv LO H,data
27 OM
28 disp-2 JR Z,disp
29 ADO HUiL
2A ppqq LO HL,laddr)
28 DEC HL
2C INC L
20 DEC L
2E LO L,data
2f CPL
30 disp-2 JR NC,disp
31 yyyy LO SP,data16
32 ppqq LO (addrl,A
33 INC SP
34 INC (HU
35 DEC iHU
36 vv LO (HU,data
37 SCF
38 JR C.disp
39 ADO HL,SP
3A ppqq LO A,laddr)
38 DEC SP
3C INC A
3D DEC A
3E vv LD A,data
3F CCf
4 Osss LO B,reg
46 LO B,(HLJ
4 lsss LO C,reg
4E LO C,(HU
5 Osss LD O,reg
56 LO O,(HLJ
5 lsss LO E,reg
5E LO E.lHU
6 Osss LO H.reg
66 LO H.lHU
6 lsss LO L,reg
6E LO L,(HU
7 Osss LO IHU,reg
76 HALT
7 lsss LO A,reg
7E LO A,(HU
80m ADD A,reg
86 ADD A,(HLI
8 1m ADC A,reg
8E AOC A,{HLl
90m SUB reg
96 SU8 (HU
9 lrrr sac A,reg
9E SBC A,{HU
AOm AND reg
A6 AND (HU
A 1m XOR reg
AE XOR (HU
BOrn OR reg
B6 OR (HLI
B 1m CP reg
BE CP (HU
CO RET NZ
Cl
pop
BC
C2 ppqq JP NZ,addt
C3 ppqQ JP addr
C4 ppqQ CALL NZ,addr
C5 PUSH BC
C6 vv ADD A,data
C7 RST OOH
C8 RET Z
C9 RET
CA ppqq JP Z,addr
CB 0 Orr, RLC reg
CB06 RLC (HU
ca 0 1,rr RRC reg
CB Of RRC (HU
CB 1 Orrr RL reg
CB 16 RL {HLI
CB 1 1m RR reg
3-40
Table 3-5. Instruction Object Codes in Numerical Order (Continued)
CB IE RR (HU
CB 2 Om SLA reg
CB 26 SLA (HU
CB21m SRA reg
CB 2E SRA (HLI
CB 31m SRL reg
CB 3E SRL (HLI
CB 01bbbm BIT b.reg
CB 01bbbl10 BIT b.IHU
CB IObbbm RES b.reg
CB IObbbl10 RES b.IHU
CB l1bbbm SET b.reg
CB llbbbllO SET b.IHL)
CC PPQq CALL Z,addr
CO PPQq CALL addr
CE yy ADC A,data
CF RST 08H
00 RET NC
01
pop
DE
02 PPQq JP NC,addr
03 yy OUT (portl.A
D4 PPQq CALL NC,addr
05 PUSH DE
Deyy SUB data
07 RST 10H
D8 RET C
09 EXX
DA PPQq JP C,addr
DB yy IN A,(port)
DC ppqq CALL C,addr
DO OOxx 9 ADD IX,pp
DO 21 yyyy LD IX,dllta16
DO 22 PPQq LO (addrl.lX
DO 23 INC IX
DO 2A PPQq Lo IX,(addrl
DO 2B DEC IX
DO 34 disp INC (IX + displ
00 35 disp DEC (IX + diep)
DO 36 disp yy Lo (IX + displ.dlltl
DO 01ddd110 disD LD reg,(lX + diapl
00 I Oass disD Lo (IX + displ.reg
DO S6 disp ADD A,(lX+disp)
DO SE disp ADC A,(IX + diap)
DO 96 disp SUB (IX +disp)
DO 9E disp SBC A'(lX+disp)
DO A8 disp AND (IX + disp)
DO AE disp XOR (IX + displ
DO B6 disp OR (IX + disp)
DO BE disp CP (lX+disp)
00 CB disp 06 RLC (lX+disp)
00 CB disp DE RRC (IX +displ
DO CB disp 16 RL IIX +disp)
DO CB disp 1E RR (IX +diap)
DO CB disp 26 SLA (IX +disp)
DO CB disp 2E SRA (IX +disp)
DO CB disp 3E SRL (lX+displ
DO CB disp 01bbbl 10 BIT b,(lX + displ
DO CB disp lObbbl10 RES b.(lX+displ
DO CB disp l1bbb110 SET b,(lX+displ
DO El pop
IX
DO E3 EX (SPI.IX
DO E5 PUSH IX
DO E9 JP (IX)
DO F9 LD SP.IX
DE yy SBC A,data
OF RST ISH
EO RET PO
E1
pop
HL
E2 PPQq JP PO.addr
E3 EX (SP).HL
E4 PPQq CALL PO.addr
E5 PUSH HL
E6 yy AND data
E7 RST 20H
E8 RET PE
E9 JP IHLI
EA PPQq JP PE,addr
EB EX OE,HL
EC ppqq CALL PE,addr
EO 01dddOOO IN reg,(CI
ED 01sss001 OUT (CI.reg
EO 01xx 2 sse HL,rp
EO 01xx 3 ppqq LD (addrl.rp
EO 44 NEG
ED 45 RETN
ED 01Onnl10 1M m
EO 47 LD I.A
ED 01xx A ADC HL,rp
ED 01xx B ppqq LD rp,(addrl
ED 40 RETI
ED 4F Lo R,A
EO 57 Lo A.I
ED 5F Lo A,R
ED 67 RRO
EO 6F RLO
EO AO LDI
ED Al CPl
ED A2 INI
ED A3 OUTI
EO AS LOO
ED A9 CPO
EO AA iND
ED AS OUTO
ED SO LDIR
ED B1 CPlR
ED 82 INIR
ED B3 OTIR
ED 88 LDDR
ED B9 CPOR
EO SA INDR
EO Be OTOR
EE yy XOR dIIta
EF RST 2SH
3-41

ADC A,data - ADD IMMEDIATE WITH CARRY TO
ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC Pia N
Data
I
Memory
..

xx
.. '" Program
mmmm mmmm+2
""""-
Memory
CE
I
-
yy
mmmm
mmmm+ 1
mmmm+2
mmmm+ 3
ADC A.
--
CE
data
--
yy
1 010
1 1 00
o
001 1
o1 1 1
Add the contents of the next program memory byte and the Carry status to the Ac-
cumulator.
Suppose xx=3A16. yy=7C16. and Carry=O. After the instruction
ADC A.7CH
has executed. the Accumulator will contain 8616:
3A
7C
Carry
1 sets S to 1
No carry. set C to 0
a.If 1= 1. set P/0 to 1
1011 0110
f.J ,esult set Z to 0
"'-------Carry. set AC to 1
Addition instruction. set N to 0
The ADC instruction is frequently used in multibyte addition for the second and subse-
quent bytes.
3-43
ADC A,reg - ADD REGISTER WITH CARRY TO
ACCUMULATOR
F
A
S.C
D.E
H.L
SP
PC
IX
IV
I
R
SZACP/ON!
i
- ~ ~
~
r,
~ x + v y + c
}-l
xx
contents of
A,B.C,D,E,H
orLisvy
- ~
mmmm mmmm + 1
........
I
I
Data
Memory
Program
Memory
10001xxx mmmm
....__--1mmmm + 1
....__--1mmmm + 2
1-__...... mmmm +3
reg
--
ADC A
-..-
10001 xxx
-.-
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Add the contents of Register A. B. C. D, E, H or L and the Carry status to the Accumula-
tor.
Suppose xx=E316, Register E contains A016. and Carry=l. After the instruction
ADC AE
has executed, the Accumulator will contain 8416:
E3
AO
Carry
1 1 1 0 001 1
1010 0000
1
1 sets S to 1
Carry. set C to 1
1000 01 00
t
u
LNon.mo ,.sult. Sol Z to 0
,,",-----No carry. set AC to 0
1 1=0, set P/0 to 0 Addition instruction. set N to 0
The ADC instruction is most frequently used in multibyte addition for the second and
subsequent bytes.
3-44
ADC A,(HL) - ADD MEMORY AND CARRY TO
ADC A,(IX+disp) ACCUMULATOR
ADC A,(IY+disp)
S ZAcP/ON C Data
Q
m
mm+l
mmmm+2
~ - - - t mmmm + 3
IxlXIXlxlOIX
Memory
l
- ~ ~
~ X
_ I.,,:,x,+ YV + C
YV PPQ
,
QQ
PP
- ~ V
Program
mmmm ~ m m m + 1
Memory
I BE mmm
I
mm
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of ADC A.(HU:
ADC A(HU
----
8E
Add the contents of memory location (specified by the contents of the HL register pair)
and the Carry status to the Accumu lator
Suppose xx=E316, yy=A016, and Carry=l. After the instruction
ADC A(HU
has executed, the Accumulator will contain 8416:
E3
AO
Carry
1110 0011
1010 0000
1
1 sets S to 1
Carry. set C to 1
1 1=0. set P/O to 0
1000 0100
.fJ LNon,,.,o cesult. set Z to a
~ - - - - No carry, set AC to 0
Addition instruction, set N to 0
ADC A(lX+disp}
~ - . . -
DO BE d
Add the contents of memory location (specified by the sum of the contents of the IX
register and the displacement digit d) and the Carry to the Accumulator
ADC A(lY+disp)
~ - . -
FD BE d
This instruction is identical to ADC A(lX+displ. except that it uses the IY register in-
stead of the IX register
subsequent bytes.
3-45
ADC HL.rp - ADD REGISTER PAIR WITH CARRY TO HAND L
S Z AC P/O N C
F ~
Data
Memory
A
B.C
D,E
H.L
SP
PC
IX
IY
I
R
Be, DE, HL or SP
:" contain yyyy
xx xx
- ~ x x + y y y y
..""""
+C
mmmm
~
~ m m m + v
I
I
Program
Memory
ED mmmm
01xxl010 mmmm + 1
mmmm+2
t-----t mmmm + 3
K
EDOlxxl010
-..-
00 for rp is register pair BC
01 for rp is register pair DE
10 for rp is register pair HL
11 for rp is Stack Pointer
Add the 16-bit value from either the BC, DE. HL register pair or the Stack Pointer. and
the Carry status, to the HL register pair.
Suppose HL contains A53616, BC contains 104416, and Carry=l. After execution of
ADC HLBC
Addition instruction, set N to 0 011-0=0, set P!O to 0
the HL register pair will cqrtain:
A536 1010{)101 0011 0110
1044 0001 000001000100
Carry 1
1011010101111011
1 sets S tc 1 V t.Ncncmc result. set Z to 0
No carry, set C to 0 1 No carry, set AC to 0
subsequent bytes.
3-46
:xx+vvr
xx
"
Program
mmmm mmmm + 2
""""'- Memory
I C6
I
.....
YV
ADD A,data - ADD IMMEDIATE TO ACCUMULATOR
5 Z AcP/O N C Data
F(E[E[[IE]]JEJ Memory
to
S,C
D,E
H,L
SP
PC
IX
IY
I
R
mmmm
mmmm+ 1
mmmm+2
mmmm+3
ADD A, data
---..-- -.-
C6 yy
Add the contents of the next program memory byte to the Accumulator,
Suppose xx=3A16. yy=7C16. and Carry=O, After the instruction
ADD A,7CH
has executed. the Accumulator will contain 8616:
3A 001 1 1 01 0
7C = 0 1 1 1 1 1 0 0
101U
110
1 sets S 10 1 t LNon-ze""esu,tset Z to 0
No carry. set C to 0 - Carry. set AC to 1
o 1= 1: set P/0 to 1
This is a routine data manipulation instruction,
3-47
Data
Memory
Program
Memory
l0000xxx mmmm
mmmm+ 1
t-----1mmmm + 2
mmmm+3
t-----1
..

r.
} 0001..,
xx

H or L is yy
. r 3>
mmmm _ + 1
I
I
F
ADD A.reg - ADD CONTENTS OF REGISTER TO
ACCUMULATOR
S Z Ac P/O N C
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
ADD reg
-v-" -.-
10000 xxx
000 for reg=B
001 for reg=C
010 for reg""-D
011 for reg=E
100 for reg =H
101 for reg=L
111 for reg=A
Add the contents of Register A. B. C. D. E. H or L to the Accumulator.
Suppose xx=E316. Register E contains A016. After execution of
ADD A.E
1 sets S to 1
Carry. set C to 1
1 1=0. set PIO to 0
the Accumulator will contain 8316:
E3 1 1 1 0 00 1 1
AO = 1 0 1 0 0 0 0 0
1000 0011
r LNon-wo msull. set Z to a
.....-----No carry. set AC to 0
This is a routine data manipulation instruction
3-48
ADD A.(HL) - ADD MEMORY TO ACCUMULATOR
ADD A. (IX+disp)
ADD A.(lY+disp}
d
m
m+ 1
m +2
m + 3
Data
X X X X 0 X
Memory
-
"""" xx
"" xx+yy
yy ppqq+
-
Program
mmmm mmmm+3
ppqq
I--
........
Memory
I 00 mmm
I 86

mmm
d mmm
mmm
S ZACP/ON C

A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
The illustration shows execution of ADD A,(IX+disp).
ADD A,(IX+disp}
--...-- --
DO 86 d
Add the contents of memory location (specified by the sum of the contents of the IX
register and the displacement digit d) to the contents of the Accumulator
Suppose ppqq=4000 16. xx= 1A16. and memory location 400F16 contains 5016, After
the instruction
Addition instruction. set N to 0 oO=O; set P/O to 0
ADD A(lX+OFH)
has executed. the Accumulator will contain 6A16,
lA = 0001 1010
50 = 0 1 0 1 0 0 0 0
o1 1 0 101 0
o sets S to 0 fJ LNon-,em ,""It. set Z to 0
No carry. set C to 0 . No carry. set AC to 0
ADD A(lY+disp)

FD 86 d
This instruction is identical to ADD A(lX+disp). except that it uses the IY register in-
stead of the IX reg ister.
ADD A(HL)
86
This version of the instruction adds the contents of memory location, specified by the
contents of the HL register pair. to the Accumulator.
The ADD instruction is a routine data manipulation instruction
3-49
ADD HL,rp - ADD REGISTER PAIR TO HAND L
Data
Memory
A
B.C
D.E
H.l
SP
PC
IX
IY
I
R
Be, DE, HL or SP
=t." YVVYv.J
-
-,
xx xx II. xxxx + VYYY
mmmm
-

I
I
Program
Memory
OOxxl001 mmmm
mmmm+ 1
1------1mmmm + 2
mmmm+3
1------1
1K
00 xx 1001
--- 00 for rp is register pair BC
Add the 16-bit value from either the BC, DE. HL register pair or the Stack Pointer to the
HL register pair.
Suppose HL contains 034A16 and BC contains 214C16. After the instruction
ADD HLBC
has executed. the HL register pair will contain 249616.
034A 0000 0011 0100 1010
214C = 0010 0001 0100 1100
001aa100 1001 a11 a
No carry. set C to 0....J carry. set AC to a
Addition instruction. set N to a
The ADD HLHL instruction is equivalent to a 16-bit left shift.
3-50
ADD xy,rp - ADD REGISTER PAIR TO INDEX REGISTER
Data
Memory
A
B.C
D.E
H,L
SP
PC
IX
IV
I
R
rr 55
- ~ ~ mmmm mmmm + 2
ppqq t'--.. ..........
..................
-.
" G q q + r r 5 ~
I
Program
Memory
llvl1101 mmmm
OOxx 1001 mmmm + 1
1-__---1mmmm + 2
1-__........ mmmm + 3
The illustration shows execution of ADD IX,DE,
ADD xi,.rp
/Xk
11 \l. 11 a1 OO-- 1001
"'_-----J. ,
ofor Index register=IX 00 for rp is register pair BC
1 for Index register=IY 01 for rp is register pair DE
10 for rp is specified Index register
Add the contents of the specified register pair to the contents of the specified Index
register.
Suppose IY contains 4FF016 and BC contains 000F16 After the instruction
ADD IY.BC
has executed. Index Register IY will contain 4FFF16
3-51
AND data -AND IMMEDIATE WITH ACCUMULATOR
S Z AC P/O N C
F ~
Data
Memory
A
B,C
O,E
H,L
SP
PC
IX
IV
I
R
- ~ ").
xx
_ - I ~ xxyy
-
" mmmm
-
-r mmmm+ 2
Program
.........
Memory
I E6
I '-
yy
mmmm
mmmm+1
mmmm+2
mmmm+3
AND
--..-
data
--
E6 yy
AND the contents of the next program memory byte to the Accumulator.
Suppose xx=3A16- After the instruction
AND 7CH
has executed, the Accumulator will contain 3816.
3A 001 1 1 0 1 0
7C = 0 1 1 1 1 1 0 0
0011 1000
osets S to o..J LThree 1 bits, set PIO to 0
LNon-zero result. set Z to 0
This is a routine logical instruction: it is often used to turn bits "off' For example. the
instruction
AND 7FH
will unconditionally set the high order Accumulator bit to 0,
3-52
AND reg -AND REGISTER WITH ACCUMULATOR
F
A
B.C
D.E
H,L
SP
PC
IX
IY
I
R
s Z ACP/O N C Jt'
~
f,
-...,. xx'vy
"-
}-,oJ'OI
xx
A,B,C,D,E,
H or L is yy
_ Jt'
mmmm
-
Il mmmm + 1
.......
I
I
Data
Memory
Program
Memory
10100xxx mmmm
mmmm+ 1
t-----t
mmmm
+ 2
mmmm+3
t---........
AND reg
~ -..--
10100 xxx
-..-
000 for reg=B
001 for reg=C
010 for reg =0
011 for reg=E
100 for reg =H
101 for reg=L
111 for reg=A
AND the Accumulator with the contents of Register A, B, C, 0, E, H or L. Save the resu It
in the Accumulator.
Suppose xx=E316, and Register E contains A016 After the instruction
AND E
has executed, the Accumulator will contain A016
001 1
0000
0000
1==Two 1 bit>. se1 P/O 10 1
Non-zero result set Z to 0
E3 1 1 1 0
AO = 1010
----......;.--
101 0
sets S to 1.-J
AND is a frequently used logical instruction
3-53
AND (HL) - AND MEMORV WITH ACCUMULATOR
AND (lX+disp)
AND (IV+disp)
+d
Data
m
m+ 1
d mmmm+2
1--;;""'--1 mmmm + 3
x X 1 X 0 0
Memory
- ~ ,-
xx
xxoyy
yy ppqq
........
~
,
Program
mmmm
mmmm+3
ppqq
........
Memory
ppqq+dJ-
I FD mmm
I A6 mmm
S Z AC P/O N C
F ~
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of AND (IY+disp).
AND (IY +disp)
~ -:-r-
FD A6 d
AND the contents of memory location (specified by the sum of the contents of the IY
register and.the displacement digit d) with the Accumulator
Suppose xx=E316, ppqq=400016, and memory location 400F16 contains A016. After
the instruction
AND (IY+OFH)
o1 1 1
0000
0000
LTWO 1 bits, set PIO to 1
E3 1 1 1 a
AO = 1 01 0
-------
1 0 1 0
sets S to 1..J
AND (IX+disp)
~ - . . -
DD A6 d
This instruction is identical to AND (lY+displ. except that it uses the IX register instead
of the IY register.
AND (HL)
--.-..
A6
AND the contents of the memory location (specified by the contents of the HL register
pair) with the Accumulator.
AND is a frequently used logical instruction.
3-54
BIT b,reg - TEST BIT b IN REGISTER reg
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
s tAC P/O N C 1
~
r
b
yyy yyyy,
_ . ~
mmmm mmmm + 2
.......
I
I
BIT b, reg
-.- --.-
--
CB 01 bbb xxx
-.-
--
Bit Tested Register
a 000 000 B
1 001 001 C
2 010 010 0
3 all all E
4 100 100 H
5 101 101 l
6 110 111 A
7 111
Data
Memory
Program
Memory
CB mmmm
01bbbxxx mmmm + 1
mmmm+2
I------t mmmm + 3
Place complement of indicated register's specified bit in Z flag of F register.
Suppose Register C contains 1110 1111. The instruction BIT 4,C will then set the Z flag
to 1, while bit 4 in Register Cremains O. Bit a is the least significant bit.
3-55
BIT b, (HL) - TEST BIT b OF INDICATED MEMORY POSITION
BIT b,(lX+disp)
BIT b, (lY+disp)
5 Z AC Pia N C
F ~
Data
Memory
q
mm
mm+l
mmmm+2
1-----1mmmm + 3
b
.-/-
yyyByyyy
Pi
PP
qq
- ~ :V
Program
mmmm ~ m m m + 2
Memory
I CB mm
I
01bbbll0 mm
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of BIT 4.(HL). Bit a is the least significant bit
BIT b.
(HL)
-...- -,- -,-
CB 01 bbb 110
---
Bit Tested bbb
a 000
1 001
2 010
3 all
4 100
5 101
6 110
7 111
Test indicated bit within memory position specified by the contents of Register HL. and
place bit's complement in Z flag of the F register.
Suppose HL contains 4000H and bit 3 in memory location 4000H contains 1. The in-
struction
BIT 3.(HL)
will then set the Z flag to O. while bit 3 in memory location 4000H remains 1.
2K-
DD CB dOl bbb 110
bb.b is the same as in BIT b.(HL)
Examine specified bit within memory location indicated by the sum of Index Register IX
and disp. Place the complement in the Z flag of the F register.
3-56
Suppose Index Registel' IX contains 4000H and bit 4 of memory location 4004H is O.
The instruction
BIT 4, (IX+4H)
will then set the Z flag to 1, while bit 4 of memory location 4004H remains 0
BIT b,(IY+disp)

bbb is the same as in BIT b,(HU
This instruction is identical to BIT b, (Ix+displ. except that it uses the IY register instead
of the IX register.
CALL label - CALL THE SUBROUTINE IDENTIFIED IN THE
OPERAND
Data
xxxx-2
xxxx-l
xxxx
mmmm
{
mmmm+ 1
...... mmmm + 2
1------4mmmm + 3
Memory
I mm+3
I
-C:..xxxx-2
mm
xxxx,
'#
mmmm

Program
Memory
I CD
I
pp
5 Z Ac PIO N c
FCIIIIIJ
A
S,C
D.E
H.L
SP
PC
IX
IY
R
CALL label
"'-v-' -..-
CD ppqq
Store the address of the instruction following the CALL on the top of the stack: the top
of the stack is a data memory byte addressed by the Stack Pointer Then subtract 2
from the Stack Pointer in order to address the new top of stack. Move the 16-bit address
contained in the second and third CALL instruction object program bytes to the Pro-
gram Counter. The second byte of the CALL instruction is- the low-order half of the ad-
dress, and the third byte is the high-order byte.
Consider the instruction sequence:
CALL
AND
SUBR
7CH
SUBR
After the instruction has executed, the address of the AND instruction is saved at the
top of the stack. The Stack Pointer is decremented by 2. The instruction labeled SUBR
will be executed next
3-57
CALL condition, label - CALL THE SUBROUTINE IDENTIFIED IN
THE OPERAND IF CONDITION IS
SATISFIED
CALL condition. label
T ~ I
11 xxx 100 pp qq
T Condition Relevant Flag
-'-
000 NZ Non-Zero Z
001 Z Zero Z
010 NC Non-Carry C
all C Carry C
100 PO Parity Odd PIO
101 PE Parity Even PIO
110 P Sign Positive S
111 M Sign Negative S
This instruction is identical to the CALL instruction. except that the identified
subroutine will be called only if the condition is $atisfied; otherwise. the instruction se-
quentially following the CALL condition instruction will be executed.
I
CALL : COND.SUBR
_------1 condition not satisfied
AND 7CH
condition
satisfied
SUBR
If the condition is not satisfied. the AND instruction will be executed after the CALL
COND.SUBR instruction has executed. If the condition is satisfied. the address of the
AND instruction is saved at the top of the stack. and the Stack Pointer is decremented
by 2. The instruction labeled SUBR will be executed next.
3-58
CCF - COMPLEMENT CARRY FLAG
S Z AC P/O N C
Fc:r::r::I:IJEJ........ - - - - - - - ~ ~ C : X J
Data
Memory
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
,
mmmm - -. mmmm + 1
---
I
I
Program
Memory
3F mmmm
I-__-Immmm + 1
mmmm+2
I----I
mmmm
+ 3
CCF
3F
Complement the Carry flag. No other status or register contents are affected
3-59
CP data - COMPARE IMMEDIATE DATA WITH
ACCUMULATOR
t
s Z AC Pia N C
Data
Memory

- xx
mmmm

Program
Memory
I FE
I
yy
F
A
B.C
D.E
H.l
SP
PC
IX
IV
I mmmm
R mmmm+ 1
mmmm+2
mmmm+3
CP data
FE yy
Subtract the contents of the second object code byte from the contents of the Ac-
cumulator. treating both numbers as simple binary data. Discard the result; ie.. leave
the Accumulator alone. but modify the status flags to reflect the result of the subtrac-
tion.
Suppose xx=E316 and the second byte of the CP instruction object code contains
AD16 After the instruction
CP OAOH
has executed. the Accumulator will still contain E316. but statuses will be modified as
follows:
11 =0. set PIO to 0
Notice that the resulting carry is complemented.
E3
AO
osets S to 0
No borrow. set C to 0
1110 0011
1010 0000
0100 0011
t
u
LNoo-mo ,e,"lt. set Z to 0
'-------Noborrow. set AC to 0
Subtract instruction. set N to 1
3-60
CP reg - COMPARE REGISTER WITH ACCUMULATOR
F
A
B,C
D,E
H,l
SP
PC
IX
IY
I
R
-
t
1
I's Z AC P/O N C"
- XX-
yy
')
tEIEIEIEIIEl
I
} l
xx
Contents of
____A.B,C,D,E,H
or Lis yy
-

mmmm
-
I
I
Data
Memory
Program
Memory
10111xxx mmmm
mmmm+ 1
mmmm + 2
__-I mmmm + 3
CP reg
--.- --
10111 xxx
-.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 forreg=H
101 forreg=L
111 for reg=A
Subtract the contents of Register A, B, C D. E, H or L from the contents of the Ac-
cumulator. treating both numbers as simple binary data. Discard the result; i.e.. leave
the Accumulator alone. but modify status flags to reflect the result of the subtraction.
Suppose xx=E316 and Register B contains A016. After the instruction
CP B
has executed, the Accumulator will still contain E316, but statuses will be modified as
follows:
E3
AO
a sets S to a
No borrow. set C to a
= 1110 0011
1010 0000
0100 0011
fJ ",suit set Z to 0
.........----No borrow, set AC to 0
1 1=0. set PIC to a
3-61
Subtract instruction, set N to 1
CP (HL) - COMPARE MEMORY WITH ACCUMULATOR
CP (lX+disp)
CP (lY+disp)
qq
mmm
mmm+1
mmmm+2
t-----t mmmm + 3
t
;' S
Z AC pia N C Data
~
Memory
xx _r ""'"
yy
1
'- xx-yy -/ _
pp qq
- ~ V
Program
mmmm _ I....:.mmm +'
Memory
I BE m
I
m
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of CP (HL):
CP (HL)
~
BE
Subtract the contents of memory location (specified by the contents of the HL register
pair) from the contents of the Accumulator. treating both numbers as simple binary
data Discard the result: ie.. leave the Accumulator alone. but modify status flags to
reflect the resu It of the subtraction
Suppose xx=E316 and yy=A016 After execution of
CP (HL)
the Accumulator will still contain E316. but statuses will be modified as follows:
E3 1 1 1 0 00 1 1
AO = 0 1 1 0 0 0 0 a
0100 0011
a sets S to a t
U
LNOn",em ,esult. set Z to 0
No borrow. set C to a . No borrow. set AC to-O
1 1=0. set P/O to a
Notice that the resu Iting carry is complemented.
CP (IX+disp)
---...-- -..--
DO BE d
3-62
Subtract the contents of memory location (specified by the sum of the contents of the
IX register and the displacement value d) from the contents of the Accumulator. treat-
ing both numbers as simple binary data. Discard the result; i.e., leave the Accumulator
alone, but modify status flags to reflect the result of the subtraction.
CP (IY+disp)
---
FD BE d
This instruction is identical to CP (IX+displ. except that it uses the IY register instead of
the IX register.
CPO-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT ADDRESS AND BYTE COUNTER
yy ppqq
Data
Memol')!
ED mmmm
A9 mmmm+ 1
mmmm+2
......----1 mmmm + 3
5 Z Ac P/O N C
FfXT'XTXT'"J'i'n 5et if 8C-l O.
reset otherwise
A xx
B,C tt uu
D.E

H.l SP ..
PC mmmm Program
IX Memol')!
IV I----------------t
I
R
CPD
'-...-'
ED A9
Compare the contents of the Accumu lator with the contents of memory location
(specified by the HL register pairl. If A is equal to memory. set Z flag. Decrement the HL
and BC register pairs. (BC is used as the Byte Counter)
3-63
Suppose xx=E316. ppqq=400016. BC contains 000116. and yy=A016. After the in-
struction
CPO
has executed, the Accumulator will still contain E316. but statuses will be modified as
follows:
E3 1 1 1 0 001 1
AO 1 01 0 0000
0100 0011
o sets S to O.J fJ LNon-mo 'e,,". set Z to 0
'-------No borrow. set AC to 0
The P/O flag will be reset
because BC-1 =0
Subtract instruction involved.
set N to 1
Carry not affected.
The HL register pair will contain 3FFF16, and BC=O
CPDR-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT ADDRESS AND BYTE COUNTER.
CONTINUE UNTIL MATCH IS FOUND OR BYTE
COUNTER IS ZERO
CPOR
--..--
ED B9
This instruction is identical to CPO. except that it is repeated until a match is found or
the byte counter is zero. After each data transfer, interrupts will be recognized and two
refresh cycles will be executed.
Suppose the HL register pair contains 500016, the BC register pair contains 00FF16.
the Accumu lator contains F916' and memory has contents as follows:
Location Contents
5000
16 AA16
4FFF16 BC16
4FFE16 1916
4FFD16 7A16
4FFC16 F916
4FFB16 0016
After execution of
CPOR
the P/O flag will be 1. the Z flag will be 1, the HL register pair will contain 4FFB16, and
the BC register pair will contain 00FA16.
3-64
CPI-COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT BYTE COUNTER.
INCREMENT ADDRESS
S Z AC P/O N C

otherwise
A XX
B.C tt uu
D,E
H.L PP QQ
SP
PC mmmm
IX
IY
I
R
CPI
ED A1
Data
Memory
YY PPQQ
Program
Memory
ED mmmm
Al mmmm+ 1
...-.----1 mmmm + 2
.....__--1 mmmm + 3
Compare the contents of the Accumulator with the contents of memory location
(specified by the HL register pair). If A is equal to memory, set the Z flag. Increment the
HL register pair and decrement the BC register pair (BC is used as Byte Cou nter)
Suppose xx=E316. ppqq=400016. BC contains 003216. and yy=E316 After the in-
struction
CPI
has executed. the Accumulator will still contain E316, but statuses will be modified as
follows:
E3 1 1 1 1 0 a 1 1
-E3 0 0 0 0 1 1 0 1
0000 0000
osets S to 0--1 fJ LResult is O. set Z to 1
1,...-----No borrow. set AC to 0
The PIO flag will be set
because BC-1 l' O.
Subtract instruction involved.
set N to 1,
Carry not affected
The HL register pair will contain 400116. and BC will contain 003116.
3-65
CPIR - COMPARE ACCUMULATOR WITH MEMORY.
DECREMENT BYTE COUNTER.
INCREMENT ADDRESS.
CONTINUE UNTIL MATCH IS FOUND
OR BYTE COUNTER IS ZERO
CPIR
----
ED B1
This instruction is identical to CPI. except that it is repeated until a match is fou nd or
the byte counter is zero. After each data transfer interrupts will be recognized and two
refresh cycles will be executed.
Suppose the HL register pair contains 45016. the BC register pair contains 00FF16.
the Accumulator contains F916. and memory has contents as follows:
Location Contents
4500
16 AA16
4501
16
15
16
4502
16 F916
After execution of
CPIR
the P10 flag will be 1. and the Z flag will be 1. The HL register pa ir will conta in 450316.
and the BC register pair will contain OOFC16.
3-66
CPL - COMPLEMENT THE ACCUMULATOR
S Z ACP/O N C
FCI:IIIIrIJ
Data
Memory
A
B.C
D.E
H,L
SP
PC
IX
IV
I
R
- ~
~
xx xx
"""-
"
mmmm mmmm+ 1
"""-
I
I
Program
Memory
2F mmmm
1-----1 mmmm + 1
I---......t mmmm + 2
I---......t mmmm + 3
CPL
2F
Complement the contents of the Accumu lator. No other register's contents are
affected.
Suppose the Accumu lator contains 3A16. After the instruction
CPL
has executed, the Accumulator will contain C516
3A = 001 1
Complement = 1 1 00
1 0 1 0
o1 01
This is a routine logical instruction. You need not use it for binary subtraction, there are
special subtract instructions (SUB, SBC)
3-67
DAA - DECIMAL ADJUST ACCUMULATOR
S Z AC P/O N C

Data
Memory
A
B.C
D,E
H,L
SP
PC
IX
IY
I
R
xx
-
""-decimal
V mmmm _ I....:,mmm + 1
I
I
Program
Memory
27 mmmm
mmmm+ 1
1-----1mmmm + 2
1--__-1 mmmm + 3
DAA
27
Convert the contents of the Accumulator to binary-coded decimal form. This instruc-
tion should only be used after adding or subtracting two BCD numbers: ie, look upon
ADD DAA or ADC DAA or INC DAA or SUB DAA or SBC DAA or DEC DAA or NEG DAA
as compound, decimal arithmetic instructions which operate on BCD sources to gener-
ate BCD answers.
Suppose the Accumu lator contains 3916 and the B reg ister contai ns 4716 After the i n-
structions
ADD B
DAA
have executed, the Accumulator will contain 8616, not 8016
Z80 CPU logic uses the values in the Carry and Auxiliary Carry, as well as the Ac-
cumulator contents, in the Decimal Adjust operation.
3-68
DEC reg - DECREMENT REGISTER CONTENTS
SZACP/ONC
F ~
Data
Memory
_&
00 xxx 101
-..-
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
~ Coo,""" of Po,
B. C. D. E. H.
or Lis yy
- ~ V mmmm
...,::mmm + 1
I
I
Program
Memory
OOxxxl01 mmmm
mmmm+ 1
t----1mmmm + 2
mmmm+3
t----t
000 for reg=B
001 for reg=C
010 forreg=D
011 for reg=E
100 for reg= H
101 for reg=L
111 for reg=A
Subtract 1 from the contents of the specified register.
Suppose Register A contains 5016. After execution of
DEC A
Register A will contain 4F16
3-69
DEC rp - DECREMENT CONTENTS OF SPECIFIED REGISTER
DEC IX PAIR
DECIY
S Z AC P/O N C
Fc::o:IIIl
Data
Memory
A
RC
D.E
H.L
SP
PC
IX
IY
I
R
Co,..,,, of Be
DE, HL or SP
is yyyy
mmmm

I
I
Program
Memory
OOxxl0ll mmmm
mmmm+ 1
I-----fmmmm + 2
I-----fmmmm + 3
The illustration shows execution of DEC rp:
]X
00 xx 1011
Subtract 1 from the 1 value contained in the specified register pair. No status flags
are affected
Suppose the Hand L registers contain 2F001 6 After the instruction
DEC HL
has executed. the Hand L registers will contain 2EFF16.
DEC IX
-.---
DD 28
Subtract 1 from the 16-bit value contained in the IX register
DEC IY
--....-
FD 28
Subtract 1 from the 16-bit value contained in the IY register.
Neither DEC rp. DEC IX nor DEC IY affects any of the status flags. This is a defect in the
Z80 instruction set. inherited from the 8080. Whereas the DEC reg instruction is used in
iterative instruction loops that use a counter with a value of 256 or less. the DEC rp
(DEC IX or DEC IY) instruction must be used if the counter value is more than 256. Since
the DEC rp instruction sets no status flags. other instructions must be added to simply
370
test for a zero resu It. This is a typicaI loop form:
LOOP
LD DE.DATA ;LOAD INITIAL 16-81T COUNTER VALUE
;FIRST INSTRUCTION OF LOOP
DEC
LD
OR
JP
DE
A.D
E
NZ,LOOP
;DECREMENT COUNTER
;TO TEST FOR ZERO. MOVE D TO A
;THEN OR A WITH E
;RETURN IF NOT ZERO
DEC (HL) - DECREMENT MEMORY CONTENTS
DEC (lX+disp)
DEC (IV+disp)
Data
mmm
mmm+1
mmmm+2
...------1 mmmm + 3
Cyy-1
yy
P
f
-
pp qq
mmmm
~ m m m + ~
Program
Memory
I 35
m
I m
S Z AC P/O N C
F ~
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of DEC (HL):
DEC (HL)
'-v-"
35
Subtract 1 from the contents of memory location (specified by the contents of the HL
reg ister paid.
Suppose ppqq=450016. yy=5F16 After execution of
DEC (HL)
memory location 450016 will contain 5E16.
5F = 0 1 0 1 1 1 1 1
-01 = 1 1 1 1 1 1 1 1
I?]1 0 1 1 1 1 0
~ ~ a sets S to O...jJ r LNoo-mo 'esult. set Z to a
1 1=0. set PIO to 0 - No borrow. set AC to a
3-71
DEC (IX+disp)
'-v-' --
DD 35 d
Subtract 1 from the contents of memory location (specified by the sum of the contents
of the IX register and the displacement value d)
DEC (IY+disp)
~ - . . -
FD 35 d
This instruction is identical to DEC (IX+disp), except that it uses the IY register instead
of the IX register
01 - DISABLE INTERRUPTS
S Z AC P/O N C
FCIIIID
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
..,
mmmm mmmm+ 1
........
I
I
01
-.-'
F3
Data
~
Program
Memory
F3 mmmm
.....__-1 mmmm + 1
....----1 mmmm + 2
.....__-1 mmmm + 3
When this instruction is executed, the maskable interrupt request is disabled and the
INT input to the CPU will be ignored, Remember that when an interrupt is
acknowledged, the maskable interrupt is automatically disabled
The maskable interrupt request remains disabled until it is subsequently enabled by an
EI instruction,
No registers or flags are affected by this instruction
3-72
DJNZ disp - JUMP RELATIVE TO PRESENT
CONTENTS OF PROGRAM COUNTER IF
REG B IS NOT ZERO
s Z ACPIO N C
xx-l
~
Data
c::a::r::co
Memory
j
xx'
- .......mmmm+
mmmm
~ d d - 2 ) + 2,
Program
Memory
I
10
L dd-2
F
A
B.C
D.E
H.l
SP
PC
IX
IV
~ mmmm
R mmmm+ 1
mmmm+2
mmmm+3
DJNZ disp
~ --
10 dd-2
Decrement Register B If remaining contents are not zero. add the contents of the DJNZ
instruction object code second byte and 2 to the Program Counter. The jump is
measured from the address of the instruction operation code. and has a range of -126 to
+129 bytes. The Assembler automatically adjusts for the twice-incremented PC.
If the contents of B are zero after decrementing. the next sequential instruction is ex-
ecuted.
The DJNZ instruction is extremely useful for any program loop operation, since the one
instruction replaces the typical "decrement-then-branch on condition" instruction se-
Quence.
EI- ENABLE INTERRUPTS
S Z AC PIO N C
F ~
Data
Memory
A
B,C
D.E
H.L
SP
PC
IX
IV
I
R
--
mmmm mmmm + 1
"""""-
I
I
Program
Memory
FB mmmm
mmmm+ 1
t-----t mmmm + 2
t-----t mmmm + 3
3-73
EI
FB
Execution of this instruction causes interrupts to be enabled. but not until one more in-
struction executes.
Most interrupt service routines end with the two instructions:
EI
RET
;ENABLE INTERRUPTS
;RETURN TO INTERRUPTED PROGRAM
If interrupts are processed serially. then for the entire duration of the interrupt service
routine all maskable interrupts are disabled - which means that in a multi-interrupt
application there is a significant possibility for one or more interrupts to be pending
when any interrupt service routine completes execution.
If interrupts were acknowledged as soon as the EI instructions had executed, then the
Return instruction would not be executed. Under these circumstances, returns would
stack up one on top of the other - and unnecessarily consume stack memory space.
This may be illustrated as follows:
Interrupt
Interrupt service routine
By inhibiting interrupts for one more instruction following execution of EI. the zeo CPU
ensures that the RET instruction gets executed in the sequence:
EI
RET
;ENABLEINTERRUPTS
;RETURN FROM INTERRUPT
It is not uncommon for interrupts to be kept disabled while an interrupt service routine
is executing. Interrupts are processed serially:
Lt'""""s ~
3-74
Lt'""'rus: ~
EX AF,AF'-EXCHANGE PROGRAM STATUS AND ALTERNATE
PROGRAM STATUS
F'
A'
B',C'
D',E'
H',L'
Alternate
R . t S t
S Z ACP/O N C
- "\
egis er e
I I I I I I
I
-if
I
-, V Program
mmmm ~ m m m + 1
Memory
I DB mmmm
I
mmmm + 1
F
A
S.C
D.E
H.L
SP
PC
IX
IV
I
R
mmmm +2
t------4I mmmm + 3
EX AF,AF'
~
08
The two-byte contents of register pairs AF and AT are exchanged.
Suppose AF contains 4F9916 and A'F' contains 10AA16. After execution of
EX AF,AF'
AF will contain 1OAA16 and AF' will contain 4F9916.
3-75
EX DE,HL - EXCHANGE DE AND HL CONTENTS
S Z AC P/O N C
Fco:IID
Data
Memory
A
S,C
D.E
H,L
SP
PC
IX
IY
I
R
pp qq
,)
xx yy
-
..,
mmmm mmmm+ 1
"""'"
I
I
Program
Memory
EB mmmm
I--__---tmmmm + 1
mmmm+2
t----t
mmmm
+ 3
EX DE.HL
---...-
EB
The 0 and E registers' contents are swapped with the Hand L registers' contents
Suppose pp=0316, qq=2A16. xx=4116 and yy=FC16 After the instruction
EX DE,HL
has executed, H will contain 0316. L will contain 2A16. 0 will contain 4116 and E will
contain FC16
The two instructions:
EX DE.HL
LD A,(HU
are eq uivalent to:
LD A,(DE)
but if you want to load data addressed by the 0 and E register into the B register.
EX DE.HL
LD B.(HL)
has no single instruction equivalent.
3-76
EX (SP).HL - EXCHANGE CONTENTS OF REGISTER AND
EX (SP).IX TOP OF STACK
EX (SP).IY
Data
ssss
ssss + 1
ssss + 2
mmmm
mmmm+ 1
mmmm+2
I-------t
mmmm
+ 3
Memory
-
-
qq
"
-
pp
K
xx YV
ssss
-, V
mmmm ~ m m m + 1
Program
Memory
I E3
I
S Z AC P/O N C
Fo:r:IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
The illustration shows execution of EX (SP).HL
EX (SP).HL
~
E3
Exchange the contents of the L register with the top stack byte. Exchange the contents
of the H register with the byte below the stack top.
Suppose xx=2116. yy=FA16. pp=3A16' qq=E216 After the instruction
EX (SP).HL
has executed, H will contain 3A16. L will contain E216 and the two top stack bytes will
contain FA16 and 2116 respectively.
The EX (SP).HL instruction is used to access and man ipu late data at the top of the stack
EX (SP).IX
~
DO E3
Exchange the contents of the IX register's low-order byte with the top stack byte, Ex-
change the IX register's high-order byte with the byte below the stack top.
EX (SP).IY
~
FD E3
This instruction is identical to EX (SPl.IX. but uses the IY register instead of the IX
register.
3-77
EXX - EXCHANGE REGISTER PAIRS AND ALTERNATE
REGISTER PAIRS
S ZACP/ON C
Fc::r:::r::IIIJ
Altemate
Register Set
Program
Memory
09 mmmm
I--......;;;.;;......... mmmm + 1
mmmm+2
t----t mmmm + 3
F'
A'
{
I----+--........ BC'
D.E
t-------t----f
H
L
}4
..
-
~ m m m + ~ mmmm
I
I
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
EXX
09
The contents of register pairs BC, DE and HL are swapped with the contents of register
pairs B'C', DE. and H'L',
Suppose register pairs BC, DE and HL contain 490116, 5F0016 and 725116 respec-
tively, and register pairs B'C DE. H'L' contain 000016, 10FF16 and 333316 respec-
tively After the execution of
EXX
the registers will have the following contents:
BC: 000016; DE: 10FF16; HL: 333316;
B'C': 490116; D'E': 5F0016; H'L': 725116
This instruction can be used to exchange register banks to provide very fast interrupt
response times,
3-78
HALT
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
S,C
D,E
H,L
SP
PC
IX
IV
I
R
-
.,
mmmm mmmm+ 1
- ........
I
I
HALT
76
Program
Memory
76 mmmm
mmmm+ 1
t-----t mmmm + 2
t-----t mmmm + 3
When the HALT instruction is executed, program execution ceases. The CPU requ ires
an interrupt or a reset to restart execution. No registers or statuses are affected:
however. memory refresh logic continues to operate.
3-79
1M 0 - INTERRUPT MODE 0
S Z AC PIO N C
FO::C:O::O
Data
Memory
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
-
~
mmmm - -. mmmm + 2
.........
-.
r
IMO
'-..,,-'
ED 46
Program
Memory
ED mmmm
46 mmmm+ 1
I-__~ mmmm +2
I-__~ mmmm +3
This instruction places the CPU in interrupt mode a In this mode. the Interrupting
device will place an instruction on the Data Bus and the CPU will then execute that in-
struction No registers or statuses are affected
1M 1 -INTERRUPT MODE 1
1M 1
'-..,,-'
ED 56
This instruction places the CPU in interrupt mode 1 In this mode. the CPU responds to
an interrupt by executing a restart (RST) to location 003816.
1M 2 - INTERRUPT MODE 2
1M 2
---
ED 5E
This instruction places the CPU in Interrupt mode 2 In this mode, the CPU performs an
indirect call to any specified location in memory. A 16-bit address is formed using the
contents of the Interrupt Vector (I) register for the upper eight bits, while the lower
eight bits are supplied by the interrupting device. Refer to Chapter 12 for a full descrip-
tion of interrupt modes. No registers or statuses are affected by this instruction
3-80
IN A,(portl-INPUT TO ACCUMULATOR
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
s Z Ac PIO N C
t
Data
CIIIIIJ
I I/O port yy j4--
Memory
I
-
- ., V Program
mmmm
~ m m m + 2
Memory
I DB
I
yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
INA
---
DB
(port)
'"-v-'
yy
Load a byte of data into the Accumulator from the I/O port (identified by the second IN
instruction object code byte)
Suppose 3616 is held in the buffer of I/O port 1A16 After the instruction
IN A,(1 AH)
has executed, the Accumulator will contain 3616
The IN instruction does not affect any statuses
Use of the IN instruction is very hardware dependent Valid I/O port addresses are
determined by the way in which I/O logic has been implemented. It is also possible to
design a microcomputer system that accesses external logic using memory reference
instructions with specific memory addresses
3-81
INC reg -INCREMENT REGISTER CONTENTS
S Z AC plo N C
F I:EIEIEIEI]D
Data
Memory
A
BC
DE
H.L
SP
PC
IX
IY
I
R
~ Co,,,,,, of A.
B, C. D, E. H or
Lis yy
_/ ~
mmmm :-.0 - . ~ m m m + 1
I
I
Program
Memory
OOxxx 100 mmmm
1-----1mmmm + 1
mmmm+2
t-----1 mmmm + 3
INC reg
I ~
00 xxx 100
000 for reg =8
001 for reg=C
010 for reg=D
all forreg=E
100 for reg =H
101 for reg=L
111 for reg=A
Add 1 to the contents of the specified register
Suppose Register E contains A816 After execution of
INC E
Register E will contain A916
3-82
INC rp - INCREMENT CONTENTS OF SPECIFIED REGISTER PAIR
INC IX
INC IV
S Z AC P/O N C
FCIIII:IJ
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
} Coo""" of DC.
DE, HL or SP
......isyyyy
- I ~ m m m + v
mmmm
I
I
Data
Memory
Program
Memory
OOxxOO11 mmmm
mmmm+ 1
t-----t
mmmm
+ 2
~ - - - - f m m m m + 3
The illustration shows execution of INC rp
~
00 xx 0011
Add 1 to the 16-blt value contained in the specified register pair No status flags are
affected
Suppose the 0 and E registers contain 2F7A16 After the instruction
INC DE
has executed, the D and E reg isters wi II contain 2F7B 16
INC IX
.-..--
DO 23
Add 1 to the 16-bit value contained in the IX register.
INC IY
.-..--
FD 23
Add 1 to the 16-bit value contained in the IY register.
Just like the DEC rp, DEC IX and DEC IY, neither INC rp, INC IX nor INC IY affects any
status flags This is a defect In the Z80 instruction set inherited from the 8080.
3-83
qq+d
mmm
mmm+l
mmm+2
mmm+3
Data
x X X X 0
Memory
Cyy+l
.......
-
...._-
yy pp
,/
- ~
Program
mmmm
-
mmmm + 3
ppqq --
.......
Memory
DO
m
I 34
m
-..G
Pqq
+
d
)=
d
m
m
-
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
INC (HL) - INCREMENT MEMORY CONTENTS
INC (IX+disp)
INC (lY+disp)
S Z AC PIO N C
F []J]IEI]]]I]
The illustration shows execution of INC (IX+d):
INC (IX+disp)
~ -.-
DD 34 d
Add 1 to the contents of memory I"cation (specified by the sum of the contents of
Register IX and the displacement value d),
Suppose ppqq =400016 and memory location 400F16 contains 3616 After execution
of the instruction
INC (IX+OFH)
memory location 400F16 will contain 3716,
36 = 0 0 1 1 0 1 1 0
1
Addition instruction, set N to a
O 0=0, set P/O to
001 1 0 1 1 1
osets S to 0 r LNo,-mo 'esult. set Z to 0
Carry status not affected - No carry, set AC to a
INC (IY+disp)
--..- -.-
FD 34 d
This instruction is identical to INC (IX+dispL except that it uses the IY register instead
of the IX register.
INC (HL)
~
34
Add 1 to the contents of memory location (specified by the contents of the HL register
pair),
3-84
IND -INPUT TO MEMORY AND DECREMENT POINTER
m
m+ 1
I-__---Immmm + 2
mmmm + 3
1------1
s Z AC PIO N C
Cxx-1 ~
Data
cm::G:GIIIJ
,..
,.r I/O port yy I
Memory
I
- ppqq
xx yy ~
~ ~ P p q q - 1
pp qq
Program
mmmm
mmmm+'V
..... Memory
I ED mmm
I AA mmm
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
IND
--.--
ED AA
Input from 1/0 port (addressed by Register C) to memory location (specified by HL)
Decrement Registers Band HL.
Suppose xx=0516, yy= 1516, ppqq=240016. and 1916 is held In the buffer of 1/0 port
1516 After the instruction
IND
has executed. memory location 240016 will contain 1916, The B register will contain
0416 and the HL reg ister pa ir 23FF16
INDR -INPUT TO MEMORY AND DECREMENT POINTER
UNTIL BYTE COUNTER IS ZERO
INDR
--...--
ED BA
INDR is identical to IND. but is repeated until Register B=O.
Suppose Register B contains 0316. Register C contains 1516. and HL contains 240016
The following sequence of bytes is available at 1/0 port 1516:
17
16. 5916 and AE16
After the execution of
INDR
the HL register pair will contain 23FD16 and Register B will contain zero. and memory
locations will have contents as follows:
Location
2400
23FF
23FE
Contents
17
16
59
16
AE16
This instruction is extremely useful for loading blocks of data from an input device into
memory.
3-85
INI-INPUT TO MEMORY AND INCREMENT POINTER
m
m+ 1
t----I mmmm + 2
t----I mmmm +3
s Z AC PIO N C
Cxx-l ~
Data
o:::o:::DJ

....... I/O port yy I
Memory
I
ppqq
..
xx yy ~
. ~
Ppqq+l
pp qq
.....
mmmm
~ V
Program
~ m m m + 2
Memory
I ED mmm
I A2 mmm
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
INI
'-v-'
ED A2
Input from I/O port (addressed by Register C) to memory location (specified by HL)
Decrement Register B: increment register pair HL
Suppose xx=:0516. yy=: 1516, ppqq=:240016. and 1916 is held in the buffer of I/O port
15
16
After the instruction
INI
has executed. memory location 240016 will contain 1916 The B register will contain
0416 and the HL register pair 240116
INIR - INPUT TO MEMORY AND INCREMENT POINTER
UNTIL BYTE COUNTER IS ZERO
INIR
'-v-'
EO B2
INIR is identical to INI. but is repeated until Register 8=0,
Suppose Register B contains 0316, Register C contains 1516. and HL contains 240016
The following sequence of bytes is available at I/O port 1516
1716.5916 and AE16
After the execution of
INIR
the HL register pair will contain 240316 and Register Bwill contain zero. and memory
locations will have contents as follows:
Location
2400
2401
2402
Contents
17
16
59
16
AE16
This instruction is extremely useful for loading blocks of data from a device into memo-
ry,
3-86
IN reg,(C) -INPUT TO REGISTER
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC PIO N C
t
m:m::J]J]D
---
I/O port vv I
-
t
\'y
A B, C, D, E,
H or L
- mmmm
_ \.::mmm + 2
I
I
Data
Memory
Program
Memory
ED mmmm
01xxxOOO mmmm + 1
mmmm+2
mmmm + 3
IN reg. (C)
K
ED 01 xxx 000
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
110 for setting of status flags without
changing registers
Load a byte of data into the specified register (reg) from the 1/0 port (identified by the
contents of the C register).
Suppose 4216 is held In the buffer of 1/0 port 3616. and Register C contains 3616.
IN D.(C)
has executed. the 0 register will contain 4216
During the execution of the instruction. the contents of Register B are placed on the top
half of the Address Bus. making it pOSSible to extend the number of addressable 1/0
ports.
3-87
JP label - JUMP TO THE INSTRUCTION IDENTIFIED
IN THE OPERAND
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
B.C
O.E
H.l
SP
PC
IX
IY
I
R
mmmm
r
ppqq :)
Program
- Memory
I C3
I
,
qq
t
pp
mmmm
mmmm+ 1
mmmm+2
mmmm+3
JP label
-.- '-v-'
C3 ppqq
Load the contents of the Jump instruction object code second and third bytes into the
Program Counter; this becomes the memory address for the next instruction to be ex-
ecuted. The previous Program Counter contents are lost.
In the following sequence
JP NEXT
AND 7FH
NEXT CPL
The CPL instruction will be executed after the JP instruction The AND instruction will
never be executed. unless a Jump instruction somewhere else in the instruction se-
quence jumps to this instruction
3-88
condition
satisfied
JP condition, label - JUMP TO ADDRESS IDENTIFIED IN THE
OPERAND IF CONDITION IS
SATISIFED
JP condo label
Kl
11 cc 010 ppqq
I Condition Relevant Flag
000 NZ Non-Zero Z
001 Z Zero Z
010 NC No Carry C
011 C Carry C
100 PO Parity Odd Pia
101 PE Parity Even Pia
110 P Sign Positive S
111 M Sign Negative S
This instruction is identical to the JP instruction. except that the jump will be per-
formed only If the condition is satisfied: otherwise. the Instruction sequentially follow-
Ing the JP condition instruction will be executed
Consider the instruction sequence
JP COND.LABEL
---------'11 condition not satisfied
AND +7CH
LABEL OR B
After the JP cond.label instruction has executed. if the condition is satisfied then the
OR instruction will be executed If the condition IS not satisfied. the AND instruction.
being the next sequential instruction. IS executed
3-89
JP (HL) - JUMP TO ADDRESS SPECIFIED BV CONTENTS
JP (IX) OF 16-BIT REGISTER
JP (IV)
S Z Ac P!O N C
FCIIIIIJ
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
pp qq
P
mmmm
I
I
Data
Program
Memory
E9 mmmm
~ __--1 mmmm + ,
mmmm+2
J - - - ~ mmmm + 3
The illustration shows execution of JP (HL):
JP (HL)
-...--
E9
The contents of the HL register pair are moved to the Program Counter: therefore. an
implied addressing Jump is performed.
The instruction sequence
LD H.ADDR
JP (HL)
has exactly the same net effect as the single instruction
JP ADDR
Both specify that the Instruction with label ADDR is to be execu ted next
The JP (HL) instruction is useful when you want to increment a return address for a
subroutine that has multiple returns
Consider the following call to subroutine SUB:
SUB
ERR
CALL
JP
:CALL SUBROUTINE
:ERROR RETURN
:GOOD RETURN
Using RET to return from SUB would return execution of JP ERR: therefore. if SUB ex-
ecutes without detecting error conditions. return as follows:
POP
INC
INC
INC
JP
HL
HL
HL
HL
{HL)
:POP RETURN ADDRESS TO HL
:ADD 3 TO RETURN ADDRESS
.RETURN
JP (IX)
-.,,-'
DD9
This instruction is identical to the JP {HL) instruction. except that it uses the IX register
3-90
instead of the HL register pair.
JP (lY)
'-.,.-'
FD E9
This instruction is identical to the JP (HU instruction. except that it uses the IY register
instead of the HL register pair.
JR C,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF CARRY IS SET
JR C, disp
'-.,.-' -..-
38 dd-2
This instruction is identical to the JR disp instruction. except that the jump is only ex-
ecuted if the Carry status equals 1: otherwise. the next instruction is executed
In the following instruction sequence:
AND
JR
4002
4000
C=1
C.$+8
_---------'1 c=o
, 7FH
- ~ ~ 4 0 0 8 OR B
After the JR (,$+8 instruction. the OR instruction is executed if the Carry status equals
1. The AND instruction is executed if the Carry status equals 0
3-91
JR disp - JUMP RELATIVE TO PRESENT CONTENTS OF
PROGRAM COUNTER
S Z AC P/O N C
FCIIIIIJ
Data
Memory
A
S,C
D.E
H.L
SP
PC
IX
IY
I
R
'mmmmD Program
mmmm
-
a . ~ d - 2 ) + 2
Memory
1
I 18
I dd-2
JR disp
--.--...-
18 dd-2
mmmm
mmmm+ ,
mmmm+2
mmmm+3
Add the contents of the JR instruction object code second byte. the contents of the Pro-
gram Counter. and 2. Load the sum into the Program Counter The jump is measured
from the address of the instruction operation code. and has a range of -126 to +129
bytes. The Assembler automatically adjusts for the twice-incremented Pc.
The following assembly language statement is used to Jump four steps forward from ad-
dress 400016.
JR $+4
Result of this instruction is shown below:
3-92
JR NC,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF CARRY FLAG IS RESET
JR NC.disp
-----
30 dd-2
OR
JR
4005
c=o
4000
4001
4002
4003
This instruction is identical to the JR disp instruction, except that the Jump is only ex-
ecuted if the Carry status equals 0: otherwise, the next instruction is executed.
In the following instruction sequence
I
ADD I A,7FH
I
I
I
I
After the JR NC,$-3 instruction. the OR instruction is executed if the Carry status equals
1 The ADD instruction is executed if the Carry status equals O.
JR NZ,disp-JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF ZERO FLAG IS RESET
JR NZ.disp
'-.,-.' -v-'
20 dd-2
B OR
z=o
This instruction is identical to the JR disp instruction. except that the jump is only ex-
ecuted if the Zero status equals 0: otherwise. the next instruction is executed.
In the following instruction sequence:
I
_--4..:..;0:;.;;0:..;;0----::;J.;.;R-...,' NZ.$+6
AND t
4005
'---'-4006
After the JR NZ,$+6 instruction. the OR instruction is executed if the Zero status equals
O. The AND instruction is executed if the Zero status equals 1.
3-93
Z=l
JR l,disp - JUMP RELATIVE TO CONTENTS OF PROGRAM
COUNTER IF ZERO FLAG IS SET
JR Z,disp
--..----
28 dd-2
This instruction is identical to the JR disp instruction, except that the Jump is only ex-
ecuted if the Zero status equals 1; otherwise, the next instruction is executed
In the following instruction sequence
I
,...-__4....;;0....;.0..;;.0_--.,;.J....;.R_ ....... 1 Z, $+6
4002 AND: 7FH
4004 tz=o
4005
'---tlr- 4006 OR B
After the JR Z,$+6 instruction, the OR instruction is executed if the Zero status equals
1 The AND instruction is executed if the Zero status equals 0
LD A,I- MOVE CONTENTS OF INTERRUPT VECTOR OR
LD A,R REFRESH REGISTER TO ACCUMULATOR
S Z AC Pia N C

A
B,C
D.E
H.L
SP
PC
IX
IY
I
R
xx
- V mmmm
I
xx
I
Data

Memory
ED mmmm
57 mmmm + 1
mmmm + 2
t----I mmmm + 3
The illustration shows execution of LD A.I:
LD A.I
ED 57
Move the contents of the Interrupt Vector register to the Accumulator. and reflect inter-
rupt enable status in Parity/Overflow flag.
Suppose the Interrupt Vector register contains 7F16. and interrupts are disabled After
execution of
LD A.I
Register A will contain 7F16. and P/O will be 0
LD A.R
-.,-.'
ED 5F
Move the contents of the Refresh register to the Accumulator. The value of the interrupt
flip-flop will appear In the Parity/Overflow flag.
3-94
LD A,(addr) - LOAD ACCUMULATOR FROM MEMORY USING
DIRECT ADDRESSING
S Z ACP/ON C
Data
ppqq
mmmm
mmmm+ 1
PP mmmm +2
't----'--'-----1 mmmm + 3
D:IIIIJ
Memory
yy yy
- .I'
Program
mmmm mmmm+3
...... Memory
I 3A
I I
qq
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
LD A (addr)
--...--- --...---
3A ppqq
Load the contents of the memory byte (addressed directly by the second and third
bytes of the LD A.(addrl instruction object code) into the Accumulator Suppose memo-
ry byte 084A16 contains 2016 After the instruction
label EQU 084AH
LD A(label)
has executed. the Accumulator will contain 2016
Remember that EQU is an assembler directive rather than an instruction: It tells the As-
sembler to use the 16-bit value 084A16 wherever the label appears.
The instruction
LD A.(Iabell
is equivalent to the two instructions
LD HL.label
LD A.(HL}
When you are loading a single value from memory. the LD A(label) instruction is prefer-
red: it uses one instruction and three object program bytes to do what the LD HL.label.
LD A (HL} combination does in two instructions and four object program bytes. Also.
the LD HL.label. LD A (HLI combination uses the Hand L registers. which LD A (label)
does not.
3-95
LD A,(rp) -LOAD ACCUMULATOR FROM MEMORY LOCATION
ADDRESSED BY REGISTER PAIR
Data
ppqq
..... 1
mmmm
mmmm+ 1
mmmm+2
I------t mmmm + 3
Memory
- yy yy
} ...... BC or DE contain ppqq I
C:--:-::;mmm.~ l Program
mmmm
Memory
I OOOx1010
I
S Z ACP/0N C
FCIIIIIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
,
R
LD A(rp)
:Ilw
-o if register pair=BC
1 if register pair=DE
Load the contents of the memory byte (addressed by the BC or DE register pair) Into the
Accumu lator.
Suppose the B register contains 0816, the C register contains 4A16, and memory byte
084A16 contains 3A16 After the instruction
LD A(BC)
has executed. the Accumulator will contain 3A16
Normally. the LD A,(rp) and LD rp,data will be used together. since the LD rp.data in-
struction loads a 16-bit address into the BC or DE registers as follows:
LD BC,084AH
LD A(BCI
3-96
LD dst,src - MOVE CONTENTS OF SOURCE REGISTER TO
DESTINATION REGISTER
S Z AC PIO N C
FDIIIIJ
Data
Memory
Program
Memory
01dddsss mmmm
mmmm+ 1
I-----I
mmmm
+ 2
1-__--1 mmmm + 3
Register A. B. C,
tD.E.H;l
}lR..;"" A, B. C
D. E, H, L
-
~
mmmm mmmm+ 1
........
I
I
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
LD dst. src
III
01 ddd sss
'-v-'
000 for dst or src=B
001 for dst or src=C
010 for dst or src=D
all for dst or src=E
100 for dst or src=H
101 for dst or src=L
111 for dst or src=A
The contents of any designated register are loaded into any other register
For example
LD A,S
loads the contents of Register B into Register A.
LD LD
loads the contents of Register D into Register L
LD C,C
does nothing, since the C register has been specified as both the source and the
destination
3-97
LO HL,(addr) - LOAD REGISTER PAIR OR INDEX REGISTER
LD rp, (addr) FROM MEMORY USING DIRECT ADDRESSING
LD IX,(addr)
LD IY, (addr)
m
m + 1
m+2
m+3
Data
Memory
Xl( ppqq
yV
ppQ1
,
yy xx
.. ,- ~ Program
mmmm ".:,mmm +3
Memory
I
2A mmm
I
1
QQ mmm
~
pp
mmm
mmm
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
S Z AC P/O N C
FCIIIIIJ
The illustration shows execution of LD HL(ppqq):
LD HL.addr
--..---..,.-.-
2A ppqq
Load the HL register pair from directly addressed memory location.
Suppose memory location 400416 contains AD16 and memory location 400516 con-
tains 1216 After the instruction
LD HL(4004H)
has executed, the HL register pair will contain 12AD16.
1fL
ED 01 dd 1011 ppqq
--,-
00 for rp is register pair Be
Load register pair from directly addressed memory.
Suppose memory location 49FF16 contains BE16 and memory location 4A0016 con-
tains 3316. After the instruction
LD DE, (49FFH)
has executed, the DE register pair will contain 33BE16.
LD lX,(addr)
--..,.-.- --..--
DD 2A ppqq
Load IX register from directly addressed memory.
3-98
Suppose memory location 011116 contains FF16 and memory location 011216 con-
tains 5616. After the instruction
LO IX,(D111H)
has executed, the IX register will contain 56FF16
LO IY,(addrl
---..-- ---..--
FO 2A ppqq
Load IY register from directly addressed memory.
Affects IY register instead of IX. Otherwise identical to LO IX(addr),
LD I,A - LOAD INTERRUPT VECTOR OR REFRESH
LD R,A REGISTER FROM ACCUMULATOR
5 Z AC P/O N C
F o::::r::r:IIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
IV
R
xx
JJ'
mmmm mmmm + 2
--
I
I
Data
Program
Memory
ED mmmm
4F mmmm+ 1
J-----1mmmm + 2
mmmm+3
......---1
The illustration shows execution of LD R.A
LO R,A
'"-v-'
ED 4F
Load Refresh register from Accumulator.
Suppose the Accumulator contains 7F16 After the instruction
LO R,A
has executed. the Refresh register will contain 7F16
LO I.A
'-'v-'
ED 47
Load Interrupt Vector register from Accumulator,
3-99
LD reg.data - LOAD IMMEDIATE INTO REGISTER
S Z AC P/O N C
Fo::::I::IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
}-0........,;.
Register A, B, C,
D, E, H or L
- ~ ~
mmmm mmmm + 2
- .......
I
I
Data
Program
Memory
OOxxx 11 0 mmmm
YY mmmm+ 1
mmmm+2
I----I
mmmm
+ 3
00 xxx 110 yy
-.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load the contents of the second object code byte into one of the registers.
When the instruction
LD A,2AH
has executed, 2A16 is loaded into the Accumulator.
3-100
LD rp,data - LOAD 16 BITS OF DATA IMMEDIATE INTO
LD IX,data REGISTER
LD IV,data
S Z Ac P/O N C
FD:IIIIJ
mmmm
mmmm+ 1
mmmm+2
mmmm+3
Program
Memory
OOxxOOOl
\
qq
pp
Data
~
e m o r Y
HL or
nto
tion
y.;""",.eC'D<
SP. Load ppqq i
::cted destina
mmmm mmmm+3
........
I
I
A
B.C
D,E
H,L
SP
PC
IX
IV
I
R
The illustration shows execution of LD rp,data:
_Jt1
00 xx 0001 ppqq
--
Load the contents of the second and third object code bytes into the selected register
pair. After the instruction
LD SP,217AH
has executed, the Stack Pointer will contain 217A16
LD IX, data
---...- --
DD 21 ppqq
Load the contents of the second and third object code bytes into the Index register IX.
LD IY, data
---- -.-
FD 21 ppqq
Load the contents of the second and third object code bytes into the Index Register IY.
Notice that the LD rp,data instruction is equivalent to two LD reg,data instructions
For example:
LD HL,032AH
is equivalent to
LD H,03H
LD L,2AH
3-101
LD reg, (HL) - LOAD REGISTER FROM MEMORY
LD reg, (IX+disp)
LD reg, (lY+disp)
S Z AC P/O N C
F o::r::::r:r::o
Data
Memory
m
m+ 1
m+2
m+3
+d
}--Bog;"" A, B, C,'"
yy
-,
D, E. H or L
Program
mmmm mmmm+3
ppqq
-
....... Memory
I DO mmm
I Olxxx110 mmm

d mmm
mmm
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of LD reg.(IX+disp)
LD reg. (IX + disp)

DD 01 xxx 110 d
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load specified register from memory location (specified by the sum of the contents of
the IX register and the displacement digit d)
Suppose ppqq=400416 and memory location 401016 contains FF16 After the instruc-
tion
LD B(IX+OCH)
has executed. Register B will contain FF16.
LD reg. (Iv + disp)

FD 01 xxx 110 d
l"------I..... same as for LD reg.(IX+disp)
This instruction is identical to LD reg,(lX+displ. except that it uses the IV register in-
stead of the IX register.
3-102
LD reg,(HU
m
01xxxll0
-...-
l... ........ ~ s a m e as for LD reg.OX+disp)
Load specified register from memory location (specified by the contents of the HL
register pair).
LD SP,HL - MOVE CONTENTS OF HL OR INDEX REGISTER
LD SP,IX TO STACK POINTER
LD SP,IV
S Z Ac P/O N C
FCIIIID
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
pp qq
::>,
mmmm ~ mmmm+ 1
I
I
Data
Program
Memory
F9 mmmm
mmmm+ 1
t-----f
mmmm
+ 2
t-__--fmmmm + 3
The illustration shows execution of LD SP.HL:
LD SP.HL
~
F9
Load contents of HL into Stack Pointer
Suppose pp=0816 and qq=3F16 After the instruction
LD SP.HL
has executed. the Stack Pointer will contain 083F16
LD SP.IX
~
DO F9
Load contents of Index Register IX into Stack Pointer
LD SP.lY
~
FD F9
Load contents of Index Register IY into Stack Pointer.
3-103
LD (addr),A - STORE ACCUMULATOR IN MEMORY USING
DIRECT ADDRESSING
S Z ACP/ON C
Data
ppqq
mmmm
mmmm+ 1
pp mmmm+2
't----'-'----1 mmmm + 3
cr:IIIIJ
Memory
yy yy
-

mmmm
Program
Memory
I 32
I
I
qq
F
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
tY
32 ppqq
Store the Accumulator contents in the memory byte addressed directly by the second
and th ird bytes of the LD (addrLA instruction object code,
Suppose the Accumulator contains 3A16 After the instruction
label EQU 084AH
LD (label).A
has executed. memory byte 084A16 will contain 3A16.
Remember that EQU is an assembler directive rather than an it tells the As-
sembler to use the 16-bit value 084AH whenever the word "label" appears,
The instruction
LD (addrl.A
is equivalent to the two instructions
LD H.label
LD (HL).A
When you are storing a single data value in memory. the LD Oabell.A instruction is
preferred because it uses one instruction and three object program bytes to do what the
LD H(label). LD (HL).A combination does in two instructions and four object program
bytes. Also. the LD H(labell. LD (HL).A combination uses the Hand L registers. while the
LD (labell.A instruction does not.
3-104
lD (addr),Hl- STORE REGISTER PAIR OR INDEX
lD (addr) ,rp REGISTER IN MEMORY USING DIRECT
lD (addr),xy ADDRESSING
S Z ACP/ON C
Data
ppqq
ppqq + 1
mmmm
mmmm+ 1
mmmm +2
mmmm+3
CIIIIlJ
Memory
yy
;
xx
~
"
I
xx yy
--
Program
mmmm mmmm+4
....... Memory
I ED
I 01010011
qq
pp
F
A
B.C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of LD (ppqql.DE:
~
ED 01 xx 0011 ppqq
........
Store the contents of the specified register pair in memory. The third and fourth object
code bytes give the address of the memory location where the low-order byte is to be
written. The high-order byte is written into the next sequential memory location.
Suppose the BC register pair contains 3C2A16. After the instruction
label EQU 084AH
LD (labell.BC
has executed. memory byte 084A16 will contain 2A16 Memory byte 084B16 will con-
tain3C16
Remember that EOU is an assembler directive rather than an instruction; it tells the As-
sembler to use the 16-bit value 084A16 whenever the word "label" appears.
LD (addrl.HL
~
22 ppqq
This is a three-byte version of LD (addrl.rp which directly specifies HL as the source
register pair.
3105
1X
DO 22 ppqq
Store the contents of Index register IX in memory. The third and fourth object code
bytes give the address of the memory location when'! the low-order byte is to be writ-
ten The high-order byte is written into the next sequential memory location.
~
FD 22 ppqq
This instruction is identical to the LD (addrl.lX instruction, except that it uses the IY
register instead of the IX register.
3-106
LD (HL).data -LOAD IMMEDIATE INTO MEMORY
LD (Ix+disp) ,data
LD (lY+disp) ,data
S Z AC P/O N C
Data
m
m+ 1
m+2
m+3
+d
CIIIIIJ
Memory
~
xx ppqq
I
mmmm
~ m m m + ~
Program
ppqq
Memory
I DO mmm
I
~ p q q + d ~ . _
36 mmm
d
mmm
'-- xx mmm
F
A
B.C
D,E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of LD (IX+&xx:
LD (IX+disp),data
-.".-... -..- --.-
DD 36 d xx
Load Immediate into the Memory location designated by base relative addressing.
Suppose ppqq=540016 After the instruction
LD (IX+9),FAH
has executed. memory location 540916 will contain FA16
LD (IY+disp),data
----- -.-----..-'
FD 36 d xx
This instruction is identical to LD (IX+disp),data, but uses the IY register instead of the
IX register.
LD (HL),data
-.".-... ----..-'
36 xx
Load Immediate into the Memory location (specified by the contents of the HL register
pair)
The Load Immediate into Memory instructions are used much less than the Load Im-
mediate into Register instructions
3-107
LD (HL),reg - LOAD MEMORY FROM REGISTER
LD (lX+disp),reg
LD (ly+disp),reg
Data
mmm
mm+l
mmmm+2
1------1 mmmm + 3
Contents of A, B. yy
1
c. D. E. H or L
~ i s y y
pp qq
mmmm
~ m m m + ~
Program
Memory
I
01110xxx m
I mm
S ZACP/ON C
Fo::::r::rIIl
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
The illus1ration shows execution of LD (HU,reg:
'II
01110xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Load memory location (specified by the contents of the HL register pair) from specified
register.
Suppose ppqq=450016 and Register C contains F916 After the instruction
LD (HU,C
has executed, memory location 450016 will contain F916.
l ~
DDOll10xxxa
T ~ same as for LD (HU,reg
Load memory location (specified by the sum of the contents of the IX register and the
3-108
displacement value d) from specified register.
LD (lY+dispLreg
:LY
FD01110xxxa
T...-----tl... same as for LD (HU.reg
This instruction is identical to LD (IX+dispLreg. except that it uses the IY register in-
LD (rp),A - LOAD ACCUMULATOR INTO THE MEMORY
LOCATION ADDRESSED BY REGISTER PAIR
S Z AC plO N C Data
ppqq
1
mmmm
mmmm+ 1
mmmm+2
t------t mmmm + 3
co:::IIIJ
Memory
yy
.
yy
}
Be or DE I
contain ppr
q
-,
Program
mmmm
-
--" mmmm + 1
--
Memory
,
I
OOOxOO10
I
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
LD (rpl.A
m
'-'
oif register pair=BC
1 if register pair=DE
Store the Accumulator in the memory byte addressed by the BC or DE register pair.
Suppose the BC register pair contains 084A16 and the Accumulator contains 3A16
LD (BCLA
has executed. memory byte 084A16 will contain 3A16
The LD (rp).A and LD rp.data will normally be used together. since the LD rp.data in-
struction loads a 16-bit address into the BC or DE registers as follows:
LD BC.084AH
LD (BCl.A
3-109
LDD - TRANSFER DATA BETWEEN MEMORY LOCATIONS.
DECREMENT DESTINATION AND SOURCE ADDRESSES
Program
Memory
ppqq-1
ppqq
Data
t::E::j

ED mmmm
..... .. mmmm + 1
mmmm+2
1-------41 mmmm + 3
rrss- 1

Set if BC-1 ;I! 0, reset otherwise
t
5 Z AC P/G N C
FaTID:!]
A ..... M":
B.CI- __
D.E rr ss -----
.Lt-__..:P;.:.p ...... q.:..q:..-__ ..... ------
Sp .... .......
PC mmmm
IX ----.....;,;.;;.;,;.....;.....;-----.
Iy ...... -I
I
A
LDD
---
ED A8
Transfer a byte of data from memory location addressed by the HL register pair to
memory location addressed by the DE register pair. Decrement contents of register
pairs BC. DE. and HL.
Suppose register pair BC contains 004F16. DE contains 454516. HL contains 201216.
and memory location 201216 contains 1816. After the instruction
LDD
has executed. memory location 454516 will contain 1816. register pair BC will contain
004E16. DE will contain 454416. and HL will contain 201116.
3-110
LDDR - TRANSFER DATA BETWEEN MEMORY
LOCATIONS UNTIL BYTE COUNTER IS
ZERO. DECREMENT DESTINATION AND
SOURCE ADDRESSES
LDDR
---
ED B8
Th is instruction is identical to LDD. except that it is repeated until the BC register pair
contains zero After each data transfer. interrupts will be recognized and two refresh cy-
cles will be executed.
Suppose we have the following contents in memory and register pairs:
Register/Contents Location/Contents
HL 201216 201216 1816
DE 454516 201116 AA16
BC 000316 2010162516
After execution of
LDDR
register pairs and memory locations will have the following contents:
Register/Contents Location/Contents Location/Contents
HL 200916 201216 1B16 454516 1816
DE 454216 201116 AA16 454416 AA16
BC 000016 201016 2516 454316 2516
This instruction is extremely useful for transferring blocks of data from one area of
memory to another.
3-111
LDI - TRANSFER DATA BETWEEN MEMORY
LOCATIONS. INCREMENT DESTINATION AND
SOURCE ADDRESSES
Program
Memory
A
B,C tt uu
D,E rr ss
,L pp QQ
SP
PC mmmm
IX
IY
I
R
ED mmmm
AO mmmm+ 1
.....__-1 mmmm + 2
.....__-1 mmmm+ 3
Set if BC-1 ~ 0, reset otherwise
S Z ACP'O N C
Fc:::c:I:I]IIJ
LDI
~
ED AO
Transfer a byte of data from memory location addressed by the HL register pair to
memory location addressed by the DE register pair, Increment contents of register pairs
HL and DE Decrement contents of the BC register pair
Suppose register pair BC contains 004F16, DE contains 454516, HL contains 201216_
and memory location 201216 contains 1816, After the instruction
LDI
has executed, memory location 454516 will contain 1816, register pair BC will contain
004E16, DE will contain 454616_ and HL will contain 201316
3-112
LDIR-TRANSFER DATA BETWEEN MEMORY
LOCATIONS UNTIL BYTE COUNTER IS
ZERO. INCREMENT DESTINATION AND
SOURCE ADDRESSES
LOIR
-..-
ED BO
This instruction is identical to LDI. except that it is repeated until the BC register pair
contains zero. After each data transfer. interrupts will be recognized and two refresh cy-
cles will be executed
Suppose we have the following contents in memory and register pairs:
Register/Contents Location/Contents
HL 201216 201216 1816
OE 454516 201316 CD16
BC 000316 201416 F016
After execution of
LDIR
register pairs and memory will have the following contents:
Register/Contents Location/Contents Location/Contents
HL 201516 2012161816 4545161816
OE 454816 201316 C016 454616 C016
BC 000016 201416 F016 454716 F016
This instruction is extremely useful for transferring blocks of data from one area of
memory to another.
NEG - NEGATE CONTENTS OF ACCUMULATOR
Data
Program
Memory
,ED mmmm
,44 mmmm+ 1
1-----1 mmmm + 2
I-----t mmmm + 3
~ " ~ xx __ xx +'
"
mmmm mmmm + 2
........
I
I
S ZACP/ON C
F ~
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
Negate contents of Accumulator. This is the same as subtracting contents of the Ac-
cumulator from zero. The result is the two's complement. BOH will be left unchanged
Suppose xx=5A16. After the instruction
NEG
5A 01 01 1 01 0
Two's complement = 1 0 1 0 0 1 1 0
3-113
NOP - NO OPERATION
S Z AC PIO N C
FCIID:D
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
_ - - ( ~ " m m m +~ mmmm
I
I
NOP
---
00
Data
~
Program
Memory
00 mmmm
1--__--1mmmm + 1
1--__--1mmmm + 2
t-__--fmmmm + 3
This is a one-byte instruction which performs no operation, except that the Program
Counter is incremented and memory refresh continues. This instruction is present for
several reasons:
1) A program error that fetches an object code from non-existent memory will fetch
00. It is a good idea to ensure that the most common program error will do nothing.
2) The NOP instruction allows you to give a label to an object program byte:
HERE NOP
3) To fine-tune delay times. Each NOP instruction adds four clock cycles to a delay.
NOP is not a very useful or frequently used instruction.
3-114
OR data - OR IMMEDIATE WITH ACCUMULATOR
S ZAcP/ON C
F ~
Data
Memory
A
S,C
D.E
H,L
SP
PC
IX
IV
I
R
--' ~ xx ,.:x OR yy
'"
mmmm mmmm+2
Program
.........
Memory
I F6
I yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
OR
F6
data
yy
OR the Accumulator with the contents of the second instruction object code byte.
OR 7CH
has executed. the Accumulator will contain 7E16
3A 001 1 1 01 0
7C = 0 1 1 1 1 1 0 0
0111 1110
osets S to O ~ LSiX 1 bits. set PIO to 1
LNon-zero resu It set Z to 0
This is a routine logical instruction; it is often used to turn bits "on". For example. the
instruction
OR 80H
will unconditionally set the high-order Accumulator bit to 1.
3-115
OR reg - OR REGISTER WITH ACCUMULATOR
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
S 2 AC Pia N C
- ~
~
r.
xx OR yy
--.
} Co"JOfA
xx
....c. D, E. H or L
is yy
-
,
mmmm mmmm + 1
--
I
I
B.
Data
Memory
Program
Memory
10110xxx mmmm
1-------1mmmm + 1
mmmm+2
I------t
mmmm
+ 3
OR reg
--- -..-
10110 xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Logically OR the contents of the Accumulator with the contents of Register A B, C. D.
E, H or L. Store the result in the Accumulator.
Suppose xx=E316 and Register E contains A8l6. After the instruction
OR E
has executed. the Accumulator will contain EB16
001 1
1000
1 0 1 1
L Six 1 bits. set PIO to 1
LNon-zero resu It. set Z to 0
E3 1 1 1 0
A8 = 101 0
------
1 1 1 0
sets S to 1...J
3-116
OR (HL) - OR MEMORY WITH ACCUMULATOR
OR (IX+disp)
OR (IY+disp)
S Z AC PIO N C
Data
qq
mmm
mmm+1
mmmm+2
1-------.. mmmm + 3
~
Memory
-, ~
xx .......xx OR yy
yy
P
f
pp qQ
mmmm
~ m m m + ~
Program
Memory
I B6 m
I m
F
A
B,C
D.E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of OR (HU:
OR (HU
~
86
OR contents of memory location (specified by the contents of the HL register pair) with
the AccumulatoL
Suppose xx=E316. ppqq=400016. and memory location 400016 contains A816' After
the instruction
OR (HU
has executed. the Accumulator will contain EB 16
E3 1 1 1 0 00 1 1
AS = 1010 1000
1110 1011
1 sets S to 1...J LSix 1 bits. set PIO to 1
OR (IX+disp)
-.--- -..-
DD B6 d
OR contents of memory location (specified by the sum of the contents of the IX register
and the displacement value d) with the AccumulatoL
OR (IY+disp)
--- -.-
FD 86 d
This instruction is identical to OR (IX+displ. except that it uses the IY register instead of
the IX register.
3-117
OUT (C) ,reg - OUTPUT FROM REGISTER
1)[
ED 01 xxx 001
-.-
F
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
5 Z AC PIO N C
+
CIIIIIJ
- I/O port vv I
I
}--"",J" B c.
I
vv
D, E, H or L
"
mmmm mmmm+ 2
........
I
I
Data
Memory
Program
Memory
ED mmmm
01xxxOO1 mmmm + 1
mmmm+2
t-----1 mmmm + 3
000 for reg=B
001 for reg=C
010 for reg=D
all forreg=E
100 for reg=H
101 for reg=L
111 for reg=A
Suppose yy= 1F16 and the contents of Hare AA16 After the execution of
OUT (C),H
AA16 will be in the buffer of I/O port 1F16'
3-118
OUTD - OUTPUT FROM MEMORY. DECREMENT ADDRESS
qq
mmm
mmm+ 1
mmmm+2
t-----t mmmm + 3
s Z AC P/O N C
xx-1
~
+
Data
~
~ I/O port yy I
Memory
I
pp
xx Vy ~
~ ~
I ~ p p q q - 1
I
qq
~
pp
--
Program
mmmm r--.. ... .J'
~ ~ m m m + 2
Memory
I ED m
I AS m
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
OUTD
~
ED AB
Output from memory location specified by HL to I/O port addressed by Register C.
Registers Band HL are decremented.
Suppose xx=OA16. yy=FF16. ppqq=500016. and memory location 500016 contains
OUTD
has executed. 7716 will be held in the buffer of I/O port FF16. The B register will con-
tain 0916. and the HL register pair 4FFF16
OTDR - OUTPUT FROM MEMORY. DECREMENT ADDRESS,
CONTINUE UNTIL REGISTER 8=0
OTDR
---...--
ED 88
OTDR is identical to aUTO. but is repeated until Register B contains O.
Suppose Reg ister B contains 0316. Register C contains FF 16. and HL contains 500016
Memory locations 4FFE16 through 500016 contain:
Location/Contents
4FFE16 CA16
4FFF16 1816
5000
16 F116
After execution of
OTDR
register pair HL will contain 4FFD16. Register 8 will contain zero. and the sequence
F116. 1816. CA16 will have been written to 1/0 port FF16.
This instruction is very useful for transferring blocks of data from memory to output
devices.
3-119
OUTI- OUTPUT FROM MEMORY. INCREMENT ADDRESS
qq
mmm
mmm+1
mmmm+2
I-----t!mmmm + 3
s Z Ac Pia N
C
xx-1
J
+
C
Data
GEGEIIJ
II
~
I/O port yy J
Memory
+
pp
xx
yy
....rppqq+ 1
pp qq
~
Program
mmmm
--
~ m m m + 2
Memory
I ED m
I A3 m
F
A
S.C
D.E
H.l
SP
PC
IX
IY
I
R
OUTI
-.-
ED A3
Output from memory location specified by HL to I/O port addressed by Register C
Register B is decremented and the HL register pair is incremented.
Suppose xx=OA16, yy=FF16' ppqq =500016, and memory location 500016 contains
OUTI
has executed, 7716 wi II be held in the buffer of I/O port FF16 The B register will con-
tain 0916 and the HL register pair will contain 500116.
OTIR-OUTPUT FROM MEMORY. INCREMENT ADDRESS,
CONTINUE UNTIL REGISTER 8=0
OTIR
---
ED B3
OTIR is identical to OUTI, except that it is repeated until Register B contains 0
Suppose Register B contains 0416, Register C contains FF16, and HL contains 500016
Memory locations 500016 through 500316 contain:
Location/Contents
5000
16 CA16
5001
16 1B16
5002
16
81
16
5003
16 AD16
After execution of
OTIR
register pair HL will contain 500416, Register B will contain zero and the sequence
CA16, 1B16' B116 and AD16 will have been written to I/O port FF16
This instruction is very useful for transferring blocks of data from memory to an output
device.
3-120
OUT (port).A - OUTPUT FROM ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IV
I
R
s Z AC PIO N C
+
Data
CIIIID
I
I/O port yy ~
Memory
+
,;t'
Program
mmmm mmmm+2
.......
Memory
I 03
I
'- yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
U
03 yy
Output the contents of the Accumulator to the I/O port identified by the second OUT in-
struction object code byte
Su ppose 3616 is held in the Accumu lator. After the instruction
OUT (lAHl.A
has executed. 3616 will be in the buffer of I/O port 1A16
The OUT instruction does not affect any statuses Use of the OUT instruction is very
hardware-dependent. Valid I/O port addresses are determined by the way in which I/O
logic has been implemented. It is also possible to design a microcomputer system that
accesses external logic using memory reference instructions with specific memory ad-
dresses OUT instructions are frequently used in special ways to control microcomputer
logic external to the CPU
3-121
POP rp - READ FROM THE TOP OF THE STACK
POP IX
POPIY
S Z AC Pia N C
Data
SSSS
SSSS + 1
SSSS + 2
mmmm
mmmm+ 1
......__~ m m m m + 2
......__--1mmmm + 3
D:IIIIJ
Memory
qq
~
I
pp
:,.(-SSSS+2
/7
ssss
~ - "
mmmm
-
-immmm + 1
Program
--
Memory
I 11000001
I
F
A
S.C
D_E
H.L
SP
PC
IX
IY
I'
R
The Illustration shows execution of POP BC:
POP rp
lZ-
11 xx 0001
00 for rp is reg ister pair BC
11 for rp is register pair A and F
POP the two top stack bytes into the designated register pair_
Suppose qq=0116 and pp=2A16- Execution of
POP HL
loads 01 16 into the L register and 2A16 into the H register. Execution of the instruction
POP AF
loads 01 into the status flags and 2A16 into the Accumulator Thus, the Carry status
will be set to 1 and other statuses will be cleared.
POP IX
~
DD E1
POP the two top stack bytes into the IX register
POP IY
-.,-
FD El
POP the two top stack bytes into the IY register.
The POP instruction is most frequently used to restore register and status contents
which have been saved on the stack: for example, while servicing an interrupt.
3-122
PUSH rp - WRITE TO THE TOP OF THE STACK
PUSH IX
PUSHIY
Data
ssss-2
ssss-1
ssss
mmmm
mmmm+ 1
mmmm+2
t-----1mmmm + 3
Memory
I
qq
----I pp
LsSSS-2 )
//
SSSS
,
~ m m m + v
mmmm
Program
Memory
ppqq
I FD
I E5
S Z AC Pia N C
FCIIIIIJ
A
B.C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of PUSH IY
PUSH IY
~
FD E5
PUSH the contents of the IY register onto the top of the stack.
Suppose the IY register contains 45FF16' Execution of the instruction
PUSH IY
loads 4516, then FF16 onto the top of the stack.
PUSH IX
~
DO E5
PUSH the contents of the IX register onto the top of the stack
LK
11 xx 0101
-..-
11 for rp is register pair A and F
PUSH contents of designated register pair onto the top of the stack
Execution of the instruction
PUSH AF
loads the Accumulator and then the status flags onto the top of the stack.
The PUSH instruction IS most frequently used to save register and status contents; for
example, before servicing an interrupt
3-123
RES b,reg - RESET INDICATED REGISTER BIT
S Z AC Pia N C
FCI:IJIIJ
Data
Memory
A
B,C
D,E
H,L
SP
PC
IX
IV
I
R
c
)
yyyyyyyy 0
.&
T
,
mmmm mmmm+2
.......
I
I
Program
Memory
CB mmmm
10bbbllllll mmmm + ,
mmmm+2
t-----t mmmm + 3
~ l \
CB 10 bbb xxx
-...- -...-
Bit bbb xxx
- -
a 000 000
1 001 001
2 010 010
3 all all
4 100 100
5 101 101
6 110 111
7 111
Reset I ndicated bit within specified register.
Register
B
C
D
E
H
L
A
RES 6,H
has executed, bit 6 in Register H will be reset (Bit a is the least significant bit)
3-124
RES b,{HL) - RESET BIT b OF INDICATED MEMORY POSITION
RES b,{IX+disp)
RES b, (lY+disp)
5 Z AC P/O N C Data
Fo:r:r::r:o Memory
c
0
~
yyyyyyyy ppqq+
a
T
';mmm+4
mmmm
Program
ppqq
........ Memory
1
I DD mmm
I
0
pqq
+
d
:)::
CB mmm
d mmm
10bbb110 mmm
mmm
A d
B.C
D,E
H.L
$P
PC
IX
IV
I m
R m+1
m+2
m+3
m+4
The illustration shows execution of SET b,(IX+disp). Bit a is execution of SET
b,(IX+disp). Bit a is the least significant bit.
~
DD CB d 10 bbb 110
bbb Bit Reset
000 a
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Reset ind icated bit within memory location indicated by the sum of Index Register IX
and d.
Suppose IX contains 411016 After the instruction
RES 0,(IX+7)
has executed, bit 0 in memory location 411716 will be O.
~
FD CB d 10 bbb 110
--.-
bbb is the same as in RES b.(IX+disp)
This instruction is identical to RES b, (IX+disp), except that it uses the IY register instead
3-125
of the IX register
RES b,(HL)
III
CB10bbb110
bbb is the same as in RES b,(IX+disp)
Reset indicated bit within memory location indicated by HL.
Suppose HL contains 444416 After execution of
RES 7,(HL)
bit 7 in memory location 444416 will be 0
RET - RETURN FROM SUBROUTINE
S Z Ac P/O N C Data
xxxx
xxxx + 1
xxxx + 2
mmmm
mmmm+ 1
mmmm+2
t-----4 mmmm + 3
CCIIII:l
Memory
,
qq
I
pp
.. ,
xxxx
-
Il xxxx';' 2
mmmm
.,
--
Program
Memory
L(
ppqq r- I C9
I
F
A
S,C
D,E
H,L
SP
PC
IX
IY
I
R
RET
C9
Move the contents of the top two stack bytes to the Program Counter: these two bytes
provide the address of the next instruction to be executed. Previous Program Counter
contents are lost. Increment the Stack Pointer by 2. to add ress the new top of stack.
Every subroutine must contain at least one Return (or conditional Return) instruction:
this is the last instruction executed within the subroutine, and causes execution to
return to the calling program.
3-126
RET cond - RETURN FROM SUBROUTINE IF CONDITION
IS SATISFIED
K
11 xxx 000
000
001
010
all
100
101
110
111
Condition
NZ Non-Zero
Z Zero
NC Non-Carry
C Carry
PO Parity Odd
PE Parity Even
P Sign Positive
M Sign Negative
Relevant Flag
Z
Z
C
C
Pia
Pia
S
S
CALL
AND
SUbl+--.....
This instruction is identical to the RET instruction, except that the return is not ex-
ecuted unless the condition is satisfied: otherwise, the instruction sequentially follow-
ing the RET cond Instruction will be executed
SUBR
7 C H ~
1
I
I
I ;First subroutine instruction
I
I condition satisfied
I
R T cond I
---------"
condition not
satisfied
a SOH
After the RET cond is executed. if the condition is satisfied then execution returns to the
AND instruction which follows the CALL. If the condition is not satisfied. the OR in-
struction. being the next sequentia I instruction. is executed,
3-127
RET cond - RETURN FROM SUBROUTINE IF CONDITION
IS SATISFIED
K
11 xxx 000
000
001
010
all
100
101
110
111
Condition
NZ Non-Zero
Z Zero
NC Non-Carry
C Carry
PO Parity Odd
PE Parity Even
P Sign Positive
M Sign Negative
Relevant Flag
Z
Z
C
C
Pia
Pia
S
S
CALL
AND
SUbl+--.....
This instruction is identical to the RET instruction, except that the return is not ex-
ecuted unless the condition is satisfied: otherwise, the instruction sequentially follow-
ing the RET cond Instruction will be executed
SUBR
7 C H ~
1
I
I
I ;First subroutine instruction
I
I condition satisfied
I
R T cond I
---------"
condition not
satisfied
a SOH
After the RET cond is executed. if the condition is satisfied then execution returns to the
AND instruction which follows the CALL. If the condition is not satisfied. the OR in-
struction. being the next sequentia I instruction. is executed,
3-127
RETI- RETURN FROM INTERRUPT
xxxx
xxxx +'
xxxx + 2
mmmm
mmmm+ 1
mmmm+2
mmmm+3
Data
Memory
qq
pp
- ~
xxxx I xxxx+2
mmmm
~
.-. Program
Memory
p p q q ~
ED
I 4D
S Z AC Pia N C
Fo:::I:IIIJ
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
RETI
---
ED 4D
Move the contents of the top two stack bytes to the Program Cou nter: these two bytes
contents are lost Increment the Stack Pointer by 2, and address the new top of stack.
This instruction is used at the end of an interrupt service routine, and, in addition to
returning control to the interrupted program, it is used to signal an I/O device that the
interrupt routine has been completed. The I/O device must provide the logic necessary
to sense the instruction operation code: refer to An Introduction to Microcom-
puters: Volume 2 for a description of how the RETI instruction operates with the Z80
family of devices
3-128
RETN - RETURN FROM NON-MASKABLE INTERRUPT
Data
mmmm
mmmm+ 1
mmmm +2
mmmm
mmmm+ 1
1-----1 mmmm + 2
mmmm+3
t-----t
Memory
, qq
II
pp
-, )
xxxx _ t. xxxx + 2
mmmm
Ii-<ppqq =>-
Program
Memory
I ED
I
45
S ZACP/ON C
FOIIIlJ
A
B,C
D,E
H,L
SP
PC
IX
IV
I!
R
RETN
--.--
ED 45
Move the contents of the top two stack bytes to the Program Counter; these two bytes
contents are lost Increment the Stack Pointer by 2 to address the new top of stack.
Restore the interrupt enable logic to the state it had prior to the occurrence of the non-
maskable interrupt.
This instruction is used at the end of a service routine for a non-maskable interrupt, and
causes execution to return to the program that was interrupted.
3-129
RL reg - ROTATE CONTENTS OF REGISTER LEFT
THROUGH CARRY
Data
Memory
Program
Memory
CB mmmm
00010001 mmmm + 1
mmmm+2
t-----t mmmm + 3
s Z AC Pia N 1
F I x I x I 0\ x \ 0,\
t ~ A
u , ~
D,E
H,L
SP
- ~ V PC mmmm
~ m m m + 2
IX
IY
I
R
I
The illustration shows execution of RL C:
l\
CB 00010 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register left one bit through Carry,
Suppose 0 contains A916 and Carry=O After the instruction
RL 0
has executed, 0 will contain 5216 and Carry will be 1:
Before After
Register 0 Carry Register 0 Carry
11010 100 11
a sets S to a
3 ones. set P/0 to a
OJ
Non-zero resu It. set Z to 0
3-130
RL (HL) - ROTATE CONTENTS OF MEMORY LOCATION
RL (IX+disp) LEFT THROUGH CARRY
RL (IY+disp)
Data
Memory
......................... ..... + d
Program
Memory
DO mmmm
CB mmmm+ 1
d mmmm+2
___ mmmm + 3
mmmm+4
1---"""'1
A
_-----t--------i
B.C
D.E t--------t-------I
H.L
SP t---------"-------I
PC IX ppqq - __--
IY ... .....------.,
I
R
The illustration shows execution of RL (IX+disp)
RL (IX+disp)
--.,,- -.-
Rotate contents of memory location (specified by the sum of the contents of Index
Register IX and displacement integer d) left one bit through Carry.
Suppose the IX reg ister contains 400016. memory location 400716 contains 2f 16. and
Carry is set to 1. After execution of the instruction
RL
memory location 400716 will conta in 5F16. and Carry is 0
Before After
Memory Carry Memory Carry
1001 0 1 1 1 1] OJ [Q)
osets S to 0.J L...Non-zero result. set Z to 0
6 ones. set P10 to 1
RL (IY+disp)
R
This instruction is identical to RL (IX+dispL but uses the IY register instead of the IX
register.
3-131
RL (HL)
~
CB 16
Rotate contents of memory location (specified by the contents of the HL register pair)
left one bit through Carry
RLA - ROTATE ACCUMULATOR LEFT THROUGH CARRY
Data
Memory
Program
Memory
17 mmmm
~ __--1mmmm + 1
I-__~ m m m m + 2
I-__~ m m m m + 3
s Z AC PIO N 1
FI I 101 loP
s.c
D.E
H.L
SP
~ m m m + ~
PC mmmm
IX
IV
I
I
R
I
RLA
17
Rotate Accumu lalor contents left one bit through Carry status
Suppose the Accumulator contains 2A16 and the Carry status is set to 1 After the in-
struction
RLA
has executed. the Accumulator will contain F516 and the Carry status will be reset to 0:
Before After
Accu mu lator Carry Accumulator Carry
1011110101 OJ 111110101\ @]
3 -132
RLC reg - ROTATE CONTENTS OF REGISTER LEFT CIRCULAR
S Z AC-P/0 N C )
FIXIXIOIXlol....-
Data
Memory
Ar- """4 ......
B,C
. ~
H.L .-------"'-----------t
SP
~ ~ t------m==m:":m::':m=------i-_---4-..,.:rrmmmm +'9
IV
I: ...------r-.-------t
R I
Program
Memory
CB mmmm
00000011 mmmm + 1
mmmm +2
....------tl
mmmm
+ 3
The illustration shows execution of RLC E:
1-1
CB 00000 xxx
OJ
Carry
Non-zero result. set Z to 0
After
Register 0
osets S to 0
4 ones, set P/0 to 1
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register left one bit. copying bit 7 into Carry.
Suppose Register 0 contains A916 and Carry is 1, After execution of
RLC 0
Register 0 will contain 5316 and Carry will be 1.
Before
Reg ister 0 Carry
11 01010011 OJ
3-133
RLC (HL)-
RLC (Ix+disp)
RLC (lY+disp)
ROTATE CONTENTS OF MEMORY LOCATION
LEFT CIRCULAR
c
Data
Memory
L_.h::Q;iiIi++U-_Jppqq
m
m+ 1
mmmm+2
t--------I mmmm + 3
pp qq
mmmm

Program
Memory
I CS mmm
I 06 mmm
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of RLC (HL):
RLC
CB 06
left one bit. copying bit 7 into Carry.
Suppose register pair HL contains 54FF16 Memory location 54FF16 contains A516.
and Carry is O. After execution of
RLC (HL)
memory location 54FF16 will contain 4B16. and Carry will be 1:
Before After
Non-zero resu It. set Z to 0
@]
osets S to O__J
4 ones. set P/0 to 1
RLC (IX+disp)

11 010010
1
1
Rotate memory location (specified by the su m of the contents of Index register IX and
displacement integer d) left one bit. copying bit 7 into Carry.
Suppose the IX register contains 400016. Carry is 1. and memory location 400716 con-
tains 2F16. After the instruction
RLC (IX+7)
3-134
has executed. memory location 400716 will contain 5E16. and Carry will be 0:
Before After
--- --
OJ
10 0 1 0 1 1 1 11
osets S to 0
5 ones, set PIO to 0
RLC (IY+disp)
~ - . -
~
This instruction is identical to RLC (IX+displ. but uses the IY register instead of the IX
register.
RLCA - ROTATE ACCUMULATOR LEFT CIRCULAR
Data
Memory
Program
Memory
-
S Z AC
P/0N
0
FI I 101 101
B,C
D.E
H,L
SP
- ~ V
PC
mmmm
~ m m m + 1
IX
IY
I I
R I
07 mmmm
mmmm+ 1
r---t mmmm + 2
r---t mmmm+3
RLCA
----
07
Rotate Accumulator contents left one bit copying bit 7 into Carry.
Suppose the Accumu lator contains 7A16 and the Carry status is set to 1. After the in-
struction
RLCA
has executed. the Accumulator will contain F416 and the Carry status will be reset to 0:
Before After
Accumulator Carry
1011110101 OJ
RLCA should be used as a logical instruction
Accumulator Carry
1111101001 @]
3-135
RLD - ROTATE ONE BCD DIGIT LEFT BETWEEN
THE ACCUMULATOR AND MEMORY LOCATION
Data
m
m+ 1
...-__ mmmm + 2
...-__ mmmm + 3
x
I
y r 5 ppqq
t
pp qq

mmmm
-
Program
Memory
I ED mmm
I 6F
mmm
S Z AC p/O N C

A
B.C
D.E
HL
SP
PC
IX
IV
I
R
RLD
---
ED 6F
The fou r low-order bits of a memory location (specified by the contents of register pair
HU are copied into the four high-order bits of the same memory location The previous
contents of the fou r high-order bits of that memory location are copied into the four
low-order bits of the Accumulator The previous four low-order bits of the Accumulator
are copied into the four low-order bits of the specified memory location.
Suppose the Accumulator contains 7F, 6, HL register pair contains 4000, 6. and memo-
ry location 4000'6 contains 1216 After execution of the instruction
RLD
Memory
Non-zero result. set Z to 0 high-order bit=O, set S to 0
4 ones, set P10 to ,
the Accumulator will contain 7116 and memory location 400016 will contain 2F16:
Before After
Accumulator Memory Accumulator

\ /'
\ -"
", ,"
........
3-136
RR reg - ROTATE CONTENTS OF REGISTER RIGHT THROUGH
CARRY
Data
Memory
Program
Memory
5 Z AC P/O N ~
FIXIXlotxtO\
-.-
~
A
~ . ~
D,E
H,L
SP
- /" !)
PC mmmm ~ m m m + 2
IX
IY
I
I
R
I
CB mmmm
00011001 mmmm + 1
mmmm +2
1-----1mmmm + 3
The illustration shows execution of RR C:
-L\
CB 00011 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Rotate contents of specified register right one bit through Carry
Suppose Register H contains OF 16 and Carry is set to 1, After the instruction
RR H
has executed. Register H wi II contain 8716. and Carry wi II be 1:
Before After
-- --
Register H Carry Register H Carry
1000011111 IT] 10000111
1 sets S to 1
LNon-zero result. set Z to a
3-137
RR (HL) - ROTATE CONTENTS OF MEMORY LOCATION
RIGHT THROUGH CARRY
RR (Ix+disp)
RR (lY+disp)
q+d
m
m + 1
m +2
m+3
m+4
-
s Z AC P '0 N C
Data
rXIXIOIXIOIl
,. Memory I
..
ppq
l"
_/ 9
mmmm ...;,-- -. mmmm + 4
Program
Memory
ppqq
1
I FD mmm
I CB
C;pqq + d'"""'-
mmm
d
mmm
~ -
1E
mmm
mmm
F
A
B.C
DE
HL
SP
PC
IX
IY
I
R
The illustration shows execution of RR (lY+disp):
~ + d i ~ . e l
J;;h
Rotate contents of memory location (specified by the sum of the contents of the IY
register and the displacement value d) right one bit through Carry
Suppose the IY register contains 450016. memory location 450F16 contains 1016_ and
Carry is set to 0 After execution of the instruction
RR (IY+OFH)
memory location 450F16 will contain OE16. and Carry will be 1:
Before After
100011101\ [Q] [j]
Non-zero result set Z to 0 osets S to 0
3 ones. set P/O to 0
RR (IX+disp)
~ -..-
J;;h
This instruction is identical to RR (lY+displ. but uses the IX register instead of the IY
register.
3-138
RR (HU
CB 1E
right one bit through Carry
RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY
Program
Memory
Data
1F mmmm
I-__-Immmm + 1
I-__-Immmm + 2
1-__-1mmmm + 3
s
F I I 101 101
1
'"
s.c
D.E
H.L
SP
- PC mmmm
1
IX
IY
I
I
R I
RRA
1F
Rotate Accumu lator contents rig ht one bit through Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1. After the in-
struction
RRA
has executed, the Accumulator will contain BD16 and the Carry status will be reset to
0:
Before
Accumulator Carry
1011110101 OJ
After
Accumulator Carry
1101 1 1 1 01l @]
3-139
RR (HU
CB 1E
right one bit through Carry
RRA - ROTATE ACCUMULATOR RIGHT THROUGH CARRY
Program
Memory
Data
1F mmmm
I-__-Immmm + 1
I-__-Immmm + 2
1-__-1mmmm + 3
s
F I I 101 101
1
'"
s.c
D.E
H.L
SP
- PC mmmm
1
IX
IY
I
I
R I
RRA
1F
Rotate Accumu lator contents rig ht one bit through Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1. After the in-
struction
RRA
has executed, the Accumulator will contain BD16 and the Carry status will be reset to
0:
Before
Accumulator Carry
1011110101 OJ
After
Accumulator Carry
1101 1 1 1 01l @]
3-139
RRC (HL)-
RRC (IX+disp)
RRC (ly+disp)
ROTATE CONTENTS OF MEMORY LOCATION
RIGHT CIRCULAR
C
Data
Memory
pqq
m
m+ 1
mmmm+2
t-----t mmmm + 3
p
t
pp qq
-
--
Program
mmmm mmmm+2
-
....... Memory
i I CB mmm
I DE mmm
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
The illustration shows execution of RRC (HU:
RRC (HU
~
CB OE
right one bit circularly, copying bit 0 into the Carry status,
Suppose the HL register pair contains 450016. memory location 450016 contains
3416. and Carry is set to 1. After execution of
RRC (HU
memory location 450016 will contain 1A16' and Carry will be 0:
Before After
1001101001 OJ 0011010
lNon-zero result. set Z to 0 osets S to 0
RRC (IX+disp)
~
Rotate contents of memory location (specified by the sum of the contents of the IX
3-141
register and the displacement value d) right one bit circularly, copying bit 0 into the Ca-
rry status.
RRC (IY+disp)
'Xh
This instruction is identicaf to the RRC (IX+disp) instruction, but uses the IY register in-
RRCA - ROTATE ACCUMULATOR RIGHT CIRCULAR
Program
Memory
Data
~
OF mmmm
mmmm+ 1
~ - - - I mmmm + 2
~ __-I mmmm + 3
s Z AcP/ON C
r
F I I 101 10 I
s,c
D,E
H,L
SP
--
PC mmmm -'w mmmm + 1
IX
.......
IV
I I
R
I
RRCA
----
OF
Rotate Accumulator contents right one bit circularly, copying bit 0 into the Carry status.
Suppose the Accumulator contains 7A16 and the Carry status is set to 1 After the in-
struction
RRCA
has executed, the Accumulator will contain 3016 and the Carry status will be reset to
0:
Before
Accu mu lator Carry
1011110101 OJ
After
Accumulator Carry
1001111011 [Q]
RRCA should be used as a logical instruction.
3-142
RRD - ROTATE ONE BCD DIGIT RIGHT BETWEEN THE
ACCUMULATOR AND MEMORY LOCATION
S Z AC Plo N C Data
q
mm
mm+ 1
mmmm+2
1----"""'1mmmm + 3

I
x
I V
r I s
Of
-r=
pp qq
-, V Program
mmmm
I. mmmm+2
- -
Memory
I
ED mm
I
67 mm
F
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
RRD
--.....--
ED 67
The four high-order bits of a memory location (specified by the contents of register pair
HL) are copied into the four low-order bits of the same memory location. The previous
contents of the four low-order bits are copied into the four low-order bits of the Ac-
cumu lator. The previous four low-order bits of the Accumulator are copied into the four
high-order bits of the specified memory location.
Suppose the Accumulator contains 7F16. HL register pair contains 400016. and memo-
ry location 400016 contains 1216. After execution of the instruction
RRD
the Accumu lator will contain 7216 and memory location 400016 will contain F116:
Before After
-- --
Accumu lator Memory
7,'" F' ,
\ \ I
\ I
" '.(
, ... _" ,-"
High-order bit=O. set S to 0
Accumulator Memory
lIID
LNon-mo ,.sult
set Z to 0
3-143
RST n - RESTART
S Z AC p/o N C Data
F
A
B,C
D,E
H,L
SP
PC
IX
IY
I
R
o::::r::n:I:l
Memory
j mm+ 1
""1 mm
(PPQQ-2)
~ ........
ppqq
V"_ ~ m m m +y.
mmmm
Program
Memory
I
I
COOOOOOOOOOxxxOOO
11 xxx 111
I
ppqq-2
ppqq-1
ppqQ
mmmm
mmmm+ 1
mmmm+2
mmmm+3
SUBROUTINE
CALL USING
RST
R
11 xxx 111
Call the subroutine origined at the low memory address specified by n
When the instruction
RST 18H
has executed. the subroutine origined at memory location 001816 is called, The pre-
vious Program Counter contents are pushed to the top of the stack.
Usually. the RST instruction is used in conjunction with interrupt processing. as de-
scribed in Chapter 12,
If your application does not use all RST instruction codes to service
interrupts. do not overlook the possibility of calling subroutines
using RST instructions. Origin frequently used subroutines at ap-
propriate RST addresses. and these subroutines can be called with
a single-byte RST instruction instead of a three-byte CALL instruction
3-144
SBC A.data - SUBTRACT IMMEDIATE DATA FROM
ACCUMULATOR WITH BORROW
s Z AC PIO N J 1
Data
~
ft
~ X - Y Y - C r
Memory
xx
-, V Program
mmmm _ - ..",:.mmm + 2
Memory
I DE
I
"-
YY
F
mmmm
R mmmm+l
mmmm+2
mmmm+3
A
B,C
D,E
H,L
SP
PC
IX
IY
SBC A data
--...- -.-
DE yy
Subtract the contents of the second object code byte and the Carry status from the Ac-
cumulator
Suppose xx=3A16 and Carry=l, After the instruction
SBC A7CH
has executed, the Accumulator will contain B016.
3A
Twos camp of 7C
Twas camp of Carry
1 sets S to 1
Borrow. set C to 1
1 1=0. set P/O to 0
0011 1010
1000 0100
1111 1111
1011 1101
fJ LNon-ze,o <esult. set Z to a
-----Borrow. set AC to 1
The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.
3-145
SBC A,reg - SUBTRACT REGISTER WITH BORROW
FROM ACCUMULATOR
A
B.C
D.E
HL
SP
PC
IX
IY
I
R
r
i S Z AC plO N C
~
xx-yy-C
t
}-Coo,"o:t A B
xx
C. D, E. H or L
is yy
, - ~ m m m + v mmmm
I
I
Data
Program
Memory
l00llxxx mmmm
mmmm+ 1
1------1mmmm + 2
1--__....... mmmm +3
reg SBC A.
-.--'
10011
--.-
xxx
--.-
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Subtract the contents of the specified register and the Carry status from the Accumu la-
tor.
Suppose xx=E316' Register E contains A016. and Carry=l. After the instruction
SSC A,E
has executed. the Accumulator will contain 4216
E3
Two' s camp of AO
Two's comp of 1
asets S to 0
No borrow. set C to a
11 =0. set P/O to a
1 1 1 0 001 1
0110 0000
1 1 1 1 1 1 1 1
0100 0010
r LNoo-,em '"'"'I. ,et Z to a
"------No borrow. set AC to a
The Carry flag is set to 1 for a borrow and reset to aif there is no borrow.
3-146
sac A,(HL)-
sac A,UX+disp)
sac A,UY+disp)
SUBTRACT MEMORY AND CARRY FROM
ACCUMULATOR
S Z AC P/O N C
Data
m
m+ 1
mmmm+2
1-----1 mmmm + 3
IXIXIXIXllIX.
Memory
.1
xx
yy
PO;
pp qq
-
-
mmmm 1
Program
Memory
I 9E mmm
I mmm
F
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SSC A. (HU:
SSC A,(HU
-.,--
9E
Subtract the contents of memory location (specified by the Contents of the HL register
pair) and the Carry from the Accumulator,
Suppose Carry=O. ppqq=400016. xx=3A16. and memory location 400016 contains
7C16. After execution of the instruction
SSC A,(HU
the Accumulator will contain BE16.
3A a01 1
Two'S comp of 7C 1 aa0
Two's comp of Carry
1 010
0100
o
1 sets S to 1
Borrow. set C to 1
OO=O. set P/O to a
1011 1110
}.J L Non-2O'o 'esult. set Z to a
L... Borrow. set AC to 1
The Carry flag is set to 1 for a borrow and reset to 0 if there is no borrow.

DD 9E d
Subtract the contents of memory location (specified by the sum of the contents of the
IX register and the displacement value d) and the Carry from the Accumulator
SBC A,{IY+disp)

FD 9E d
This instruction is identical to the SSC A, {IX+displ instruction, except that it uses the IY
register instead of the IX register,
3-147
SBC HL,rp - SUBTRACT REGISTER PAIR WITH CARRY
FROM HAND L
Data
Memory
Program
Memory
ED mmmm
01xxOO10 mmmm + 1
1-__ mmmm + 2
1-__ mmmm + 3
,
I
Be. DE. HL or SP
contains yyyy
xx xx
J

mmmm
-
I
I
S Z AC PIO N C

B.C
D.E
H.L
SP
PC
IX
IV
I
R
K
01 xx 0010
Subtract the contents of the designated register pair and the Carry status from the HL
register pair.
Suppose HL contains F4A216. BC contains A03416. and Carry=O. After the instruction
SBC HL,BC
has executed. the HL register pair will conta in 546E16:
Two's camp of F4A2
Two's camp of A034
Two's camp of Carry
1111 0100 1010
010111111100
0010
1100
o
osets S to 0
No borrow. set C to 0
OWl 01 00 0 11 0 111 0
... L__ set Z to 0
1 1=0. set P/O to 0 Subtract instruction. set N to 1
The Ca rry flag is set to 1 for a borrow and reset to 0 if there is no borrow.
3-148
SCF - SET CARRY FLAG
Program
Memory
Data
Memory
37 mmmm
1------.. mmmm + ,
1-__...... mmmm + 2
1------4 mmmm + 3
S Z AC P/O N C
~
r I I I I I
,
- ' ~ m m m + v
mmmm
I
I
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
F
SCF
37
When the SCF instruction is executed. the Carry status is set to 1 regardless of its pre-
vious value. No other statuses or register contents are affected.
3-149
SET b.reg - SET INDICATED REGISTER BIT
S Z AC PIO N C
FCIIIIIJ
Data
Memory
A
B.C
O.E
H.L
SP
PC
IX
IY
I
R
r
1
"-
yyyy yyyy
-'-
mmmm mmmm + 2
-
........
I
I
l l ~ ~
CB 11 bbb xxx
-.- --
Bit bbb xxx Register
-
a 000 000 B
1 001 001 C
2 010 010 0
3 011 011 E
4 100 100 H
5 101 101 L
6 110 111 A
7 111
Program
Memory
CB mmmm
11bbbxxx mmmm + 1
mmmm+2
......----1mmmm + 3
SET indicated bit within specified register. After the instruction
SET 2.L
has executed, bit 2 in Register L will be set. (Bit a is the least significant bit.)
3-150
SET b,(HL} - SET BIT b OF INDICATED MEMORY POSITION
SET b, (IX+disp)
SET b, (lY+disp)
S Z AC P/O N C
FCI:IIIJ:]
qq
mm
mm+ 1
mmmm+2
t-----t
mmmm
+ 3
yyyy yyyy
P
f
pp qq
- ~
Program
mmmm
-
I mmmm + 2
......... Memory
I CB mm
I 11bbbl10 mm
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SET b.(HU. Bit 0 is the least significant bit
1 1 ~ ~
CB 11 bbb 110
Bit Set bbb
o 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Set indicated bit within memory location indicated by HL.
Suppose HL contains 400016. After the instruction
SET 5.(HU
has executed. bit 5 in memory position 400016 will be 1.
SET b,(IX+disp)
bbb is the same as in SET b,(HU
Set indicated bit within memory location indicated by the sum of Index Register IX and
displacement
3-151
Suppose Index Register IX contains 400016. After execution of
SET 6.0X+5Hl
bit 6 in memory location 400516 will be 1.
~
FD CB d 11 bbb 110
bbb is the same as in SET b.(HU
This instruction is identical to SET b.(lX+disp), except that it uses the IY register instead
of the IX register
SLA reg - SHIFT CONTENTS OF REGISTER LEFT ARITHMETIC
Data
Program
Memory
CB mmmm
00100001 mmmm + 1
t------4 mmmm + 2
t------4 mmmm + 3
s Z ACP/O N 1.
FIXIXIOIXIOI'I
A
r
u.v
'"
D.E
H.L
SP
~ m m m + ~
PC mmmm
IX
IV
I I
R
I
The illustration shows execution of SLA C:
SLA reg
I ~
CB 00100 xxx
000 for reg=B
001 for reg=C
010 for reg=D
all for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift contents of specified register left one bit. resetting the least significant bit to O.
Suppose Register B contains 1F16. and Carry= 1 After execution of
SLA B
Register B will contain 3E16 and Carry will be zero
3-152
Before
Register B Carry
1000111111 m
After
Register B Carry
0111110 [Q]
osets S to 0
Non-zero result set Z to 0
SLA (HL)-
SLA (lX+disp)
SLA (lY+disp)
SHIFT CONTENTS OF MEMORY LOCATION
LEFT ARITHMETIC

Data
Memory
Program
Memory
CB mmmm
26 mmmm +'
mmmm+2
t-----t mmmm + 3
A

D,E
H,L J- PP qq

mmmm
IX --__p-
lY ------....-------i
I
R
The illustration shows execution of SLA (HL):
SLA (HL)
CB 26
Shift contents of memory location (specified by the contents of the HL register pair} left
one bit resetting the least significant bit to O.
Suppose the HL register pair contains 450016, memory location 450016 contains
8416. and Carry=O. After execution of
SLA (HL)
memory location 450016 will contain 0816, and Carry will be 1.
Before After
-- --
110000100\ IT] 0001000 ill
osets S to 0
one. set P/0 to 0
l Non-zero resu It set Z to 0
3-153
SLA (IX+disp)
li
Shift contents of memory location (specified by the sum of the contents of the IX
register and the displacement value d) left one bit arithmetically. resetting least signifi-
cant bit to 0
SLA (IY+disp)
' ~
This instruction is identical to SLA (IX+disp). but uses the IY register instead of the IX
register.
SRA reg - ARITHMETIC SHIFT RIGHT CONTENTS OF
REGISTER
S Z ACP/ON C
F
A
B,C
D,E
H.L
SP
PC
IX
IY
I
R
IxrXIOlxlOI
-
~
{
141
'-
mmmm
~ m m m + v
-
I
I
Data
Memory
Program
Memory
CB mmmm
00101111 mmmm + 1
mmmm+2
I-----t mmmm + 3
The illustration shows execution of SRA A:
SRA reg
I ~
CB 00101 xxx
000 for reg=B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift specified register right one bit Most significant bit is unchanged,
Suppose Register H contains 5916. and Carry=O. After the instruction
SRA H
has executed. Register H will contain 2C16 and Carry will be 1.
3-154
Before
Register H
10 1 0 1 1 00 11
C
@]
After
Register H
00101100
C
OJ
osets S to 0
L.Non-zero result. set Z to 0
SRA (HL)-
SRA (IX+disp)
SRA (ly+disp)
ARITHMETIC SHIFT RIGHT CONTENTS OF
MEMORY POSITION
Data
Memory
m
m+ ,
m+2
m+3
m+4
+d
L
ppqq
- ~ ~
Program
mmmm mmmm+4
ppqq I- "-
Memory
I DO mmm
I - CB mmm
~ p q q + d ~ d
mmm
~ -
2E mmm
mmm
R
A
Be
D.E
H.L
5P
PC
IX
IY
The illustration shows execution of SRA (IX+disp)
SRA (IX+disp)
~ - . -
~
Shift contents of memory location (specified by the sum of the contents of Register IX
and the displacement value d) right Most significant bit is unchanged.
Suppose Register IX contains 340016. memory location 34AA16 contains 2716. and
Carry=l After execution of
SRA (IX+OAAH)
memory location 34AA16 will contain 1316. and Carry will be 1.
Before After
[001001111 00010011
OJ
osets S to 0
L..Non-zero result. set Z to 0
3-155
SRA (IY+displ
'-;R
This instruction is identical to SRA (IX+displ. but uses the IY register instead of the IX
register.
SRA (HLl
~
CB 2E
Shift contents of memory location (specified by the contents of the HL register pair)
right one bit. Most significant bit is unchanged.
SRL reg - SHIFT CONTENTS OF REGISTER RIGHT
LOGICAL
,
0
~
-
s Z AC P/O N C
FlolxlOlxlOI
- ,
A j
S.C
~ . L
H.L
SP
_/
PC mmmm mmmm+2
IX -
~
IY
I I
R I
Data
Memory
Program
Memory
CB mmmm
00111011 mmmm+ 1
mmmm+2
1-----1mmmm + 3
The illustration shows execution of SRL E:
SRL reg
l ~
CB 00111 xxx
--.-
000 for reg=B
001 for reg=C
010 for reg=D
011 forreg=E
100 for reg=H
101 for reg=L
111 for reg=A
Shift contents of specified register right one bit. Most significant bit is reset to O.
Su ppose Register 0 contains 1F16' and Carry=O. After execution of
SRL 0
Register 0 will contain OF, 6, and Carry will be 1.
3-156
Before
Register D Carry
1000111111 @]
After
Register D Carry
10000 1 1 1 11 [JJ
~
L...Non-zero result. set Z to 0
SRL (HL)-
SRL (IX+disp)
SRL (IV+disp)
SHIFT CONTENTS OF MEMORV LOCATION
RIGHT LOGICAL
Data
m
m+1
mmmm+2
1---....... mmmm + 3
t
pp
I
qq
mmmm
~ m m m + v
Program
Memory
I CB mmm
I 3E mmm
S Z AC PIO N C
: ~ x o X 0 ....
B.C
D.E
H.L
SP
PC
IX
IY
I
R
The illustration shows execution of SRL (HL):
SRL (HL)
-...,.-...-
CB 3E
Shift contents of memory location (specified by the contents of the HL register pair)
right one bit. Most significant bit is reset to O.
Suppose the HL register pair contains 200016, memory location 200016 contains 8F16.
and Carry=O. After execution of
SRL (HU
Carry
memory location 200016 will contain 4716. and Carry will be 1.
Before After
Memory Carry Memory
1100011111 [Q] 1010001111 OJ
~
L.. Non-zero result. set Z to 0
SRL (IX+disp)
~
Shift contents of memory location (specified by the sum of the contents of the IX
register and the displacement value d) right one bit. Most significant bit is reset to O.
3-157
SRL (IY+disp)
' ~
This instruction is identical to SRL (IX+displ. but uses the IY register instead of the IX
register
SUB data -SUBTRACT IMMEDIATE FROM ACCUMULATOR
- ~ J.
xx
___ xx-yy
-, "D Program
mmmm
~ m m m + 2
Memory
I 06
I
.....
yy
A
B.C
D.E
H.L
SP
PC
IX
IY
I mmmm
R mmmm + 1
mmmm+2
mmmm+ 3
S Z AC P/O N C Data
F ~ Memory
SUB data
-,.-. --.-
06 yy
Subtract the contents of the second object code byte from the Accumulator.
SUB 7CH
has executed. the Accumulator will contain BE16
3A 001 1 1 0 1 0
Two's comp of 7C = 1 000 01 00
1011 1110
1 sets S to 1 t-J LNon.zem ,esult. set Z to a
Borrow. set C to 1 L Borrow. set AC to 1
o 0=0. set P/O to 0
3-158
SUB reg - SUBTRACT REGISTER FROM ACCUMULATOR
Program
Memory
Data
Memory
10010xxx mmmm
1-__--1 mmmm + 1
I-__--Immmm + 2
1-__--1 mmmm + 3
, C,
y
S Z AC PIO N C
. ~ ")
mEIEIEJIIE]
f.
-'....... xx-yy
}-CM"I. '" ,
xx
D, E, H or L is y
~ - . ~ m m m + ~
mmmm
1
I
F
A
S.C
D.E
H.L
SP
PC
IX
IY
I
R
reg SUB
----
10010 xxx
--.-
000 for reg=B
001 for reg =C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg =L
111 for reg=A
Subtract the contents of the specified register from the Accumulator.
Suppose xx=E3 and Register H contains A016 After execution of
SUB H
Subtract instruction, set N to 1
osets S to 0
No borrow, set C to 0
the Accumulator will contain 4316-
E3 =:: 1 1 1 0 0 0 1 1
Two's comp of AD = 0 1 1 0 0000
0100 0011
fJ LNon-,em ,.sult, s.t Z to a
.... - -----No borrow, set AC to 0
1 1=0. set P/0 to 0
3-159
SUB (HL) - SUBTRACT MEMORY FROM ACCUMULATOR
SUB (Ix+disp)
SUB (lY+disp)
m
m+ 1
m+2
m+3
+d
Data
x X X X 1 X
Memory
-" J.- xx _ 1,,- xx-yy yy ppqq
- V mmmm
_ 1 mmmm +3 Program
ppqq I-- ......... Memory
I DD mmm
I 96

mmm
d mmm
mmm
A
RC
D.E
H.L
SP
PC
IX
IY
I
R
S Z AC PIO N C

The illustration shows execution of SUB (IX+dl:
SUB (IX+disp)

DO 96 d
Subtract contents of memory location (specified by the su m of the contents of the IX
register and the displacement value d) from the Accumulator.
Suppose ppqq=400016. xx=FF16. and memory location 40FF16 contains 5016 After
execution of
1 1=0. set P/O to 0
SUB (IY+disp)

Su btract instruction. set N to 1
1111 1111
101 1 0000
1010 1111
fJ LNon-zero 'esult, set Z to a
",- No borrow. set AC to 0
1 sets S to 1
No borrow, set C to 0
SUB (IX+OFFH)
the Accumulator will contain AF16
FF
Two's comp of 50 =
FD 96 d
This instruction is identical to SUB (IX+disp). except that it uses the IY register instead
of the IX register.
SUB (HU
96
Subtract contents of memory location (specified by the contents of the HL register pair)
from the Accumulator
3-160
XOR data - EXCLUSIVE-OR IMMEDIATE WITH ACCUMULATOR
S ZACP/ON C
F ~
Data
Memory
A
B,C
D,E
H.L
SP
PC
IX
IV
I
R
- ~ > xx ........ xxyy
- ,,-
Program
mmmm mmmm+2
.......
Memory
I EE
I
"- yy
mmmm
mmmm+ 1
mmmm+2
mmmm+3
XOR data
EE yy
Exclusive-OR the contents of the second object code byte with the Accumulator.
XOR 7CH
has executed, the Accumulator will contain 4616
3A 001 1
7C = 01 1 1
-------
0100
osets S to O ~
1 0 1 0
1 1 00
01 1 0
LNon-zero resu It set Z to 0
LThree 1 bits, set Pia to 0
The Exclusive-OR instruction IS used to test for changes in bit status.
3-161
XOR reg - EXCLUSIVE-OR REGISTER WITH ACCUMULATOR
F
A
B.C
D.E
H.L
SP
PC
IX
IY
I
R
s Z AC P/O N C
- ~ ~
I!IEIIImI[)
f,
I......... xxyy
~ Co,,,LA'
C, 0, E, H or L
is yy
-,
mmmm mmmm + 1
--
I
I
Data
Memory
Program
Memory
lO1Olxxx mmmm
1-----1mmmm + 1
mmmm+2
1-----1mmmm + 3
reg XOR
-..-
10101 xxx
-..-
000 for reg= B
001 for reg=C
010 for reg=D
011 for reg=E
100 for reg=H
101 for reg=L
111 for reg=A
Exclusive-OR the contents of the specified register with the Accumulator.
Suppose xx=E316 and Register E contains A016. After the instruction
XOR E
has executed, the Accumulator will contain 4316.
E3 1 1 1 a
AO = 1 a 1 a
-------
a 1 aa
osets S to o..J
001 1
0000
001 1
L Non-zero resu It set Z to a
LThree 1 bits. set PIO to 0
The Exclusive-OR instruction is used to test for changes in bit status.
3-162

8080A
UNUSED
OPERATION
CODES
8080A/Z80
COMPATIBILITY
FEATURES
8080A/Z80
ASSEMBLY
LEVEL
CONVERSION
2-BYTE
OPERATION
CODES
8080A/Z80
INCOMPATIBILITIES
8080A!Z80 COMPATIBILITY
Although the Z80 microprocessor can certainly be used on
its own merits. one of its important characteristics is its
compatibility with the 8080A microprocessor. This com-
patibility has the following features:
1) All BOBOA machine language instructions are also l80 machine language instruc-
tions
2) All B080A registers are also l80 registers (see Table 3-6l.
3) Almost all 80BOA programs will run on a l80. with some minor differences to be
noted later.
4) The l80 has instructions. registers. and other features not present on the 8080A,
so l80 programs will not generally run on B080A processors.
Note that this compatibility does not extend to assembly
language source statements since l80 assemblers and B080A
assemblers use different operation code mnemonics. Table 3-7
contains a list of the 8080A mnemonic codes and the corres-
ponding Z80 code. while Table 3-8 Is the same list organized
by Z80 code.
Readers should note the binary coding limitations that this com-
patibility places on the extra features of the Z80 microprocessor.
The 8080A has some unused operation codes (see Table 3-9) that
are used for some of the l80's extra instructions. But there are
simply not enough such codes to cover the large number of
features in a simple form.
Thus. many of the added Z80 instructions require a 2-byte opera-
tion code. The first byte is CB. DO. ED. or FD. Note the following
meanings of these codes from Table 3-9:
CB - a register or bit operation
DO - an operation involving register IX
ED - a miscellaneous non-8080A instruction not covered elsewhere
FD - an operation involving register IY
The second byte of the operation code describes the actual operation to be performed.
The end result is that these multi-byte instructions execute rather FASTER AND
slowly (and use more memory) because an additional memory SLOWER
access is required The reader should be aware of this variation in EXECUTING
execution times and try to use faster executing instructions when INSTRUCTIONS
possible. This warning particularly applies to the extra shift
instructions (RLC, RRC, RL. RR. SRA, SRL) and to instructions involving the index
registers IX and IY.
There are a few minor incompatibilities between the
8080A and the Z80. These are:
1) The Z80 uses the P (or P/O) flag to indicate twos com-
plement overflow after arithmetic operations. The 8080A always uses this flag for
parity.
2) The l80 and 8080A execute the DAA instruction differently. On the l80, this in-
struction will correct decimal subtraction as well as decimal addition. On the
8080A, it will correct only decimal addition
3) The l80 rotate instructions clear the AC flag. The 8080A rotate instructions do
not' affect the AC flag.
3-164
Table 3-6. Register and Flag Correspondence between
laO and 8080A
Z80 Regl'ter
A
A'
B
B'
C
C'
o
0'
E
E'
F
F'
H
H'
I
IX
IY
L
L'
R
PC
SP
Z80 Regl'ter Pair,
BC
DE
HL
AF
Z80 Fleg.
C (Carryl
104 (Half -Carry)
N (Subtract)
P/O (Parity/Overflow)
S ISign)
Z (Zero)
8080.\ Regi,ter
A
None
B
None
C
None
o
None
E
None
Least S ~ n i f i c a n t Half of PSW
None
H
None
None
None
None
L
None
None
PC
SP
8080.\ Regl'ter Pel,.
B
o
H
PSW
8080" Fleg,
C (Carry)
AC (Auxiliary Carry)
None
P (Parity)
5 (Sign)
Z (Zero)
The l80 is not compatible with the extra features of
the 808& microprocessor. The codes used for RIM and
SIM on the 8085 are used for relative jumps (Nl and NC) on
the l80.
808&!l80
INCOMPATIBILITIES
TIMING
INCOMPATIBILITIES
Instruction timings on the 8080A, 808&, and Z80 all
differ. Programs that depend on precise instruction tim-
ings will therefore execute properly only on the pro-
cessor for which they were written.
The N flag on the l80 occupies bit 2 of the F register: the corresponding bit in the
Processor Status Word of the 8080A is always a logic "'.
3-165
Table 3-7 Correspondence between 8080A and Z80 Mnemonics
8080A Mnemonic l80 Mnemonic
ACI data ADC A,data
ADC reg or M ADC A,reg or (HLl
ADD reg or M ADD A,reg or (HL)
ADI data ADD A,data
ANA reg or M AND reg or (HLl
ANI data AND data
CALL addr CALL addr
CC addr CALL C,addr
CM addr CALL M,addr
CMA CPL
CMC CCF
CMP reg or M CP reg or (HLl
CNC addr CALL NC.addr
CNZ addr CALL NZ.addr
CP addr CALL P.addr
CPE addr CALL PE.addr
CPI data CP data
CPO addr CALL PO.addr
CZ addr CALL Z.addr
OM
.
OM
f DAD rp ADD HL,rp
OCR reg or M DEC reg or (HLl
DCX rp DEC rp
01 01
EI EI
HLT HALT
IN port IN A.(port)
INR reg or M INC reg or (HLl
INX rp INC rp
JC addr JP C,addr
JM addr JP M.addr
JMP addr JP addr
JNC addr JP NC,addr
JP addr JP P.addr
JNZ addr JP NZ.addr
JPE addr JP PE.addr
JPO addr JP PO,addr
JZ addr JP Z,addr
LOA addr LD A.laddr)
LOAX B or 0 LD A.(BCI or (DEI
8080A Mnemonic laO Mnemonic
LHLO addr LD HL.(addrl
LXI rp.data16 LD 'P.data16
MOV reg.reg or M LD reg.reg or (HL)
MOV reg or M,reg LD reg or (HLl.reg
MVI reg or M.data LD reg or (HLl.data
NOP NOP
ORA reg or M OR reg or (HLl
ORI data OR data
OUT port OUT (port), A
PCHL JP (HLl
POP pr POP pr
PUSH pr PUSH pr
RAL RLA
RAR RRA
RC RET C
RET RET
RLC RLCA
RM RET M
RNC RET NC
RNZ RET NZ
RP RET P
RPE RET PE
RPO RET PO
RRC RRCA
RST n RST n
RZ RET Z
SBB reg or M SBC A,reg or (HLl
SBI data SBC A,data
SHLD addr LD (addrl,HL
SPHL LD SP.HL
STA addr LD laddrl,A
STAX B or 0 LO (BC) or (DE},A
STC SCF
SUB reg or M SUB reg or (HLl
SUI data SUB data
XCHG EX OE,HL
XRA reg or M XOR reg or (HLl
XRI data XOR data
XTHL EX (SPl.HL
3-166
Table 3-8 Correspondence between Z80 and 8080A Mnemonic"
zeo Mnemonic eOeOA Mnemonic
ACC A,data ACI data
ADC A,(HU ADC M
ADC A,reg ADC reg
ADC + displ
-
ADC HL,rp -
ADD A,data ADI data
ADD A,(HLl ADD M
ADD A,reg ADD reg
ADD A,(xv + disp) -
ADD HL,rp DAD rp
ADD IX,PP
-
ADD IY,rr -
AND data ANI data
AND (HU ANA M
AND reg ANA reg
AND (xv + disp) -
BIT b,lHU
-
BIT b,reg -
BIT b,lxV + displ
-
CALL addr CALL addr
CALL C,addr CC addr
CALL M,addr CM addr
CALL NC,addr CNC addr
CALL NZ,addr CNZ addr
CALL P,addr CP addr
CALL PE,addr CPE addr
CALL PO,addr CPO addr
CALL Z,addr CZ addr
CCF CMC
CP data
Cpt data
CP (HLI CMP M
CP reg CMP reg
CP (XV + displ
-
CPO -
CPDR
-
CPI -
CPIR

CPL CMA
DAA DAA
DEC IHU DCR M
DEC reg DCR reg
DEC rp DCX rp
DEC XV -
DEC (XV + displ
-
01 01
DJNZ disp -
EI EI
EX AF,AF'
-
EX DE,HL XCHG
EX (SPI.HL XTHL
EX (SPl.xv
-
EXX
-
HALT HLT
1M m -
IN A,(port) IN port
IN reg,lCI -
INC INR M
INC reg INR reg
Z80 Mnemonic B080A Mnemonic
INC rp INX rp
INC XV

INC (XV + disp) -
IND -
INOR
-
INI -
INIR -
JP addr JMP addr
JP C,addr JC addr
JP (HU PCHL
JP M,addr JM addr
JP NC,addr JNC addr
JP NZ,addr JNZ addr
JP P,addr JP addr
JP PE,addr JPE addr
JP PO,addr JPO addr
JP Z,addr JZ addr
JP xv
-
JR C,disp -
JR disp -
JR NC,disp -
JR NZ,disp -
JR Z,disp -
LD A,(addr) LDA addr
LD A,(Be) or (DE) LDAX B or D
LD A,I -
LD A,R -
LD (addd,A STA addr
LD (addr),BC or DE -
LD SHLD addr
LD (addr),SP -
LD (addr),xv -
LD (Be) or IDEI.A STAX B or D
LD BC or DE,laddrl -
LD HUaddr) LHLD addr
LD (HU,data MVI M,data
LD IHU,reg MOV M,reg
LD I.A -
LD R,A -
LD reg, data MVI reg,data
LD reg,(HU MOV '8g,M
LO reg, reg MOV rag,reg
LO + displ -
LO rp,data16 LXI rp,data16
LO SP.laddr) -
LO SP,HL SPHL
LO SP,xv -
LD xV,data 16 -
LO
-
LO (XV + disp),data -
LO (xV + disp),reg -
LOD -
LOOR -
LDI -
LOIR -
NEG -
NOP NOP
OR data ORI data
- ,nd,cates that there IS no correspondong ,nstructlon.
3-167
Table 3-8. Correspondence between Z80 and 8080A Mnemonics (Continued)
Z80 Mnemonic 8080A Mnemonic
OR (HLI ORA M
OR reg ORA reg
OR (XV + disp) -
OTDR -
OTIR -
OUT (C),reg
~
OUT (port).A OUT port
aUTO -
OUTI -
pop pr pop pr
POP XV -
PUSH pr PUSH pr
PUSH XV -
RES b,(HL) -
RES b,reg -
RES b,(xv + disp} -
RET RET
RET C RC
RET M RM
R ~ T NC RNC
RET NZ RNZ
RET P RP
RET PE APE
RET PO RPO
AET Z RZ
RET! -
RETN
-
RL (HL) -
RL reg -
AL (XV + displ -
RLA RAL
RLC (HL) -
RLC reg -
RLC (XV + disp)
~
RLCA RLC
ALD -
Z80 Mnemonic 8080A Mnemonic
RR (HL) -
RR reg
-
RR (XV + disp) -
RRA RAR
RRC (HL) -
RRC reg
-
RRC (XV + disp) -
RRCA RRC
RRD -
RST n RST n
SBC A,data SBI data
SBC A,IHL) SBB M
SBC A,reg SBB reg
SBC A,(xV + displ -
SBC HL,rp -
SCF STC
SET b,IHL) -
SET b,reg
-
SET b,lxv + disp) -
SLA (HL) -
SLA reg -
SLA (XV + disp) -
SRA (HL) -
SRA reg -
SRA (XV + disp) -
SRL (HL) -
SRL reg
-
SRL (XV + disp) -
SUB data SUI data
SUB (HL) SUB M
SUB reg SUB reg
SUB (XV + disp) -
XOR data XRI data
XOR (HL) XRA M
XOR reg XRA reg
XOR (XV + disp) -
- indicates that there is no corresponding instruction
3-168

CPU registers and status flags explained

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Chapter 3 page 1-42

'4T """ Om"""'... M ROO' "',

xy,(addrl 1hl11012Appqq 20 [ xy(HIl] - [ addr + 1L [xy(LOII - [ addrl

.t:. Ihe conlents of HL to Ihe memory location addressed by the con-

(xy + disp) 11x11101 CBdisp 4 23

load immediate into register.

hclusive-OR contents of register with contents of Accumulator.

16-bit add register pair contents to contents of Hl.

IRotate contents of register left with branch Carry. ~

Shift contents of register right and clear MSB (Logical Shiftl.

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