I2C Basics

I2C bus is a two wire multimaster bus invented by Philips which is used to communicate with peripherals in embedded devices, motherboards etc. The name I2C is derived from IIC (Inter Integrated Circuit). The main objective behind the invention of I2C bus is to establish a simple low pin count bus that can connect different ICs on a circuit board of Television or Radio. Later I2C grew beyond the limits of TV and Radio and now it can be found in almost every computer motherboards and other embedded devices. I2C can also be used for communication between multiple circuit boards in equipments with or without using a shielded cable depending on the distance and speed of data transfer. The advantages and limitations of I2C bus are as follows. Advantages

Only two bus lines are required to establish full-fledged bus. Each slave device connected is uniquely addressable using slave addresses Can choose a short 7 bit addressing or 10 bit addressing (which can accommodate large number of devices on the same bus, but less popular). No strict baud rate specified since the clock is driven directly by the master. True multimaster support with up to 8 masters in a single bus system. Very simple protocol which can be emulated by microcontrollers without integrated I2C peripheral device. Inexpensive Supports up to 3.4 Mbits/sec transfer speeds.

Limitations

7 bit addressing supports only a very small number of devices. Different devices from different manufacturers come with hard coded slave address or address will be configurable in a small range only. This can lead to address clashes sometimes. No automatic bus configuration or plug and play

The Protocol
I2C uses two wires for communication (SDA and SCL). In HS mode these lines are known as SDAH and SCLH. All the devices are connected to these lines in parallel (Multidrop). Every slave device has a unique address witch which masters can select any one of them uniquely for communication.

I2C is a multimaster bus with up to 8 masters can be present on a single bus at any time. Master devices do not need an address unless it implements slave functionality (in a multimaster environment) but still it needs a master code (only in a multimaster environment). A transaction between master and slave happens in different phases. START (Master Slave)

ADDRESS (Master Slave) R/W Bit (Master Slave) ACK (Slave Master) DATA (Master Slave) STOP (Master Slave) The DATA and ACK phases can repeat any number of times to transfer more data to/from the addressed slave.

Addressing
Master devices can choose any one of the connected slaves arbitrarily for communication by using addresses assigned to each slave device. A master does not need an address unless it is designed to behave as a slave in multimaster environment. The I2C specification defines two addressing formats, 7 bit addressing and 10 bit addressing respectively. The 7 bit address format can theoretically address 128 slaves at a time. But practically this is limited to 112 slaves since some addresses are reserved for special purposes. Later the maximum of 112 slave devices per network became a limitation and 10 bit addressing was brought in place to circumvent this. The following table shows the reserved addresses.

Slave Address R/W Bit Description 0000 000 0 General Call Address

0000 000 0000 001 0000 010 0000 011 0000 1xx 1111 1xx 1111 0xx

1 x x x x x x

START Byte CBUS Address Reserved for different bus formats Reserved for future purpose High Speed mode master code Reserved for future purpose 10 bit slave addressing

Start
All transactions that happen on I2C bus always begin with a START condition. Only a master can establish START condition on the bus. The slaves should detect the START condition and be ready to receive the ADDRESS and DATA. The bus is considered to be busy from the point a master establishes START. The bus is released by using STOP condition.

A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition.

ADDRESS
All slave devices connected on to the I2C bus must have a unique addresses. The master devices use this address to select individual slaves for communication. Master sends out the required slave address on to the bus after the START condition is established. All slaves should clock in this address and compare it with its own address. All the slaves except the addressed slave will ignore the message and the addressed slave will respond with an ACKNOWLEDGE. I2C devices can use two types of addressing namely 7bit and 10 bit.

R/W Bit

The R/W bit is used to specify the direction of data transfer and is always set by the master device. This bit is always the last bit of the address byte (Last bit of first address byte in 10 bit addressing). The value of ZERO indicates a write to the slave and ONE indicates a read from the slave. After the direction bit and ACKNOWLEDGE, master will send the data to the slave or read data from the slave depending on the direction. The data transfer will be terminated when master sets STOP condition on the bus.

ACKNOWLEDGE
ACKNOWLEDGE is a way for the devices to let master know that it has transferred a byte successfully over I2C bus. The slaves should acknowledge each byte it receives. ACKNOWLEDGE is defined as a low state on SDA when the master generates clock for acknowledge bit. A high state on SDA at this time is known as NOT ACKNOWLEDGE. The selected slave can choose transfer or not transfer data by appropriately giving or not giving ACKNOWLEDGE. IF the address byte is not acknowledged by the slave, master can abort the transfer by generating STOP or start a new transfer by generating RESTART.

STOP Condition
Master devices establish STOP condition on the bus to let the slaves know that the message is finished. The bus is considered to be busy until master sets STOP condition. After the STOP, the bus is free and any other masters can claim the bus for communication adhering to the arbitration process. A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a STOP condition.

General Call Address (0000 000)

The general call address is used to do broad cast over the entire bus. It addresses all the slaves connected to the bus irrespective of their programmed address. But it is not mandatory that all the connected devices should respond to general call addressing. The devices that not interested in general call can ignore the same. But

those devices make use of general call should acknowledge properly. The byte follows the general call address usually define what action needs to be taken by the slaves in response to the call. The command in the second byte is interpreted based on the value of its LSB. If LSB is zero, the following commands are defined. 00000110 (0x06): When receiving this command, all devices should reset and take in the programmable part of their address. 00000100 (0x04): Take in the programmable part of the address, but do not reset Other values in this scenario are undefined and should be ignored by slaves. When the LSB of the second byte in general call is one , it means that this call is made by a hardware master device who does not have any prior information of the connected slave addresses. In this case the master does the call with its own address so that the slaves can identify the source of the message.

Start Byte (0000 000 1)

Start byte is a special sequence sent out by master device to allow slower microcontrollers that implements I2C slave in firmware rather than hardware. Some microcontroller devices that doesnt have integrated I2C peripheral in hardware, may implement I2C slave functionality in firmware by polling SCL and SDA continuously. This results in wastage of CPU time in polling. The polling rate can be considerably reduced by using Start Byte when master is trying to address the slave device.

The master transmits a START followed by the Start Byte, a dummy acknowledgement and a repeated START. The slowly polling peripheral can detect bus activity by capturing one of the seven zeros transmitted in the Start Byte and switch to a higher polling rate temporarily to clock in the rest of the message. This allows the slave device to keep polling rate low normally and switch to increased polling rate only when necessary.

CBUS Address (0000 001x)

The CBUS compatibility address is used to safely connect both I2C devices and CBUS devices on the same physical bus. Since CBUS and I2C protocols follow different formats, it is necessary to isolate both the traffic from each other. Before starting a CBUS transfer, the CBUS compatibility address is placed on the bus, to which no I2C devices will respond. Then the CBUS data can be transferred over the bus safely. And once CBUS transfer is done, a STOP condition is

established on the bus and all the devices including I2C devices will detect this and become ready to communicate on the bus.

Different Bus Format

(0000 010)
This address is reserved for implement different custom protocols on the same physical bus. Only those devices capable of handling the custom protocol should respond to this address.

High Speed Mode (0000 1XX)

High Speed Mode increases the data transfer speed on I2C bus up to 3.4Mbits per second. The high Speed Mode is fully downward compatible with Standard and Fast modes. This allows both High Speed and Standard/Fast mode devices to be connected to the same physical bus, while pushing data rate up to 3.4 Mbits per second for those devices support High Speed Mode. N

Even in high Speed Mode, the initial phase of the transaction happens in Standard/Fast mode and once the high speed mode is established, the High Speed Mode capable devices switch to high Speed data transfer. This Helps the Standard/Fast mode devices to detect the scenario and safely ignore the bus activities while High Speed transfer is progressing.

The High Speed transfer starts with a START condition followed by the High Speed master code and a mandatory NACK and then a RESTART condition. Till this point everything happens in Standard/Fast mode and after the RESTART, the High Speed capable devices pump up the clock frequency and starts communicating in higher speed. While the low speed devices will wait for a STOP condition on the bus ignoring all other bus activities.

The three lowest bits of the High Speed Mode master code is used to identify different masters on the same bus (Multimaster environment). Unlike Standard/Fast mode multimaster environment, in High Speed mode the arbitration always take place before the slave address is transmitted on the bus (i.e.; before High Speed transfer starts).

Once the devices switch to higher clock frequency, all the transfers takes place with same protocol i2c protocol, but at a higher speed (Slave addressing, Read/Write selection and Data).

10 Bit Addressing
10 bit addressing allows more number of devices connected to the bus at the same time. It is compatible with 7 bit addressing and works as a natural extension to 7 bit addressing. This addressing scheme allows both devices that use 7 bit and 10 bit addressing to be connected to the same bus. In 10 bit addressing scheme, the first address byte start with 11110. This allows the slaves to detect if the addressing scheme is 10 bit or not. Next two bytes from the first address byte and the second address byte together makes a 10 bit address. The devices that supports only seven bit addressing can ignore the message when it sees the leading 11110 in the first address byte. The important thing to notice is that the direction bit does not change its place even in 10 bit addressing. It always is the last bit of the first address byte.

7 Bit Addressing

After the start condition is established, the seven bit slave address is transmitted on to the bus followed by a direction bit (which is the 8th bit). The direction of the data transmission is determined by the value of direction bit. ZERO indicates a write to the slave and ONE indicates read from slave. Only master can decide the direction of data transfer and the slaves are note allowed to override this bit. All the slave devices are required to read the address from the bus and compare it with its own address. Only the addressed slave can acknowledge to the address byte. After the slave acknowledges for masters selection, master transfers data to the bus (for write operation) or read data from the bus (for read operation).

Fast mode
Fast mode compatible devices can transmit/Receive data at up to 400kbits/sec on I2C bus. Fast mode is fully compatible with the standard mode protocol except that the data transfer rate is faster. The hardware is required to transmit are receive data reliably at 400 Kbits/sec. I2C spec recommend that the newly designed devices should incorporate Fast mode or HS mode. The specification puts the minimum requirement for a Fast mode device that the device should be able to synchronize at the rate of 400 Kbits/sec, but then it can stretch the LOW period of the clock to slow down the transfer speed. Fast mode devices should be downward compatible with standard mode bus speed and can communicate with a standard mode device on a 100 Kbits/sec bus. But Standard mode devices cant reliably be used on a fast mode bus and the spec recommends not to use such a combination. Fast mode has the following additional features

Maximum transfer rate on the bus is 400 Kbits/sec No need to worry about compatibility with other buses such as CBUS since it does not support transfers it this bit rate. Inputs of a fast mode device should incorporate spike suppressors and Schmitt triggers on SCL and SDA. This makes communication more reliable and robust at high transfer rates. When not powered, the SCL and SDA lines of a fast mode device should be in floating state so that it wont tie the bus to any particular logic state and block the bus.

I2C Terminology

I2C Stands for Inter Integrated Circuit. A low speed bus invented by Philips to establish communication between different peripheral ICs on a circuit board

Master The device that drives the clock on the bus. Only a master can initiate a transaction on the bus.

Slave The device addressed and driven by the Master. Slave used the clock produced by the master to synchronize and read the data from bus. A slave can not initiate a transaction on the bus.

SCL Stands for Serial Clock Line. The master produces a clock on the SCL pin and send data bits one by one on the data line. The slave uses this clock to synchronize the data on the data line and read it.

SDA - Stands for Serial Data Line. Master outputs the slave address and/or data on to SDA pin synchronized with the clock on SCL. Slaves use this clock to read in the bits from data line.

Address A 7 bit or 10 bit number used to uniquely identify each slave connected on I2C bus.

Standard Mode I2C mode in which data is transferred at 100kbits/sec speed.

Fast Mode I2C mode in which data is transferred at 400kbits/sec speed.

High Speed Mode I2C mode in which data is transferred at 3.4Mbits/sec speed.

Start State of bus which establish the beginning of a transaction on I2C bus. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition.

Stop - State of bus which establish the end of a transaction on I2C bus. A LOW to HIGH transition on the SDA line while SCL is HIGH indicates a START condition.

Acknowledgement Is the response from slave to master and is established as a LOW logic state on the data line.

Multimaster Is a configuration where multiple master devices can be connected to a single physical I2C bus.

SMBUS Basics
System Management Bus (SMBUS) is a simple two wire bus very similar to Philips I2C in bus configuration and protocol, invented by Intel in 1995. SMBUS is designed for communication between peripherals on mother board like voltage sensors, Batteries etc... The processor/Operating system can control the peripheral or the status can be read through SMBUS. The SMBUS and the connected peripherals are usually hidden from the users but operating systems provides APIs to programmatically access the bus. The devices if supported, report their manufacturing information like serial number, vendor ID, Product ID through SMBUS to the operating system. The bus has a Clock, Data and an optional SMBALERT# signal. The bus is very similar to I2C except the addition of optional SMBALERT# signal. The protocol is adapted from I2C but the timings and voltage levels are stricter. In most cases I2C and SMBUS devices can operate on the same bus without much compatibility issues. SMBUS defines a clock frequency between 10 KHz to 100 KHz. Unlike I2C, SMBUS cant have very low clock frequencies. SMBUS specifies 35ms clock low timeout. Because of this, the slave cant stretch clock indefinitely as it does in I2C. I2C and SMBUS differ in ACK/NACK usage also. In I2C, the addressed slave can choose not to acknowledge if it is busy in other tasks. SMBUS protocol demands that the slave should acknowledge its own address no matter what. In SMBUS, NACK is always used as a means to

respond to an invalid command or data. NACK is also used to detect the presence of a removable device like battery. When addressed, if the device does not acknowledge, it is considered that the device is not present on the bus. SMBUS specification lays down different protocols for to be used to communicate with different devices. Device need not to implement all the protocols to be compliant to SMBUS specification. The specification does not define what a device should do when it receives an unsupported command. The commands defined in SMBUS specification are.

Quick Command Send Byte Receive Byte Write Byte/Word Read Byte/Word Process Call Block Read/Write Block Write Block Read Process Call Host Notify Protocol

SMBUS also implements ARP (Address Resolution Protocol) to support dynamic address configuration of the slaves. The address can be hard coded in the slave, but the master can assign a new address to the slave if it wishes to. SMBUS defines an additional bus line which is used as interrupt and is known as SMBALERT#. It is used by slaves to let the master know that there is some event happened which may me of the masters interest.

EEPROM Technology Tutorial - an overview, or tutorial about the basics of the EEPROM technology, a form of non-volatile semiconductor memory.

Semiconductor memory includes: Semiconductor memory types Memory specifications DRAM - dynamic RAM

EEPROM Flash memory MRAM SDRAM SRAM - Static RAM P-RAM - Phase change RAM

The EEPROM is a form of semiconductor memory chip that has been in use for many years. The initials EEPROM stand for Electrically Erasable Programmable Read Only Memory and this gives an insight into its method of operation. The EEPROM is a form of non-volatile memory that can be altered electrically.

EEPROM development
The EEPROM technology was one of the first forms of non-volatile semiconductor memory chip. Its development came out of the standard EPROM technology that was widespread in the late 1970s and 1980s. These EPROM memories could be programmed, typically with machine software, and then later erased by exposing the chip to UV light if the software needed to be changed. Although the erasure process took an hour or so, this was quite acceptable for development environments. However these semiconductor memories could not be erased electrically, and a totally electrical arrangement would have been more convenient. In 1983, a development group at Intel under the leadership of George Perlegos developed a technology based on the existing EPROM technology. With an addition to the existing EPROM structure, the new EEPROM memory could be erased and programmed electrically. The first EEPROM device launched onto the market was the Intel 2816. Later many of those with EEPROM development experience left Intel and set up a new company named Seeq Technology which developed and manufactured further EEPROM technology and other semiconductor memory devices.

EEPROM basics
The advantage of an EEPROM memory, apart from the fact that the data stored is non-volatile, is that it is possible to read data from it and also erase it and write data to it. To erase the data, a relatively high voltage is required, and early EEPROMs needed an external high voltage source. Later versions of these memory chips recognised the difficulty in many circuit designs of having an extra supply just for the EEPROM, and they incorporated the high voltage source into the EEPROM chip. In this way the memory device could run from a single supply, thereby considerably reducing the cost of an overall circuit using an EEPROM and simplifying the design.

When using an EEPROM it is necessary to remember that the read and write cycles are performed much slower than those experienced with RAM. As a result it is necessary to use the data stored in the EEPROM memory in such a way that this does not impede the operation of the overall system. Typically the data stored in it can be downloaded at start-up. It is also important to note that Write and erase operations are performed on a byte per byte basis. EEPROM memory uses the same basic principle that is used by EPROM memory technology. Although there are several different memory cell configurations that can be sued the basic principle that is behind each memory cell is the same. Often the memory cell will comprise two field effect transistors. One of these is the storage transistor. This has what is termed a floating gate. Electrons can be made to become trapped in this gate, and the presence or absence of electrons then equates to the data stored there. The other transistor generally in the memory cell is what is known as the access transistor and it is required for the operational aspects of the EEPROM memory cell.

EEPROM memory types

Within the overall EEPROM family of memory devices, there are two main memory types that are available. The actual way in which the memory device is operated depends upon the flavour or memory type and hence its electrical interface.

Parallel EEPROM memory: Parallel EEPROM devices typically have an 8 bit wide bus which allows it to cover the complete memory of many smaller processor applications. Most devices have chip select and write protect pins and some microcontrollers used to have an integrated parallel EEPROM for storage of the software. The operation of a parallel EEPROM is faster than that of a comparable serial EEPROM, and also the operation is simpler than that of an equivalent serial EEPROM. The disadvantages are that serial EEPROMs are larger as a result of the higher pin count. Also they have been decreasing in popularity in favour of serial EEPROM or Flash as a result of convenience and cost. Flash memory offers better performance at an equivalent cost, whereas serial EEPROMs offer advantages of small size. Serial EEPROM memory: The serial EEPROMs are more difficult to operate as a result of the fact that there are fewer pins are operations must be performed in a serial manner. As the data is transferred in a serial fashion, this also makes them much slower than their parallel EEPROM counterparts. There are several standard interface types: SPI, I2C, Microwire, UNI/O, and

1-Wire are five common types. These interfaces require between 1 and 4 controls signals for operation. Using these interfaces these semiconductor memory devices may be contained within an eight pin package. The result that the packages for these memory devices can be made so small is their chief advantage. EEPROM memory failure modes
One of the main problems with EEPROM technology is its overall reliability. There are two ways in which these memory devices can fail:

Endurance : It is found that during the rewrite operations of the EEPROM memory, the gate oxide in the floating-gate transistors of the memory cell gradually accumulate trapped electrons. The electric field associated with these trapped electrons combines with that of the wanted electrons in the floating gate. As a result the state where there are no electrons in the floating gate still has a residual field, and as this rises as more electrons become trapped, a condition eventually rises when it is not possible to differentiate between the threshold for the zero state cannot be detected and the cell is stuck in programmed state. The manufacturers usually specify minimal number of rewrite cycles being 10 million or more Data retention time : The data retention time is also very important, especially if the EEPROM contains software that is required for the operation of an item of electronics equipment. The data retention period is limited. This results from the fact that during storage, the electrons injected into the floating gate may drift through the insulator as it is not a perfect insulator, especially at increased temperature. This causes any charge being stored in the floating gate to be lost and the memory cell will revert to its erased state. The time taken for this to happen is very long, and manufacturers usually guarantee data retention of 10 years or more for most devices.

Summary
EEPROM technology si still widely used in many areas of the electronics industry. Although Flash has taken over many areas of the market previously dominated by EEPROM memory technology, it is nevertheless used in many areas, especially the serial EEPROM which can be accommodated in very small packages.