FPGA IMPLEMENTATION OF A CHAOTIC OSCILLATOR USING RK4 METHOD Luciana De Micco, Hilda A.

Larrondo Departamentos de Fsica y Electr nica o Facultad de Ingeniera, UNMdP Juan B. Justo 4302 email: ldemicco@.mdp.edu.ar, larrondo@.mdp.edu.ar
ABSTRACT The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices. For digital realizations the Ordinary Differential Equations (ODEs) are replaced by a discrete time system. Furthermore numerical values are expressed in a numerical representation. It is well known that these two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we considered the use of the Eulers algorithm in two different numerical representations: (a) integer arithmetics and (b) single oating point IEEE-754 standard. For applications that require a good agreement between the analog chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be used. Guided by numerical simulations, in this paper we propose an improvement replacing the Eulers algorithm by the fourth order Runge Kutta algorithm (RK4). In order to diminish the required hardware a method based on blocks reusing is proposed. The procedure is exemplied on a Lorenz CS. The whole design was implemented onto a FPGA c EP 3C120F 7 by Altera , using only 12 % of its logic elements, 13% of its embedded multipliers and 34 % of its memory bits. The smallest Ciclone III device where our design ts is the EP 3C40U 484I7.
The authors are CONICET researchers. This work have the nancial support of CONICET and Universidad Nacional de Mar del Plata.

1. INTRODUCTION CS have produced a deep change in our vision of nature because of two opposite properties they have: (a) they are deterministic because their dynamics is governed by a known mathematical model and (b) they are extremely sensitive to initial conditions, and consequently their long term dynamics is unpredictable for nite precision implementations, and it is better described by means of statistical tools. In summary, CS must be included in the class of deterministic systems and also in the class of stochastic systems. The deterministic-stochastic duality makes CS specially interesting for electronic engineering applications, since the signals generated by CS can be used as controlled noise sources; this is a strong motivation to study hardware implementations of CS. It is important to remark that any digital realization of CS requires both the time and the state variables to be discrete. Time discretization forces the use of algorithms to replace the ordinary differential equations modelling the continuous system. State variables discretization is made by a numerical system selection. Discretization of time and nite precision, can completely change the dynamics of the system even destroying the chaotic behavior [1, 2, 3]. Micro controllers, Digital Signal Processors and FPGAs may be used to design digital implementations of CS [4, 5, 6, 7, 8, 9, 10]. For simplicity we studied in previous papers FPGA realizations of CS using the Euler algorithm with both integer arithmetics [11] and oating point number representation [12]. If one is interested in a closer approximation of the continuous chaotic attractor, more involved algorithms are required. In this paper we choose the simplest improvement over the Euler algorithm: the fourth order Runge-Kutta algorithm (RK4). RK4 is a reasonably simple and robust integration algorithm and in general it is a good candidate for the

978-1-4244-8848-3/11/$26.00 2011 IEEE

185

numerical solution of chaotic differential equations, when combined with an intelligent adaptive step-size routine [13]. The Lorenzs system studied in this paper was also implemented by other authors [14, 15]. In [14] the toolbox of the Xilinx System Generator is used under MATLAB Simulink toolbox to convert the MATLAB Simulink model into the Xilinx System Generator model. Then the VHDL code is obtained. One drawback is VHDL automatic code generation tools are non-optimal. The integration operation was approximated with Eulers algorithm, using adding and delay blocks. The implementation proposed in [15] uses RK4 in a 32bit xed point architecture. The application considered is a chaotic random key for data stream encryption that do not require an exact reproduction of the continuous chaotic attractor. As hardware density of digital systems increases oating point computations are becoming increasingly popular, particularly in applications where the variables have a very large dynamic range, or high computing precision is required. This is a reason to study in this paper the implementation in a oating point arithmetics with the IEEE-754 single precision standard representation. To reduce the area required on the FPGA, a reusing procedure of some functional blocks is proposed. The implementation presented in this paper was fully c developed with Quartus II 7.2 development software. The simulation and physical implementation was made c on an Altera Cyclone III EP 3C120 development kit. The results correspond to the Lorenz system but the same methodology can be used for the hardware implementation of many others Lorenz like CS such as R ssler o [16], Chua [17], Chen [18], L [19] etc. Results are u compared with those previously obtained for the same system with Eulers method and: (a) 16 bits integer arithmetic [11] and, (b) oating point single precision [12]. The work is organized as follows: in section 2, the Lorenz oscillator implemented in RK4 method is detailed. Section 3 is about the architecture of the proposed hardware implementation of the system. In section 4 the results are depicted and discussed. Comparisons with previous implementations are made by representing the system in the plane entropy-statistical complexity C H, as explained in [12]. Finally, conclusions and remarks for future work are given in 5. 2. THE LORENZ OSCILLATOR IMPLEMENTED IN THE FOURTH ORDER RUNGEKUTTA METHOD The Lorenz oscillator is a classical example of a continuous dynamical system exhibiting bifurcations and chaotic

behavior as well as multi stability phenomena, such as multiple periods and stagnant dots [20, 21]. It is dened by the following set of three coupled ODEs: dx dt dy dt dz dt = fx = = fy = = fz =

(x y) , x y xz , bz + xy , (1)

where fx , fy and fz are the components of the vector eld f and , and b are parameters. In this paper their values are: = 16; = 45.92; b = 4; (2)

corresponding to a chaotic behavior. The RK4 discrete system for the continuous system given by Eq. 1 is, [22]: x(n + 1) = x(n)+ 1 (1) (2) (3) (4) + kx (n) + 2kx (n) + 2kx (n) + kx (n) 6 y(n + 1) = y(n)+ 1 (1) (2) (3) (4) ky (n) + 2ky (n) + 2ky (n) + ky (n) , 6

(3)

where x(n), y(n), and z(n) are the time series that con(i) stitutes the output of the project, and the values of k (n) for i = 1, ..., 4 are:
(1) kx (n) = h fx [x(n), y(n), z(n)]

z(n + 1) = z(n)+ 1 (1) (2) (3) (4) kz (n) + 2kz (n) + 2kz (n) + kz (n) 6

(2) kx (n) = h fx [x(n) +

ky (n) kx (n) , y(n) + , 2 2 (1) kz (n) ] z(n) + 2 ky (n) kx (n) , y(n) + , 2 2 (2) kz (n) z(n) + ] (4) 2
(2) (2)

(1)

(1)

(3) kx (n) = h fx [x(n) +

186

clk
1/34
c0=clk/34

1/(34*4)

Field
+

c1=c0/4

1/6(k1+2k2+2k3+k4)

x(n)y(n)z(n)

k
generator
Step1:0 Step2:k1/2 Step3:k2/2 Step4:k3

function

f()
34 cycles

Step1:k1 Step2: k2 Step3: k3 Step4: k4

Slope generator

c1 Reg

k={kx ky kz}

x0 y0 z0

Fig. 1. Datapath.
Field function output
Step1 Step2 Step3 Step4 Step1 Step2 Step3 Step4 Step1 Step2 Step3 Step4

k1

k2

k3

k4

k1

k2

k3

k4

k1

k2

k3

k4

time

c0 =clk/34
Slope generator output

time to compute k Slope1=

Slope0=0
c1 =c0/4

1/6(k1+2k2+2k3+k4)

SlopeN

x output

x0

x1=x0+Slope1
time to compute x1

xN=xN-1+SlopeN

Fig. 2. Time diagram of the RK4 iteration process.

(4) (3) (3) kx (n) = h fx [x(n) + kx (n), y(n) + ky (n), (3) z(n) + kz (n)]

produces the output 1/6 (k + 2k + k + k ) sent to the second Adder to obtain the new value of x1 . Identical blocks are used for variables y and z. Once x1 , y1 and z1 are known they are sent to the block Register and the cycle starts again with Step 1. Blocks k-generator and Field-function of Fig. 1 constitute the brain of the RK4 solver and are reused as explained above to reduce the required FPGA area and power consumption. The block Field function requires at least 34 clock cycles of the main clock (clk ) to nish all the calculations and give a valid result for f (see Eq. 1). That is the reason c0 = clk /34. Furthermore four cycles of c0 are required to get the new value of the time series. Consequently the overall frequency turns out to be c1 = c0 /4 = clk /136. The Phase Locking Loop (PLL) was implemented c with the ALT P LL block from the Altera library, this function is fully parameterizable and admits the generation of up to four simultaneous clock signals. These signals must be multiples and / or dividers of the input clock. In this case we have employed this PLL to generate the clock signals c0 and c1 . The hole system is enabled by the signal locked, also coming from the PLL. 4. RESULTS The timing diagram for the outputs x, y and z as well as all the clocks (clk = 125 M Hz, c0 3.676 M Hz and the overall frequency c1 0.9 M Hz) are shown in Fig. 3. This Fig. is provided by the simulation software in c the Quartus II environment. Note that the values are expressed by unsigned integers only in the representac tion generated by the Quartus software, in spite they are evaluated correctly as oating point numbers in the IEEE 754 standard. At each rising edge of c1 the current value at the input of the Register block is sampled and stored in the latch until the next rising edge of c1 . The block Field (i) fuction holds in its outputs the values of kx and after the transient time due to calculations (about 34 cycles of clk ) these values are read by the block Slope generator as can be seen in Fig. 2. The compilation results c in Quartus II show that the whole design uses 12% of the logic elements of the device, 13% of the 9 bits embedded multipliers and only 34% of the total memory bits, see Table 1. The design ts in a Cyclone III c EP 3C40U 484I7 of Altera available in our lab. In order to perform the hardware evaluation of the design on the Development Kit Board, SignalT ap II Embedded Logic Analyzer was used. This tool provided

(1)

(2)

(3)

(4)

where h is the step size. Similar expressions are obtained for y and z. 3. PROPOSED ARCHITECTURE A simplied scheme of the hardware implementation is shown in Fig. 1 with the corresponding time diagram for the time series {x} shown in Fig. 2. Here, the four steps required to complete the RK4 cycle are shown. The process starts when the initial conditions for the state variables {x0 , y0 , z0 } are loaded in the block Register. Here Step 1 of the cycle, shown in Fig. 2, starts. These values are simultaneously sent to the rst and second Adder. The block k- generator is loaded with a zero (1) value. The block Field function produces k = k given by Eq. 4 and this value is fed back to the block (1) k-generator, that produces the new k /2 value, in Step 2. (2) The block Field function produces the value k , (2) that is fed back to the block k-generator to produce k /2. This procedure repeats till the four k values are gener(1) (4) ated (each one in each Step) and k to k are available at the input of the block Slope generator. This block

187

c Fig. 3. Timming diagram of the simulation in Quartus II environment

Fig. 4. Signal Tap II outputs and then it reduces the FPGA memory bits required. 5. CONCLUSIONS A method to implement in real time a chaotic dynamical system onto a FPGA board is introduced. The method is exemplied with a Lorenz chaotic system but the proposed solution can be used for the hardware implementation of many others Lorenz like chaotic systems such as R ssler, Chua, Chen, L ...etc just by changing the o u Field function block. The realization proposed here, with the reusing procedure leaves free resources in the selected FPGA as it uses 12% of the logic elements of the device, 13% of the 9 bits embedded multipliers and only 34% of the total memory bits, see Table 1. The design ts into a smaller Cyclone III device, the EP 3C40U 484I7. The constraint to use even smaller Cyclone III devices is the bits of memory requirement. In view of the free resources it is possible an improvement of the proposed design. Our future work will include the use of a ne and deeper pipelining and parallel computation, a variable step algorithm and double precision representation. 6. ACKNOWLEDGEMENTS This work have the nancial support of Universidad Nacional del Mar del Plata and CONICET.
7. REFERENCES [1] S. Callegari, G. Setti, and P. J. Langlois, A cmos tailed tent map for the generation of uniformly distributed chaotic sequences, in Proceedings of ISCAS97, I. Cyrcuits and S. Society, Eds., vol. 1. IEEE, 2003, pp. 781 784.

c Table 1. Device utilization summary Altera Cycone III EP 3C120F 780C. Total logic elements: 14290 out of 119088 Total memory bits: 1353646 out of 3981312 Embedded Multiplier 9-bit elements: 77 out of 576

c by Altera is a system- level debugging tool that captures and displays the signal behavior in real-time. It allows one to detect interactions between hardware and software in the system design. After capturing and saving the data in a SignalT ap II le they can be analyzed and viewed in a waveform [23]. The clock signals c0 and c1 as well as the outputs x, y and z are shown in Fig. 4. In Figs. 5 and 6 the time series and the attractor obtained by the hardware implementation are displayed, using h = 0.005. It is well known that chaotic systems are very sensitive to initial conditions. Consequently it is not possible to compare different realizations of the same system by means of the respective time series. It was shown that a statistical evaluation of the respective time series is a better methodology [24, 2, 12]. The systematic statistical evaluation of different realizations in FPGA is a work in progress, but preliminary results show that the implementation in RK4 presented here may be used to produce chaotic time series with the same statistical properties than those obtained by numerical integration with more involved variable step methods, up to h = 0.05. This value of h represents an important improvement over our previous realization using the Euler algorithm that required h 0.0045 [12]. This 10 times higher h implies that the number of time intervals required to cover a given evolution time is reduced in a factor 10

188

[6] G. Mazzini, G. Setti, and R. Rovatti, Chaotic complex spreading sequences for aynhchronous ds-cdma-part 1: System modeling and results, IEEE Trans. Circuits Sys. 1, vol. 44, no. 10, pp. 937947, 1997. [7] G. Setti, M. Balestra, and R. Rovatti, Experimental verication of enhanced electromagnetic compatibility in chaotic fm clock signals, in Proceedings of ISCAS00. IEEE Circuits and Systems Society, 2000, pp. III229 232. [8] S. Callegari, R. Rovatti, and G. Setti, Chaos-based fm signals: application and implementation issues, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 8, pp. 11411147, Agosto 2003.

Fig. 5. Lorenz time series.

[9] L. De Micco, R. A. Petrocelli, and H. A. Larrondo, Constant envelope wideband signals using arbitrary chaotic maps, Proceedings of XII RPIC, 2007. [10] L. De Micco, R. A. Petrocelli, D. O. Carrica, and H. A. Larrondo, Muestreo catico para la adquisicin de seales de baja frecuencia con ruido de alta frecuencia, Proceedings de la XII Reunin de Trabajo en Procesamiento de la Informacin y Control, 2007. [11] C. M. Gonz lez, H. A. Larrondo, C. A. Gayoso, and a L. J. Arnone, Generaci n de secuencias binarias pseudo o aleatorias por medio de un mapa ca tico 3d, in Proceedo ings del IX Workshop de IBERCHIP, 2003. [12] L. De Micco, O. G. Zabaleta, C. M. Gonzlez, C. M. Arizmendi, and H. A. Larrondo, Estocasticidad de un atractor catico determinista implementado en fpga, Proceedings Iberchip 2010, Febrero 2010. [13] W. Oevel and M. Sofroniou, Symplectic runge-kutta schemes ii: Classication of symmetric methods. [14] M. A. Aseeri, M. I. Sobhy, and P. Lee, Lorenz chaotic model using led programmable gate array (fpga), Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, vol. 1, no. I, pp. 52730, 2002. [15] M. Azzaz, C. Tanougast, S. Sadoudi, and A. Dandache, Real-time fpga implementation of lorenzs chaotic generator for ciphering telecommunications, Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA 09. Joint IEEE North-East Workshop on, pp. 1 4, 2009. [16] O. E. Rssler, An equation for continuous chaos, Physics Letters A, vol. 5, p. 397398, 1976. [17] T. Matsumoto, A chaotic attractor from chuas circuit, IEEE Transaction on Circuits and Systems, vol. 31, pp. 10551058, 1984. [18] T. Ueta and G. Chen, Bifurcation analysis of chens attractor, Int. J. Bifurcation and Chaos, vol. 10, pp. 1917 1931, 2000. [19] S. Lu, Attractors for nonautonomous reactiondiffusion systems with symbols without strong translation compactness, Asymptotic Analysis, vol. 54, no. 3-4, pp. 197 210, 2007.

Fig. 6. Lorenz attractor.

[2] L. De Micco, H. A. Larrondo, A. Plastino, and O. A. Rosso, Quantiers for randomness of chaotic pseudo random number generators, Philosophical Transactions of the Royal Society A, vol. 367, pp. 32813296, 2009. [3] L. De Micco, C. M. Gonz lez, H. A. Larrondo, M. T. a Martn, A. Plastino, and O. A. Rosso, Randomizing nonlinear maps via symbolic dynamics, Physica A, vol. 387, pp. 33733383, 2008. [4] R. M. Hidalgo, J. G. Fernndez, R. R. Rivera, and H. A. Larrondo, Versatile dsp-based chaotic communication system, Electronic Letters, vol. 37, pp. 12041205, 2001. [5] A. Ali-Pacha, N. Hadj-Said, A. MHamed, and A. Belgoraf, Lorenzs attractor applied to the stream cipher (alipacha generator), Chaos, Solitons and Fractals, vol. 33, no. 5, pp. 1762 1766, 2007. [Online]. Available: http://www.sciencedirect.com/science/article/B6TJ44JYKMN1-1/2/7b1aa936c2c11a007b8967c3121d393a

189

[20] J. C. Sprott, Lyapunov exponent and dimension of the lorenz attractor, http://sprott.physics.wisc.edu/chaos/lorenzle.htm, 2005. [21] E. N. Lorenz, Deterministic non periodic ow, Journal of the Atmospheric Sciences, vol. 20, pp. 130 141, 1963. [22] J. C. Butcher, Numerical Methods for Ordinary Differential Equations, 2nd ed., L. John Wiley & Sons, Ed.,

2008. [23] ALTERA, Quartus II Handbook Version 9.1, 2009. [24] O. A. Rosso, L. De Micco, H. A. Larrondo, M. T. Martn, and A. Plastino, Generalized statistical complexity measure: a new tool for dynamical systems, International Journal of Bifurcation and Chaos, vol. 20, no. 3, pp. 775785, 2010.

190