COURSE No.

& Title : SEWPZC261 DIGITAL ELECTRONICS & MICROPROCESSORS (QUESTION BANK)

Objective Questions. Topic: Number System and Codes (Ch 2)

1. The number of digits in octal system is a.8 b.7 c.10 d. none 2..The number of digits in Hexadecimal system is a.15 b.17 c.16 d. 8 3.The number of bits in a nibble is a.16 b.5 c.4 d.8 4.The digit F in Hexadecimal system is equivalent to ------ in decimal system a.16 b.15 c.17 d. 8 5.Which of the following binary numbers is equivalent to decimal 10 a.1000 b.1100 c.1010 d.1001 6.The number FF in Hexadecimal system is equivalent to ------ in decimal system a.256 b.255 c.240 d.239

7. Numbers are stored and transmitted inside a computer in a. binary form b. ASCII code form c. decimal form d. alphanumeric form 8.The decimal number 127 may be represented by a. 1111 1111B b. 1000 0000B c. EEH

d. 0111 1111 9.. A byte corresponds to a. 4 bits b. 8 bits c. 16 bits d. 32 bits 10.A gigabyte represents a.1 billion bytes b. 1000 kilobytes c. 230 bytes d. 1024 bytes 11. A megabyte represents a. 1 million bytes b. 1000 kilobytes c. 220 bytes d. 1024 bytes 12.. A Kb corresponds to a. 1024 bits b. 1000 bytes c.210 bytes d. 210 bits 13.A parity bit is a. used to indicate uppercase letters b. used to detect errors c. is the first bit in a byte d. is the last bit in a byte 14.In hexadecimal number system,A is equal to decimal number a.10 b.11 c.17 d.18 15.Hexadecimal number F is equal to octal number a.15 b.16 c.17 d.18 16.Hexadecimal number E is equal to binary number a.1110 b.1101 c.1001 d.1111 17.Binary number 1101 is equal to octal number a.15 b.16 c.17 d.14

18.Octal number 12 is equal to decimal number a.8 b.11 c.9 d. none 19.Decimal number 10 is equal to binary number a.1110 b.1000 c.1001 d.1010 20.Binary number 110011011001 is equal to decimal number a.3289 b.2289 c.1289 d.289 21.1111+11111= a.101111 b.101110 c.111111 d.011111

22.Binary multiplication 1*0= a.1 b.0 c.10 d.11 23.4 bits is equal to a. 1 nibble b.1 byte c. 2 byte d. none of above 24.The parity bit is a. always 1 b. always 0 c.1 or 0 d.none of above 25.In 2 out of 5 code,decimal number 8 is a.11000 b.10100 c.1100 d.1010 26. (23.6) 10=.2 a.11111.10011

b.10111.10011 c.00111.101 d.10111.1 27.BCD number 0110011=.10 a.66 b.67 c.68 d.69 28.. Which numbering system employs only ten digits?

binary hexadecimal arabic octal

29 .

The digits that may be used in the unit column of the decimal numbering system are:

0 through 15 0 through 9 1 through 10 1 through 16

30

To distinguish between numbering systems, one may refer to the:

reset and carry action radix positional weight significant digits

31 .

A numbering system is sometimes identified by a:

radix superscript significant digit positional weight base subscript

32.

In the decimal system, what may the unit value be called?

LSD MSB LSB MSD

33

Which figure indicates the decimal numbering system is in use?

72 78 710 716

34

Within the decimal number 3456, the 4 has a value of 400 due to its:

digit value insignificance radix positional weight

35 . With decimal notation, by which factor does each position to the left of the decimal point increase?

a. b. c. d.

a positive power of ten the LSB value the MSD value a negative power of ten

36.
a. b. c. d.

Reset and carry occurs after any decimal column reaches what value?

5 7 9 10

37 .
a. b. c. d.

With a 4-digit decimal number, how many resets and carries are possible?

1 2 3 4

38 .
a. b. c. d.

With the decimal system, after 999 is reset, what is the value of each carry?

1 10 100 1000

39 .
a. b. c. d.

What is the radix for the binary numbering system?

16 10 8 2

40 .
a. b. c. d.

The positional weight of the binary one in the binary number 001000 is represented by:

21 22 23 24

41 .
a. b. c. d.

What reference is used for the left-most position within a given binary?

LSD MSB LSB MSD

42 .
a. b. c. d.

In a binary number, the column for the LSB is represented by 20, which has a value of:

8 4 2 1

43 . If decimal numbers 28 and 3 are converted to the binary system and then added, which position would receive the last carry?
a. b. c. d. the second column each column no column the sixth column

44 .
a. b. c.

A decimal number may be converted to binary by continually subtracting the:

largest possible power of two smallest possible power of ten largest possible power of eight

d.

largest possible power of sixteen

45

What is 3110 converted to binary?

a. b. c. d.

110001 011111 101011 111110

50 .
a. b. c. d.

What is the decimal value of the binary number 111110?

31 62 64 126

51 .
a. b. c. d.

The sum of a binary 10101010 plus a binary 01111 is:

128 170 185 252

52 .
a. b. c. d.

What is the resultant in binary of the decimal problem 49 + 01 = ?

01010101 00110101 00110010 00110001

53 . After conversion, what would a 4-digit binary display show when a reset and carry from a decimal 15 has occurred?
a. b. c. d. 0000 0001 1110 1111

54 .
a. b.

What is a base 16 numbering system called?

binary octal

c. d.

coded decimal hexadecimal

55 .
a. b. c. d.

One system that might be used as a short hand for large binary strings would have:

high value decimal numbers a radix of 16 equal decimal equivalents random octal values

56 .
a. b. c. d.

Hexadecimal letters A through F are used for decimal equivalent values of:

1 through 6 9 through 14 10 through 15 11 through 17

57

With the number 8BF16, what is the positional weight of the 8?

a. b. c. d.

16 256 4096 8192

58 .
power of:

A decimal number may be converted to HEX by continually subtracting the largest possible

a. b. c. d.

16 10 08 02

59

What is the binary value of 12316?

a. b. c. d.

100100011 001100011 111011111 110011100

60 .
a.

What is the result when a decimal 5238 is converted to base 16?

327.375

b. c. d.

12.166 1388 1476

What is the HEX value of a binary 1111111111?

61 .
a. b. c. d.

3FF 400 200 FFF

62

What would be the binary result if a HEX value of F9 is added to a HEX 1?

a. b. c. d.

011111001 011111101 011111010 100000000

63 .

Hexadecimal and octal numbering systems are similar for the first:

a.9 digits b.8 digits c.7 digits d.6 digits

64 .

What is the positional weight of the MSB for octal number 7726? a. b.

84

83 c. 82
d.

65 .

What is the binary equivalent of octal number 1126?

a.10110011000 b.010 101 110 c.1001010110 d.10010101110

66 .

What is the difference between binary coding and binary coded decimal?

a. b. c. d.

BCD is pure binary. Binary coding has a decimal format. BCD has no decimal format. Binary coding is pure binary.

67 .

Which type of error was eliminated through the use of the gray code?

a. timing b.decoding c.encoding d.conversion

69 . What is the decimal value of 0011 1001 0111BCD?

a.7927 b.919 c.1627 d.397

68 .

Unlike most binary codes, the excess-3 code uses:

octal notation b. an extra three digits c. an offset d. decimals through 15

a.

69 .

The ASCII code allows encoding for how many keyboard characters?

a.64 b.128 c.256 d.512

70.What is the binary equivalent of the decimal number 368 (A) 101110000 (B) 110110000 (C) 111010000 (D) 111100000

71.The decimal equivalent of hex number 1A53 is (A) 6793 (B) 6739 (C) 6973 (D) 6379

72.The Gray code for decimal number 6 is equivalent to (A) 1100 (B) 1001 (C) 0101 (D) 0110

73.The 2s complement of the number 1101101 is (A) 0101110 (B) 0111110 (C) 0110010 (D) 0010011 74.The code where all successive numbers differ from their preceding number by single bit is (A) Binary code. (B) BCD. (C) Excess 3. (D) Gray. Ans: D

75.The hexadecimal number for (95.5)10 is (A) ( 5F.8 )16 (B) ( 9A.B) 16 (C) ( 2E.F) 16 (D) ( )5A.4 16 76.The octal equivalent of ( )247 10 is (A) ( )252 8 (B) ( )350 8 (C) ( )367 8 (D) ( )400 8 77. Convert decimal 153 to octal. Equivalent in octal will be (A) (231)8 . (B) ( )331 8 . (C) ( )431 8 . (D) none of these. Ans: A 78. The decimal equivalent of ( )1100 2 is (A) 12 (B) 16 (C) 18 (D) 20 Ans: A 79. The binary equivalent of ( )FA 16 is (A) 1010 1111 (B) 1111 1010 (C) 10110011 (D) none of these Ans: B 80.The result of adding hexadecimal number A6 to 3A is (A) DD. (B) E0. (C) F0. (D) EF.

Objective Questions. Topic: Boolean algebra and logic Gates.

(Ch 2, 3)
1.IC s are: a. analog b. digital c. both analog and digital d. mostly analog 2.The rate of change of digital signals between High and Low Level is a. very fast b. fast c. slow d. very slow 3. Digital circuits mostly use a. Diodes b. Bipolar transistors c. Diode and Bipolar transistors d. Bipolar transistors and FETs 4.Logic pulser a. generates short duration pulses b. generate long duration pulses c. generates long and short duration d. none of above 5.What is the output state of an OR gate if the inputs are 0 and 1? a.0 b.1 c.3 d.2 6.What is the output state of an AND gate if the inputs are 0 and 1? a.0 b.1

c.3 d.2 7.A NOT gate has... a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 8.An OR gate has... a. Two inputs and one output b. One input and one output c. One input and two outputs d. none of above 9.The output of a logic gate can be one of two _____? a. Inputs b. Gates c.States d. none 10.Logic states can only be ___ or 0. a. 3 b. 2 c.1 d.0 11.The output of a ____ gate is only 1 when all of its inputs are 1 a. NOR b. XOR c. AND d. NOT 12.A NAND gate is equivalent to an AND gate plus a .... gate put together. a. NOR b. NOT c. XOR d. none 13.Half adder circuit is ______? a. Half of an AND gate b. A circuit to add two bits together c. Half of a NAND gate d. none of above 14.An output of combinational ckt depends on a. present inputs b. previous inputs c. both present and previous d .none of above

15.Which are universal combinational gates a. NAND & NOR b. NOT & AND

c. X-OR & X-NOR d. none of above 16. Which is correct: a. A.A=0 b. A+1=A c. A+A=A' d. A.A'=0 17.The total number of input states for 4 input or gate is a.20 b.16 c.12 d.8 18.In a 4 input OR gate,the total number of High outputs for the 16 input states are a.16 b.15 c.13 d. none of above 19.In a 4 input AND gate,the total number of High outputs for the 16 input states are a.16 b.8 c.4 d.1 20.A buffer is a. always non-inverting b.always inverting c. inverting or non-inverting d.none of above 21.An AND gate has two inputs A and B and one inhibits input S.Output is 1 if a.A=1,B=1,S=1 b. A=1,B=1,S=0 c. A=1,B=0,S=1 d. A=1,B=0,S=0 22. An AND gate has two inputs A and B and one inhibits input S.Out of total 8 input states,Output is 1 in a. 1 states b. 2 states c. 3 states d. 4 states 23.In a 3 input NOR gate,the number of states in which output is 1 equals a. 1 b. 2 c. 3 d. 4 24.Which of these are universal gates a. only NOR

b. only NAND c. both NOR and NAND d. NOT,AND,OR 25. In a 3 input NAND gate, the number of gates in which output in 1equals a.8 b.7 c.6 d.5 26. A XOR gate has inputs A and B and output Y.Then the output equation is a.Y=A+B b.Y=A B+AB c.AB+ AB d.AB+AB 27.A 14 pin NOT gate IC has..NOT gates a.8 b.6 c.5 d.4 28.A 14 pin AND gate IC has..AND gates a.8 b.6 c.4 d.2 29.The first contribution to logic was made by a. George Boole b. Copernicus c. Aristotle d. Shannon 30.Boolean Algebra obeys a. commutative law b. associative law c. distributive law d. commutative, associative, distributive law 31. A+(B.C)= a. A.B+C b. A.B+A.C c. A d.(A+B).(A+C) 32.A.0= a. 1 b. A c. 0 d. A or 1 33.A+A.B= a. B b. A.B

c. A d. A or B 34.Demorgans first theorem is a. A.A=0 b. A=A c. (A+B)=A.B d. (AB)=A+B 35. Demorgans second theorem is a. A.A=0 b. A=A c. (A+B)=A.B d. (AB)=A+B 36. Which of the following is true a. SOP is a two level logic b. POS is a two level logic c. both SOP and POS are two level logic d. Hybrid function is two level logic 37.The problem of logic race occurs in a. SOP functions b. Hybrid functions c. POS functions d. SOP and POS functions 38. In which function is each term known as min term a. SOP b. POS c. Hybrid d. both SOP and POS 39. In which function is each term known as max term a. SOP b. POS c. Hybrid d. both SOP and Hybrid 40. In the expression A+BC, the total number of min terms will be a.2 b. 3 c.4 d. 5 41.The min term designation for ABCD is a.m0 b. m10 c. m14 d. m15 42. The function Y=AC+BD+EF is a. POS b. SOP c. Hybrid d. none of above

43. The expression Y=M(0,1,3,4) is a. POS b. SOP c. Hybrid d. none of above 44. AB+AB= a. B b. A c.1 d. 0 45. In a four variable Karnaugh map eight adjacent cells give a a. Two variable term b. single variable term c. Three variable term d. four variable term 46.A karnaugh map with 4 variables has a. 2 cells b. 4 cells c. 8 cells d.16 cells 47.In a karnaugh map for an expression having dont care terms the dont cares can be treated as a. 0 b. 1 c. 1 or 0 d. none of above 48. The term VLSI generally refers to a digital IC having a. more than 1000 gates b. more than 100 gates c. more than 1000 but less than 9999 gates d. more than 100 but less than 999 gates 49.Typical size of an IC is about a.1*1 b. 2*2 c. 0.1*0.1 d. 0.0001*0.0001 50.A digital clock uses..chip a. SSI b. LSI c. VLSI d. MSI 51. Digital technologies being used now-a-days are a. DTL and EMOS b. TTL, ECL, CMOS and RTL c. TTL, ECL and CMOS d. TTL, ECL, CMOS and DTL

52. A half adder can be used only for adding a. 1s b. 2s c. 4s d. 8s 53. A 3 bit binary adder should be a. 3 full adders b. 2 full adders and 1 half adder c. 1 full adder and 2 half adder d. 3 half adders 54. when two 4 bit parallel adders are cascaded we get a. 4 bit parallel adder b. 8 bit parallel adder c. 16 bit parallel adder d. none of above 55. The widely used binary multiplication method is a. repeated addition b. add and shift c. shift and add d. any of above 56.When microprocessor processes both positive and negative numbers, the representation used is a. 1s complement b. 2s complement c. signed binary d. any of above 57. The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the response for the blank space that will BEST make the statement true.) a. AND/OR b. NAND c.NOR d.OR/AND 58 . Each "1" entry in a K-map square represents: a. a HIGH for each input Truth Table condition that produces a HIGH output.
b.

a HIGH output on the Truth Table for all LOW input combinations.

c. a LOW output for all possible HIGH input conditions. d. a DON'T CARE condition for all possible input Truth Table combinations.

59 .

Looping on a K-map always results in the elimination of: variables within the loop that appear only in their complemented form. variables that remain unchanged within the loop. variables within the loop that appear in both complemented and uncomplemented form. variables within the loop that appear only in their uncomplemented form.

60 .

Which of the following expressions is in the sum-of-products form? (A + B)(C + D) (AB)(CD) AB(CD) AB + CD

61 .

Which of the following is an important feature of the sum-of-products form of expressions? All logic circuits are reduced to nothing more than simple AND and OR gates. The delay times are greatly reduced over other forms. No signal must pass through more than two gates, not including inverters. The maximum number of gates that any signal must pass through is reduced by a factor of two.

62 .

Which of the following expressions is in the product-of-sums form? (A + B)(C + D) (AB)(CD) AB(CD) AB + CD

63.

Solve the network in Figure 4-1 for X.

A + BC + D ((A + B)C) + D D(A + B + C) (AC + BC)D 64 . A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? The output of the gate appears to be open. The dim indication on the logic probe indicates that the supply voltage is probably low.

The dim indication is a result of a bad ground connection on the logic probe. The gate may be a tri-state device. 65 . For a two-input XNOR gate, with the input waveforms as shown in Figure 4-2, which output waveform is correct?

a b c d 66 . Which of the figures shown in Figure 4-3 represents the exclusive-NOR gate?

a b c d 67 . Which statement below best describes a Karnaugh map? A Karnaugh map can be used to replace Boolean rules. The Karnaugh map eliminates the need for using NAND and NOR gates. Variable complements can be eliminated by using Karnaugh maps. Karnaugh maps provide a cookbook approach to simplifying Boolean expressions. 68 . Which of the circuits in Figure 4-4 (a-d) is equivalent to Figure 4-4 (e)?

a b c d 69 . Which of the K-maps in Figure 4-5 represents the expression X = AC + BC + B?

a b c d 70 . The simplest equation which implements the K-map in Figure 4-6 is:

70 .

Which of the figures in Figure 4-7 (a-d) is equivalent to Figure 4-7 (e)?

a b c d 71 . Which of the following logic expressions represent the logic diagram shown?

72 .

What type of logic circuit is represented by the figure shown in Question 18? XOR XNOR

XAND XNAND 73 . Which of the following combinations cannot be combined into K-map groups? Corners in the same row Corners in the same column Diagonal corners Overlapping combinations 74 . Which of the circuits in Figure 4-9 (a-d) is the sum-of-products implementation of Figure 49(e)?

a b c d 75.How many two-input AND and OR gates are required to realize Y=CD+EF+G (A) 2,2. (B) 2,3. (C) 3,3. (D) none of these. Ans: A

76.Which of following are known as universal gates (A) NAND & NOR. (B) AND & OR. (C) XOR & OR. (D) None. Ans: A 77.How many AND gates are required to realize Y = CD+EF+G (A) 4 (B) 5 (C) 3 (D) 2 Ans: D 78.DeMorgans first theorem shows the equivalence of (A) OR gate and Exclusive OR gate. (B) NOR gate and Bubbled AND gate.

(C) NOR gate and NAND gate. (D) NAND gat When simplified with Boolean Algebra (x + y)(x + z) simplifies to (A) x (B) x + x(y + z) (C) x(1 + yz) (D) x + yz Ans: D 79.The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR Ans: D 80.The Boolean expression A.B+ A.B+ A.B is equivalent to (A) A + B (B) A.B (C) A + B (D) A.B

81.The simplification of the Boolean expression (ABC)+ (ABC) is (A) 0 (B) 1 (C) A (D) BC Ans: B

Objective Questions. Topic: Combinational Logic, Digital Arithmetic (Ch 4, Ch 6& Ch 9)

1.

A 3 bit binary adder should be a. 3 full adders b. 2 full adders and 1 half adder c. 1 full adder and 2 half adder d. 3 half adders 2. when two 4 bit parallel adders are cascaded we get a. 4 bit parallel adder b. 8 bit parallel adder c. 16 bit parallel adder d. none of above

2.

3. In 2s complement addition, the carry generated in the last stage is a. added to LSB b. neglected c. added to bit next to MSB d. added to the bit next to LSB 4. The number of inputs and outputs in a full adder are a. 2 and 1 b. 2 and 2 c. 3 and 3 d. 3 and 2 5.In a 7 segment display the segments a,b,c,d,f,g are lit. The decimal number displayed will be a. 9 b. 5 c. 4 d. 2 6. In a 7 segment display the segments b and c are lit up. The decimal number displayed will be a. 9 b. 7 c. 3 d. 1 7 .A device which converts BCD to seven segments is called a. encoder b. decoder c. multiplexer d. none of these

8.Which device changes parallel data to serial data a. decoder b. multiplexer c. demultiplexer d. flip flop 9.A 1 of 4 multiplexer requires data select line a. 1 b. 2 c. 3 d. 4 10. It is desired to route data from many registers to one register. The device needed is a. decoder b. multiplexer c. demultiplexer d. counter 11.Which device has one input and many outputs a. flip flop b. multiplexer c. demultiplexer d. counter 12.Two 16:1 and one 2:1 multiplexers can be connected to form a a. 16:1 multiplexer b. 32:1 multiplexer c. 64:1 multiplexer d. 8:1 multiplexer 13. Parallel adder is a. sequential circuits b. combinational circuits c. either sequential or combinational circuits d. none of above 14. A half adder can be used only for adding a. 1 bit b. 2 bits c. 4 bits d. 8 bits

15. Which statement below best describes the function of a decoder? a. A decoder will convert a decimal number into the proper binary equivalent. b. A decoder will convert a binary number into a specific output representing a particular character or digit. c. Decoders are used to prevent improper operation of digital systems. d. Decoders are special ICs that are used to make it possible for one brand of computer to

talk to another. 16 One can safely state that the output lines for a demultiplexer are under the direct control of the:

a. b. c. d.

input data select lines. the internal AND gates. the internal OR gate. Input data line.

17 Refer to the figure given below. The logic function generator being implemented with the .

multiplexer in this circuit produces a constant LOW on the output. The ABC inputs are checked and appear to be pulsing; also, the 07 and EN inputs are checked with the scope and all appear to be at 0 V. A check with the DMM confirms that power is on. What is the problem, and what should be done to correct it?

a. The output is shorted to Vcc; replace the IC. The scope's vertical input is in the AC mode and the common connection for the 0,2,3 and 5 inputs is bad. Set the scope's vertical input mode to DC, and repair the bad solder connection. c. Power has not been applied to the circuit; apply power. d. The output is shorted to ground; replace the IC. b.

18. Refer to the keyboard encoder in figure (a). Sometimes when the 5 key is pressed, the system attached to the keypad does not respond. The 5 input on the 74147 is monitored

with a digital storage scope while repeatedly pressing the 5 key, and the waveform in figure (b) is obtained; the P above the trace indicates the points at which the technician pressed the key. What is most likely wrong with the circuit?

a.

The switches on the 5 key are intermittent; the contacts need to be cleaned or the switch replaced. b. The pull-up resistor connected to the 5 key is bad and should be replaced. The common ground connection at the bottom of the 0 key has a bad solder c. connection; repair the connection. d. The 74147 is intermittent, possibly due to high temperature, and should be replaced.

19 .The BCD/DEC decoder shown in figure (a) is examined with a logic analyzer and the results are shown in the waveforms in figure (b). What, if anything, is wrong with the circuit?

a. b. c. d.

The "2" output is shorted to Vcc. The A1 input is internally open. The A1 input node is internally stuck LOW. Nothing is wrong with the circuit.

20. A 16-input multiplexer is to be used to perform parallel-to-serial data conversion. Which of the following counters would be required to provide the data select inputs? a. b. c. d. MOD 8 MOD 16 MOD 4 MOD 2

21. A breadboard-circuit design using a BCD-to-decimal decoder has a problem wherein the operation of the system is erratic. The technician uses his scope to examine the waveforms throughout the system and doesn't really see any problems. While he's scratching his head, what helpful advice can you offer him as to what might be wrong and what to do to correct the problem? a. The decoder is thermally intermittent; replace it. b. There is probably a bad connection on the wire wrap protoboard; recheck the wiring. c. Glitches are probably the culprit; strobe the decoder.

d.

The decoder is thermally intermittent and must be replaced; or there is probably a bad connection on the wire wrap protoboard, and the wiring must be rechecked.

22. Output 5 of a 74138 octal decoder is selected when it is enabled by a data input of:

a.

b.

c.

d.

23. How is the number one (1) indicated on the outputs of a 7447 BCD-to-seven-segment code converter? a. b. c. d. Segment a is active. Segment b is active. Segments a and b are active. Segments b and c are active.

24. For the input values (A0A3, B0B3, Data Select = 1) given for the circuit given below, what will be indicated on the displays?

a. b. c. d.

A = 0, B = 5 A = 5, B = 0 A = 6, B = 0 A = 0, B = 6

25. It is suspected that the comparator in the figure given below has a problem. The inputs are activated in the table shown below and the corresponding outputs noted. What is most likely wrong with the circuit? For P0 P3 = 1 and Q0 Q3 = 0, P > Q = 1, P = Q = 1, P < Q = 0 For P0 P3 = 0 and Q0 Q3 = 1, P > Q = 0, P = Q = 1, P < Q = 1 For P0 P3 = 1 and Q0 Q3 = 1, P > Q = 0, P = Q = 1, P < Q = 0

a. b. c. d.

The P0P3 inputs are defective. One or more of the Q inputs is bad. The P = Q output is shorted to Vcc. Nothing is wrong; the circuit is functioning properly.

26. Which statement best describes the given figure, and what is the function of the terminal labeled EN?

a.

Quad two-input multiplexer. EN is the enable input, which requires an active LOW for the device to work.

b. Quad two-bit multiplier, EN is the active HIGH trigger. Dual quad-input multiplexer, which requires an active LOW on the EN terminal for c. the device to work. Quad two-input AND gate, which requires an active LOW on the EN input to enable d. all the gates.

27. The data transmission system shown in below has a problem; the parity error output is always high. A logic analyzer is used to examine the system and shows that the DATA IN on the left matches the DATA OUT on right. What might be causing the problem?

a. b. c d..

The error gate could be defective. The storage circuit could be defective. The parity checker could be bad. Any of the above.

28. What is the purpose of a decoder's inputs? a. To allow the decoder to respond to the inputs to activate the correct output gate. b. To disable the decoder outputs so that all outputs will be inactive. c. To disable the inputs and activate all outputs. d To allow the decoder to respond to the inputs to activate the correct output gate, and to disable the inputs and activate all outputs.

29. Multiplexing of digital signals is usually required when: a. moving data internally within a microprocessor. b. moving data between memory and storage registers in a microprocessor. c. moving data over long distance transmission lines. moving data internally within a microprocessor or between memory and storage d. registers.

30. Referring to the figure given below, what output code will appear on the output (A3,A2,A1,A0) when the 5 key is pressed?

a. c.

1010 1101

b. d.

0101 1011

31. What type of device is shown in the given figure, and what inputs (A3,A2,A1,A0) are required to produce the output levels as shown?

a. b. c. d.

A binary-to-decimal encoder; 0,1,1,1 A decimal-to-binary decoder; 1,1,1,0 A BCD-to-decimal decoder; 0,1,1,1 A decimal-to-BCD encoder; 1,1,1,0

32. What are the outputs of a 7485 four-bit magnitude comparator when the inputs are A = 1001 and B = 1010? A < B is 1 A = B is 0 A > B is 1 A < B is 0 A = B is 1 A > B is 0 A < B is 0 A = B is 0 A > B is 1

a.

b.

c.

d.

A < B is 1 A = B is 0 A > B is 0

33. Determine the correct output for the multiplexer and its associated timing diagram given below.

a. c.

Ya Yc

b. d.

Yb Yd

34. What must be done in the given figure in order to use two 7485 4-bit comparators to compare two 8-bit numbers?

The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the same outputs of COMP B. The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the <, =, and b. > inputs of COMP B. The = input of COMP A must be connected to Vcc, and the < and > inputs must be c. connected to ground. a. d. The P < Q, P = Q, and P > Q outputs of COMP A must be connected to the <, =, and > inputs of COMP B, the = input of COMP A must be connected to Vcc, and the < and > inputs must be connected to ground.

35.The number of control lines for a 8 to 1 multiplexer is (A) 2 (B) 3 (C) 4 (D) 5 Ans: B

36.The gates required to build a half adder are (A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate (C) EX-OR gate and AND gate (D) Four NAND gates

37.The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER (C) DEMULTIPLEXER (D) FLIP-FLOP Ans: C 38.A device which converts BCD to Seven Segment is called (A) Encoder (B) Decoder (C) Multiplexer (D) Demultiplexer 39. How many select lines will a 16 to 1 multiplexer will have (A) 4 (B) 3 (C) 5 (D) 1 Ans: A

Objective questions: Topic: Sequential logic circuits

(Ch 5, Ch 7)

(Latches&Flipflops, Counters&Registers)
1. A flip flop is a a. combinational circuit b. memory element c. arithmetic element d. memory or arithmetic 2. In a D latch a. data bit D is fed to S input and D to R input b. data bit D is fed to R input and D to S input c. data bit D is fed to both R and S inputs d. data bit D is not fed to any input 3. In a D latch a. a high D sets the latch and low D resets it b. a low D sets the latch and high D resets it c. race can occur d. none of above 4.In a positive edge triggered JK flip flop a. High J and High K produce inactive state b. Low J and High K produce inactive state c. High J and Low K produce inactive state d. Low J and Low K produce inactive state 5.In a positive edge triggered D flip flop a. D input is called direct set b. Preset is called direct reset c. preset and clear are called direct set and reset respectively d. D input overrides other inputs 6. In a positive edge triggered JK flip flop J=1,K=0 and clock pulse is rising.Q will a. be 0 b. be 1 c. show no change d. toggle 7. For edge triggering in flip flops manufacturers use a. RC circuit b. direct coupled design c. either RC circuit or direct coupled design d. none of these 8. In a JK flip flop toggle means a. set Q=1 and Q=0 b. set Q=0 and Q=1 c. change the output to the opposite state d. no change in input

9. A mod 4 counter will count a. from 0 to 4 b. from 0 to 3 c. from any number n to n+4 d. none of above 10.A ring counter has N flip flops. The total number of states are a. N b. 2N c. 3N d. 4N 11.A counter has modulus of 10. The number of flip flops are a. 10 b. 5 c. 4 d. 3 12.In a ripple counter a. whenever a flip flop sets to 1,the next higher FF toggles b. whenever a flip flop sets to 0,the next higher FF remains unchanged c. whenever a flip flop sets to 1,the next higher FF faces race condition d. whenever a flip flop sets to 0,the next higher FF faces race cond 13.A counter has 4 flip flops. It divides the input frequency by a.4 b. 2 c. 8 d. 16 14. A decade counter skips a. binary states 1000 to 1111 b. binary states 0000 to 0011 c. binary states 1010 to 1111 d. binary states 1111 and higher 15.The number of flip flops needed for Mod 7 counter are a. 7 b. 5 c. 3 d. 1 16.A presettable counter with 4 flip flops start counting from a. 0000 b. 1000 c. any number from 0000 to 1111 d. any number from 0000 to 1000 17.A 4 bit down counter can count from a. 0000 to 1111 b. 1111 to 0000 c. 000 to 111 d. 111 to 000 18. A 3 bit up-down counter can count from

a. 000 to 111 b. 111 to 000 c. 000 to 111 and also from 111 to 000 d. none of above 19.IC counters are a. synchronous only b. asynchronous only c. both synchronous and asynchronous d. none of above 20. Shifting digits from left to right and vice versa is needed in a. storing numbers b. arithmetic operations c. counting d. storing and counting 21. The basic storage element in a digital system is a. flip flop b. counter c. multiplexer d. encoder 22. The simplest register is a. buffer register b. shift register c. controlled buffer register d. bidirectional register 23. The basic shift register operations are a. serial in serial out b. serial in parallel out c. parallel in serial out d. all of above 24. A universal shift register can shift a. from right to left b. from left to right c. both from right to left and left to right d. none of above 25. In a shift register, shifting a bit by one bit means a. division by 2 b. Multiplication by 2 c. subtraction by 2 d. any of above 26. An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses required is a. 1 b. 2 c. 4 d. 8

27. Which of the following is not a form of multivibrator? a. Tristable. b. Monostable c. Bistable d. Astable

28. The S-R latch shown here has active high inputs.

29. A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously? a. The Q output is reset to 0. b. The Q output is set to 1. c. The Q output toggles to the other state. d. The Q output remains unchanged.

30. What is the function of the following circuit?

a. b. c. d.

A four-bit memory register. A four-bit shift register. A four-bit ripple counter. A four-bit synchronous counter.

31. What is the frequency of the output of the following circuit?

a.

4 Hz

b. 16 Hz

C. 8 Hz

d. 1 Hz.

32. What is the function of the following circuit?

a. A modulo-6 counter b. A modulo-8 counter c. A modulo-10 counter d. A modulo-12 counter 33. On the fifth clock pulse, a 4-bit Johnson sequence is Q = 0, Q = 1, Q = 1, and Q = 1. On the 0 1 2 3 sixth clock pulse, the sequence is ________. a. b. c. d. Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0 Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0 Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1 Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1

34. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? a. c. 0000 1000 b. d. 0010 1111

35. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called? a. b. tristate end around

c. d.

universal conversion

36. On the third clock pulse, a 4-bit Johnson sequence is Q = 1, Q = 1, Q = 1, and Q = 0. On the 0 1 2 3 fourth clock pulse, the sequence is ________.

a. b. c. d. 37.

Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1 Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0 Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0 Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0

A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________.

a. c.

1101 0001

b. d.

0111 1110

38.

How can parallel data be taken out of a shift register simultaneously? a. b. c. d. Use the Q output of the first FF. Use the Q output of the last FF. Tie all of the Q outputs together. Use the Q output of each FF.

39.

What does the output enable do on the 74395A chip? a. b. c. d. It determines when data can be loaded. It forces all outputs to go HIGH. It forces all outputs to go LOW.

It activates the three-state buffer

40.

To operate correctly, starting a ring shift counter requires: a. b. c. d. clearing all the flip-flops presetting one flip-flop and clearing all others clearing one flip-flop and presetting all others presetting all the flip-flops

41.

In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? a. c. 2 12 b. d. 6 24

42.

A modulus-12 ring counter requires a minimum of ________. a. b. c. d. 10 flip-flops 12 flip-flops 6 flip-flops 2 flip-flops

43. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________. a. c. 01110 00101 b. d. 00001 00110

44.

What is meant by parallel loading the register? a. shifting the data in all flip-flops simultaneously b. loading data in two of the flip-flops c. loading data in all flip-flops at the same time d. momentarily disabling the synchronous SET and RESET inputs

45. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) a. c. 1100 0000 b. d. 0011 1111

46. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. a. c. 0000 0111 b. d. 1111 1000

47. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________. a. b. c. d. 4 s 40 s 400 s 40 ms

48. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________. a. 16 s

b. c. d.

8 s 4 s 2 s

49. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

a. b. c d.

ring shift clock Johnson binary

50. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

a. c.

10011100 00001100

b. d.

11000000 11110000

51. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse? a. c. 11101011 11110000 b. d. 00010111 00000000

52. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

a. b. c. d. 53.

right, one right, two left, one left, three

How many clock pulses will be required to completely load serially a 5-bit shift register? a. c. 2 4 b. d. 3

5 54.

What is the difference between a ring shift counter and a Johnson shift counter? a. b. c. d. There is no difference. A ring is faster. The feedback is reversed. The Johnson is faster.

55.

A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. a. c. 1110 1000 b. d. 0111 1001

56. In a parallel in/parallel out shift register, D = 1, D = 1, D = 1, and D = 0. After three clock 0 1 2 3 pulses, the data outputs are ________.

a. c.

1110 1100

b. d.

0001 1000

57. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time? a. b. c. d. 58. parallel-in, parallel-out parallel-in, serial-out serial-in, parallel-out serial-in, serial-out

When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________. a. b. c. 40 kHz 50 kHz 400 kHz

d. 59.

500 kHz

Ring shift and Johnson counters are:

a. b. c. d. 60.

synchronous counters aynchronous counters true binary counters synchronous and true binary counters

In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns? a. c. 1 4 b d. 2 8

61. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

a. c. 62.

1101000000 1100000000

b. d.

0011010000 0000000000

How many flip-flops are required to make a MOD-32 binary counter? a. c. 3 5 b. d. 45 6

63. Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000? a. c. 50,000 25,536 b. d. 65,536 15,536

64. A MOD-16 ripple counter is holding the count 1001 . What will the count be after 31 clock 2 pulses?

a. c. 65.

10002 10112

b. d.

10102 11012

The terminal count of a modulus-11 binary counter is ________.

a. c.

1010 1001

b. d.

1000 1100

66.

List which pins need to be connected together on a 7493 to make a MOD-12 counter. a. b. c. d. 12 to 1, 11 to 3, 9 to 2 12 to 1, 11 to 3, 12 to 2 12 to 1, 11 to 3, 8 to 2 12 to 1, 11 to 3, 1 to 2

67.

Synchronous construction reduces the delay time of a counter to the delay of: a. b. c. d. all flip-flops and gates all flip-flops and gates after a 3 count a single gate a single flip-flop and a gate

68. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the: a. input clock pulses are applied only to the first and last stages b. input clock pulses are applied only to the last stage c. input clock pulses are not used to activate any of the counter stages d. input clock pulses are applied simultaneously to each stage

69.

What is the difference between a 7490 and a 7492? a. b. c. d. 7490 is a MOD-12, 7492 is a MOD-10 7490 is a MOD-12, 7492 is a MOD-16 7490 is a MOD-16, 7492 is a MOD-10 7490 is a MOD-10, 7492 is a MOD-12

70. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.

a. c.

product log

b. d.

sum reciprocal

71. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

a. b. c. d.

500 kHz 1,500 kHz 6 MHz 5 MHz

72.

What decimal value is required to produce an output at "X" ?

a. b. c. d.

1 1 or 4 2 5

73.

A BCD counter is a ________. a. b. c. d. binary counter full-modulus counter decade counter divide-by-10 counter

74.

How many flip-flops are required to construct a decade counter? a. c. 10 5 b d. 8 4

75.

A seven-segment, common-anode LED display is designed for: a. b. c. d. all cathodes to be wired together one common LED a HIGH to turn off each segment disorientation of segment modules

76.

To operate correctly, starting a ring counter requires: a. b. c. clearing one flip-flop and presetting all the others. clearing all the flip-flops.

presetting one flip-flop and clearing all the others. d. presetting all the flip-flops.

77. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.

a.

When MR1 and MR2 are both HIGH, all Qs will be reset to zero. b. When MR1 and MR2 are both HIGH, all Qs will be reset to one.

c. MR1 and MR2 are provided to synchronously reset all four flip-flops. d. To enable the count mode, MR1 and MR2 must be held LOW. 78.

Which of the following is an invalid output state for an 8421 BCD counter?

a. c.

1110 0010

b. d.

0000 0001

79.

How many different states does a 3-bit asynchronous counter have? a. c. 2 8 b. d. 4 16

80. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________. a. b. c. d. 12 ms 24 ns 48 ns 60 ns

81.

Three cascaded modulus-5 counters have an overall modulus of ________. a. c. 5 125 b. d. 25 500

82. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required? a. c. None Two b. d. One Fifteen

83.

The final output of a modulus-8 counter occurs one time for every ________.

a. b. c. d.

8 clock pulses 16 clock pulses 24 clock pulses 32 clock pulses

84. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

a. c.

1101 1111

b. d.

1011 0000

85. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________. a. b. c. d. 15 ns 30 ns 45 ns 60 ns

86.

Three cascaded decade counters will divide the input frequency by ________. a. c. 10 100 b d. 20 1,000

87.

A counter with a modulus of 16 acts as a ________. a. b. c. d. divide-by-8 counter divide-by-16 counter divide-by-32 counter divide-by-64 counter

88.

What is the difference between a 7490 and a 7493?

a. b. c. d. 89.

7490 is a MOD-10, 7493 is a MOD-16 7490 is a MOD-16, 7493 is a MOD-10 7490 is a MOD-12, 7493 is a MOD-16 7490 is a MOD-10, 7493 is a MOD-12

A ripple counter's speed is limited by the propagation delay of:

a. b. c. d. 90.

each flip-flop all flip-flops and gates the flip-flops only with gates only circuit gates

A 4-bit counter has a maximum modulus of ________. a. c. 3 8 b. d. 6 16

91.

How many natural states will there be in a 4-bit ripple counter? a. c. 4 16 b. d. 8 32

92. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter? a. b. c. d. Five flip-flops, three AND gates Seven flip-flops, five AND gates Four flip-flops, ten AND gates Six flip-flops, four AND gates

93. The circuit given below fails to produce data output. The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the

problem?

a. The data output line may be grounded. b. One of the clock input lines may be open. c. One of the interconnect lines between two stages may have a solder bridge to ground. d. One of the flip-flops may have a solder bridge between its input and Vcc. 94. A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter? a. Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz b. Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz c. Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz d. Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz 95.

The designation the ________.

means that

a.

up count is active-HIGH, the down count is active-LOW up count is active-LOW, the down b. count is active-HIGH up and down counts are both activec. LOW up and down counts are both actived. HIGH 96. Why can a synchronous counter operate at a higher frequency than a ripple counter? a. The flip-flops change one after the other. b.

The flip-flops change at the same time. A synchronous counter cannot operate at c. higher frequencies. d. A ripple counter is faster. 97.A ring counter consisting of five Flip-Flops will have (A) 5 states (B) 10 states (C) 32 states (D) Infinite states 98.If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz. Ans: D 99.In a JK Flip-Flop, toggle means (A) Set Q = 1 and Q = 0. (B) Set Q = 0 and Q = 1. (C) Change the output to the opposite state. (D) No change in output. 100. How many flip flops are required to construct a decade counter (A) 10 (B) 3 (C) 4 (D) 2 Ans: C 101.For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change. Ans: B 102. The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance