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74ABT16244 16-Bit Buffer Line Driver with TRI-STATE Outputs

September 1995

74ABT16244 16-Bit Buffer Line Driver with TRI-STATE Outputs


General Description
The ABT16244 contains sixteen non-inverting buffers with TRI-STATE outputs designed to be employed as a memory and address driver clock driver or bus oriented transmitter receiver The device is nibble controlled Individual TRISTATE control inputs can be shorted together for 8-bit or 16-bit operation
Y Y Y

Y Y

Features
Y Y Y

Separate control logic for each nibble 16-bit version of the ABT244 Outputs sink capability of 64 mA source capability of 32 mA

Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50 pF and 250 pF loads Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability

Commercial 74ABT16244CSSC (Note 1) 74ABT16244CMTD (Notes 1 2)

Package Number MS48A MTD48

Package Description 48-Lead (0 300 Wide) Molded Shrink Small Outline JEDEC (SSOP) 48-Lead Molded Thin Shrink Small Outline JEDEC (TSSOP)

Note 1 Devices also available in 13 reel Use suffix e SSCX and MTDX Note 2 Contact factory for package availability

Logic Symbol

Connection Diagram
Pin Assignment for SSOP

TL F 10985 1

Pin Description
Pin Names OEn I0 I15 O0 O15 Description Output Enable Inputs (Active Low) Inputs Outputs

TL F 10985 2
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

TL F 10985

RRD-B30M115 Printed in U S A

Functional Description
The ABT16244 contains sixteen non-inverting buffers with TRI-STATE outputs The device is nibble (4 bits) controlled with each nibble functioning identically but independent of the other The control pins can be shorted together to obtain full 16-bit operation

Truth Tables
Inputs OE1 L L H I0 I3 L H X Outputs O0 O3 L H Z OE2 L L H Inputs I4 I7 L H X Outputs O4 O7 L H Z

Inputs OE3 L L H
H e High Voltage Level L e Low Voltage Level X e Immaterial Z e High Impedance

Outputs I8 I11 L H X O8 O11 L H Z OE4 L L H

Inputs I12 I15 L H X

Outputs O12 O15 L H Z

Logic Diagram

TL F 10985 3

Absolute Maximum Ratings (Note 1)


Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max)
b 65 C to a 150 C b 55 C to a 125 C b 55 C to a 150 C b 0 5V to a 7 0V b 0 5V to a 7 0V b 30 mA to a 5 0 mA

DC Latchup Source Current Over Voltage Latchup (I O)

b 500 mA

10V

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs

Recommended Operating Conditions


Free Air Ambient Temperature Commercial Supply Voltage Commercial Minimum Input Edge Rate Data Input Enable Input
b 40 C to a 85 C a 4 5V to a 5 5V

b 0 5V to 5 5V b 0 5V to VCC

twice the rated IOL (mA)

(DV Dt) 50 mV ns 20 mV ns

DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE No Load 01
b 100

ABT16244 Min 20 08
b1 2

Typ

Max

Units V V V V V

VCC

Conditions Recognized HIGH Signal

Min Min Min Min Max Max Max 00

Recognized LOW Signal IIN e b18 mA IOH e b3 mA IOH e b32 mA IOL e 64 mA VIN e 2 7V (Note 1) VIN e VCC VIN e 7 0V VIN e 0 5V (Note 1) VIN e 0 0V IID e 1 9 mA All Other Pins Grounded

74ABT 74ABT 74ABT

25 20 0 55 5 5 7
b5 b5

V mA mA mA V

4 75 50
b 50 b 275

mA mA mA mA mA mA mA mA mA mA mA mA MHz

0 b 5 5V VOUT e 2 7V OEn e 2 0V 0 b 5 5V VOUT e 0 5V OEn e 2 0V Max Max 00 Max Max Max VOUT e 0 0V VOUT e VCC VOUT e 5 5V All Other Pins GND All Outputs HIGH All Outputs LOW OEn e VCC All Others at VCC or GND VI e VCC b 2 1V Enable Input VI e VCC b 2 1V Data Input VI e VCC b 2 1V All Others at VCC or GND Outputs Open OEn e GND One Bit Toggling 50% Duty Cycle

50 100 100 60 100 25 25 50

Max

ICCD

Dynamic ICC (Note 1)

Max

Note 1 Guaranteed but not tested

DC Electrical Characteristics (Continued)


Symbol Parameter Min VOLP VOLV VOHV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Output Voltage Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage
b1 3

ABT16244 Typ 04
b1 0

Units Max 07 V V V V 08 V

VCC

Conditions CL e 50 pF RL e 500X TA e 25 C (Note 1) TA e 25 C (Note 1) TA e 25 C (Note 3) TA e 25 C (Note 2) TA e 25 C (Note 2)

50 50 50 50 50

27 20

30 14 12

Note 1 Max number of outputs defined as (n) n-1 data inputs are driven 0V to 3V One output at LOW Guaranteed but not tested Note 2 Max number of data inputs (n) switching n-1 inputs switching 0V to 3V Input-under-test switching 3V to threshold (VILD) 0V to threshold (VIHD) Guaranteed but not tested Note 3 Max number of outputs defined as (n) n b 1 data inputs are driven 0V to 3V One output HIGH Guaranteed but not tested

AC Electrical Characteristics
74ABT TA e a 25 C VCC e a 5V CL e 50 pF Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 10 10 15 15 10 10 Typ 23 27 35 35 42 32 Max 39 39 63 63 67 67 74ABT TA e b40 C to a 85 C VCC e 4 5V 5 5V CL e 50 pF Min 10 10 15 15 10 10 Max 39 39 63 63 67 67 ns

Symbol

Parameter

Units

ns ns

Extended AC Electrical Characteristics


74ABT
b 40 C to a 85 C VCC e 4 5V5 5V CL e 50 pF

74ABT TA e b40 C to a 85 C VCC e 4 5V 5 5V CL e 250 pF 1 Output Switching (Note 5) Min Max

74ABT TA e b40 C to a 85 C VCC e 4 5V 5 5V CL e 250 pF 16 Outputs Switching (Note 6) Min Max MHz

Symbol

Parameter

Units

16 Outputs Switching (Note 4) Min ftoggle tPLH tPHL tPZH tPZL tPHZ tPLZ Max Toggle Frequency Propagation Delay Data to Outputs Output Enable Time Output Disable Time 15 15 15 15 10 10 Typ 100 50 53 65 65 67 67 Max

15 15 25 25 (Note 7)

60 60 78 78

25 25 25 25 (Note 7)

80 80 95 85

ns ns ns

Note 4 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all low-to-high high-to-low etc ) Note 5 This specification is guaranteed but not tested The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load This specification pertains to single output switching only Note 6 This specification is guaranteed but not tested The limits represent propagation delays for all paths described switching in phase (i e all low-to-high high-to-low etc ) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 7 The TRI-STATE delay times are dominated by the RC network (500X 250 pF) on the output and have been excluded from the datasheet

Skew
74ABT TA e b40 C to a 85 C VCC e 4 5V 5 5V CL e 50 pF 16 Outputs Switching (Note 3) Max tOSHL (Note 1) tOSLH (Note 1) tPS (Note 5) tOST (Note 1) tPV (Note 2) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LHHL Skew Pin to Pin Skew LH HL Transitions Device to Device Skew LH HL Transitions 10 10 15 17 20 74ABT TA e b40 C to a 85 C VCC e 4 5V 5 5V CL e 250 pF 16 Outputs Switching (Note 4) Max 15 15 15 20 25 ns ns ns ns ns

Symbol

Parameter

Units

Note 1 Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device The specification applies to any outputs switching HIGH to LOW (tOSHL) LOW to HIGH (tOSLH) or any combination switching LOW to HIGH and or HIGH to LOW (tOST) The specification is guaranteed but not tested Note 2 Propagation delay variation for a given set of conditions (i e temperature and VCC) from device to device This specification is guaranteed but not tested Note 3 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all low-to-high high-to-low etc ) Note 4 These specifications guaranteed but not tested The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 5 This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin It is measured across all the outputs (drivers) on the same chip the worst (largest delta) number is the guaranteed specification This specification is guaranteed but not tested

Capacitance
Symbol CIN COUT (Note 1) Parameter Input Capacitance Output Capacitance Typ 50 90 Units pF pF Conditions TA e 25 C VCC e 5 0V VCC e 5 0V

Note 1 COUT is measured at frequency f e 1 MHz per MIL STD-883B Method 3012

tPLH vs Temperature (TA) CL e 50 pF 1 Output Switching

tPHL vs Temperature (TA) CL e 50 pF 1 Output Switching

TL F 1098512

TL F 10985 13

tPLH vs Load Capacitance 1 Output Switching TA e 25 C

tPHL vs Load Capacitance 1 Output Switching TA e 25 C

TL F 1098514

TL F 10985 15

tPLH vs Load Capacitance 16 Outputs Switching TA e 25 C

tPHL vs Load Capacitance 16 Outputs Switching TA e 25 C

TL F 1098516

TL F 10985 17

Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables

tPZL vs Temperature (TA) CL e 50 pF 1 Output Switching

tPLZ vs Temperature (TA) CL e 50 pF 1 Output Switching

TL F 10985 19

TL F 10985 18

tPZH vs Temperature (TA) CL e 50 pF 1 Output Switching

tPHZ vs Temperature (TA) CL e 50 pF 1 Output Switching

TL F 10985 20

TL F 10985 21

tPZH vs Temperature (TA) CL e 50 pF 16 Outputs Switching

tPHZ vs Temperature (TA) CL e 50 pF 16 Outputs Switching

TL F 10985 22

TL F 10985 23

Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables

tPZL vs Temperature (TA) CL e 50 pF 16 Outputs Switching

tPLZ vs Temperature (TA) CL e 50 pF 16 Outputs Switching

TL F 1098524

TL F 10985 25

tPZL vs Load Capacitance 16 Outputs Switching TA e 25 C

tPZH vs Load Capacitance 16 Outputs Switching TA e 25 C

TL F 1098526

TL F 10985 27

tPLH and tPHL vs Number Output Switching VCC e 5 0V TA e 25 C CL e 50 pF

TL F 10985 28

ICC vs Frequency Average TA e 25 C VCC e 5 5V

TL F 10985 29

Dashed lines represent design characteristics for specified guarantees refer to AC Characteristics Tables

AC Loading

TL F 10985 4

Includes jig and probe capacitance

TL F 10985 6

FIGURE 1 Standard AC Test Load

FIGURE 2a Test Input Pulse Requirements Amplitude 3 0V Rep Rate 1 MHz tW 500 ns tr 2 5 ns tf 2 5 ns

FIGURE 2b Test Input Signal Requirements

TL F 10985 8

TL F 10985 7

FIGURE 3 Propagation Delay Waveforms for Inverting and Non-Inverting Functions

FIGURE 5 TRI-STATE Output HIGH and LOW Enable and Disable Times

TL F 10985 5

TL F 10985 9

FIGURE 4 Propagation Delay Pulse Width Waveforms

FIGURE 6 Setup Time Hold Time and Recovery Time Waveforms

Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows

TL F 10985 30

10

Physical Dimensions inches (millimeters)

48-Lead SSOP (0 300 Wide) (SS) NS Package Number MS48A

11

74ABT16244 16-Bit Buffer Line Driver with TRI-STATE Outputs

Physical Dimensions millimeters (Continued)

48-Lead Molded Thin Shrink Small Outline Package JEDEC NS Package Number MTD48

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