Register-reference Instructions

All take 1 clock cycle during execute

Skip means increment the PC
Complement can be calculated by subtracting each digit from the highest digit
in the base. (base 2 just toggle, base 16 subtract from FFFF)
CIL, CIR are logical shifts left or right with the extended accumulator (E)
substituted for the 0 that would normally pad a logical shift.

SZE - skip if zero in the extended accumulator (E)

SZA - skip if zero in the accumulator (AC)
CMA - complement the accumulator (AC)
SNA - skip if negative in the accumulator (AC)
SPA - skip if positive in the accumulator (AC)
INC - increment the accumulator (AC)
CIL - circulate the accumulator left, E goes in the low order bit and the high order bit
bumped out goes in E
CME - complement the extended accumulator (E)
CIR - circulate the accumulator right, E goes in the high order bit and the low order
bit bumped out goes in E
CLE - clear the extended accumulator (E), place a zero in E
CLA - clear the accumulator (AC), place zeros in the AC
HLT - halt, set S to zero
Program to Exercise Most of the Register-reference Instructions
Complete the table found on the following link: Register Instruction Exercise Table
200 PC start This Program Exercises
Register Instructions
17 Number of words to follow
200 7002 SZE
201 7001 HLT
202 7004 SZA
203 7001 HLT
204 7200 CMA
205 7008 SNA
206 7001 HLT
207 7010 SPA

208 1300 ADD_data_1

209 7020 INC
20A 7040 CIL
20B 7020 INC
20C 7100 CME
20D 7080 CIR
20E 7400 CLE
20F 7001 HLT
300 7899 Data_1
Program Output

A Bit More On Memory-reference Instructions:

The memory-reference ADD instruction always places the carry-out into the extended
accumulator (E) be it 0 or 1.
ISZ
The only memory-reference instruction not discussed in either Subroutine to Subtract
or Register Instruction Exercise is
ISZ - increment DR (loaded with M[AR]) and skip (increment PC) if DR is zero
ISZ takes 3 clock
cycles to execute:

6xxx, Exxx

D6T4:
D6T5:
D6T6:

ISZ can be useful in a subroutine: Program Output

200 PC start This Program Multiplies 3 by 6
11 Number of words to follow
04F 0000 Return_Address
050 1105 ADD
051 6106 ISZ
052 4050 BUN
053 C04F BUN
105 0003 DATA
106 FFFB DATA
200 2105 LDA
201 504F BSA
202 3107 STA
204 7001 HLT

PROGRAM OUTPUT
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 0
Recently modified memory cells
Cell
Contents
200
7002
SZE
201
7001
HLT
202
7004
SZA
203
7001
HLT
204
7200
CMA
205
7008
SNA
206
7001
HLT
207
7010
SPA
208
1300
ADD_data_1
209
7020
INC
20a
7040
CIL
20b
7020
INC

DR M[AR]
DR DR+1
M[AR] DR, if( DR=0 ) then( PC PC+1 ),

20c
7100
CME
20d
7080
CIR
20e
7400
CLE
20f
7001
HLT
300
7899
Data_1
Flags
S=1 I=0 D=0 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 000
0000 0000 0000 0
PC => 200
0010 0000 0000 512
IR =>0000
0000 0000 0000 0000 0
DR =>0000
0000 0000 0000 0000 0
AC =>0000
0000 0000 0000 0000 0
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
null instruction
null
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 4
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 002
0000 0000 0010 2
PC => 202
0010 0000 0010 514
IR =>7002
0111 0000 0000 0010 28674
DR =>0000
0000 0000 0000 0000 0
AC =>0000
0000 0000 0000 0000 0
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
SZE instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 8
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 004
0000 0000 0100 4
PC => 204
0010 0000 0100 516
IR =>7004
0111 0000 0000 0100 28676
DR =>0000
0000 0000 0000 0000 0
AC =>0000
0000 0000 0000 0000 0
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
SZA instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 12
Recently modified memory cells
Cell
Contents

null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 200
0010 0000 0000 512
PC => 205
0010 0000 0101 517
IR =>7200
0111 0010 0000 0000 29184
DR =>0000
0000 0000 0000 0000 0
AC =>FFFF
1111 1111 1111 1111 -1
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
CMA instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 16
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 008
0000 0000 1000 8
PC => 207
0010 0000 0111 519
IR =>7008
0111 0000 0000 1000 28680
DR =>0000
0000 0000 0000 0000 0
AC =>FFFF
1111 1111 1111 1111 -1
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
SNA instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 20
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=0 FGO=0
AR => 010
0000 0001 0000 16
PC => 208
0010 0000 1000 520
IR =>7010
0111 0000 0001 0000 28688
DR =>0000
0000 0000 0000 0000 0
AC =>FFFF
1111 1111 1111 1111 -1
TR =>0000
0000 0000 0000 0000 0
INPR => 00
0000 0000
0
OUTR => 00
0000 0000
0
SPA instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 25
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=1 E=1 R=0 IEN=0 FGI=1 FGO=0
AR => 300
0011 0000 0000 768

PC => 209
0010 0000
IR =>1300
0001 0011 0000
DR =>7899
0111 1000 1001
AC =>7898
0111 1000 1001
TR =>0000
0000 0000 0000
INPR => A3
1010 0011
OUTR => 00
0000 0000
ADD instruction
memory referencing--direct

1001
0000
1001
1000
0000

521
4864
30873
30872
0
163
0

addressing mode

****.- ..-. ....- ...- -...******

Mano CPU state at time
Clock cycle = 29
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=1 R=0 IEN=0 FGI=1 FGO=0
AR => 020
0000 0010 0000 32
PC => 20A
0010 0000 1010 522
IR =>7020
0111 0000 0010 0000 28704
DR =>7899
0111 1000 1001 1001 30873
AC =>7899
0111 1000 1001 1001 30873
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
INC instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 33
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0
AR => 040
0000 0100 0000 64
PC => 20B
0010 0000 1011 523
IR =>7040
0111 0000 0100 0000 28736
DR =>7899
0111 1000 1001 1001 30873
AC =>F133
1111 0001 0011 0011 -3789
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
CIL instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 37
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0
AR => 020
0000 0010 0000 32
PC => 20C
0010 0000 1100 524
IR =>7020
0111 0000 0010 0000 28704
DR =>7899
0111 1000 1001 1001 30873
AC =>F134
1111 0001 0011 0100 -3788

TR =>0000
0000 0000 0000 0000
INPR => A3
1010 0011
OUTR => 00
0000 0000
INC instruction
register type

0
163
0

****.- ..-. ....- ...- -...******

Mano CPU state at time
Clock cycle = 41
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=1 R=0 IEN=0 FGI=1 FGO=0
AR => 100
0001 0000 0000 256
PC => 20D
0010 0000 1101 525
IR =>7100
0111 0001 0000 0000 28928
DR =>7899
0111 1000 1001 1001 30873
AC =>F134
1111 0001 0011 0100 -3788
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
CME instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 45
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0
AR => 080
0000 1000 0000 128
PC => 20E
0010 0000 1110 526
IR =>7080
0111 0000 1000 0000 28800
DR =>7899
0111 1000 1001 1001 30873
AC =>F89A
1111 1000 1001 1010 -1894
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
CIR instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 49
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=1 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0
AR => 400
0100 0000 0000 1024
PC => 20F
0010 0000 1111 527
IR =>7400
0111 0100 0000 0000 29696
DR =>7899
0111 1000 1001 1001 30873
AC =>F89A
1111 1000 1001 1010 -1894
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
CLE instruction

register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 53
Recently modified memory cells
Cell
Contents
null
none modified
Flags
S=0 I=0 D=7 E=0 R=0 IEN=0 FGI=1 FGO=0
AR => 001
0000 0000 0001 1
PC => 210
0010 0001 0000 528
IR =>7001
0111 0000 0000 0001 28673
DR =>7899
0111 1000 1001 1001 30873
AC =>F89A
1111 1000 1001 1010 -1894
TR =>0000
0000 0000 0000 0000 0
INPR => A3
1010 0011
163
OUTR => 00
0000 0000
0
HLT instruction
register type
****.- ..-. ....- ...- -...******
Mano CPU state at time
Clock cycle = 53
Memory dump follows:
Cell
Contents
200
7002
SZE
202
7004
SZA
204
7200
CMA
205
7008
SNA
207
7010
SPA
208
1300
ADD_data_1
209
7020
INC
20a
7040
CIL
20b
7020
INC
20c
7100
CME
20d
7080
CIR
20e
7400
CLE
300
7899
Data_1