Sequential Logic

IT06IU -- Digital Logic Design
Chapter 4 Sequential Logic Design
Overview
Introduction Latches and Flipflops Analysis of Clocked Sequential Circuits Design Procedures of Clocked Sequential Circuits Design of Counter
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Sequential Systems
A combinational system is a system whose outputs depend only upon its current inputs. A sequential system is a system whose outputs depends on the current inputs and the systems current state.
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FlipFlip-Flops/ Latches
Latches and Flip-Flops are devices that can have two internal states (0,1) The output of a latch or a Flip-Flop (FF) is dependent upon its CURRENT STATE and CURRENT INPUTS. Latches and FFs are the simplest examples of sequential systems.
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Synchronous Sequential Logic
Latch
Bistable memory element A bistable multivibrator Can store one bit of data. Types of latch According to modes of operation.

Asynchronous latches Synchronous latches

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Asynchronous latches :
Operate independently of any type of clock or timing. Data will be stored as soon as the input attain a valid voltage level.
Input
Q Q
True Output Complement Output D Q Q 0 1 0 1 1 0
D Q Q
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Synchronous latches :
Has some additional control circuit and enable input. Level triggered, or level sensitive.
Input Clock D EN Q Q True Output Complement Output
D EN 0 1 0 1 1 1 0 0
Q 0 1 NC NC
Q 1 0 NC NC
D EN Q Q
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NC : No Change
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SR Latch :
Set-Reset flip-flop. Cross-coupled NOR gates. Direct-coupled RS flip-flop NOR gate latch.

R (Reset)
Q Q Q Q S (Set) R (Reset)
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(Set) S
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R (Reset) Q
S R
Q Q
(Set) S
S R 0 0 1 1
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Q Q
Operation
0 1 0 1
Q0 Q0 Hold (no change) 0 1 Reset 1 0 Set Unstable Unstable

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Feedback : Output is fed back to the input. Cross-coupled feedback : Output of one of the NOR gate is fed back to the other NOR gate.
000 Q x1 1 Q 00 0 Q Q x11 0 S (Set) 1 R (Reset)
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1 R (Reset)
(Set) S 0
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0 R (Reset) x11 Q 0 R (Reset) 111 Q
(Set) S 1 0 R (Reset)
Q 000
(Set) S 0 1p0
Q 000
000 Q
R (Reset)
01010 Q
(Set) S 0
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Q 111
(Set) S 1p0
Q 01010
Race condition
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Synchronous sequential Logic

The actual circuit does not oscillate between 00 to 11 indefinitely, but rather ends up sometimes in state 10 and sometimes in state 01.
011 Q 1p1 R (Reset) 000 Q
1p0 R (Reset)
(Set) S 1p1
Q 000
(Set) S 1p0
Q 011
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Set state ( 1 state ) Q = 1, Q = 0. Clear state ( 0 state ) Q = 0, Q = 1. Example:

0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1
S R
Q Q0=0
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SR Latch : NAND gate latch

S (Set) Q S R R (Reset) Q Q Q
S R 1 1 0 0
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Q Q
Operation
1 0 1 0
Q0 Q0 Hold (no change) 0 1 Reset 1 0 Set Unstable Unstable

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Synchronous Gated SR Latch ( RS flip-flop ) Sequential Logic

Logic diagram (1)

S
CP
0 01 1 01 11 1 0 10 1
11 10 0
Q
R

11 01 0
S x 0 0 1 1 R Q x Q0 0 Q0 1 0 0 1 1 ? Q Q0 Q0 1 0 ? Operation Hold (Disable) Hold Reset Set Unstable
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Function table
CP 0 1 1 1 1
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Logic diagram (2)

R Q
CP Q S

Characteristic table
Q ( t ) , Q present state : the state before the application of a clock pulse ( to CP ). Q ( t +1 ) next state : the state after the application of a clock pulse ( to CP ).
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Q S R 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q ( t+1 ) 0 0 1 Indeterminate 1 0 1 Indeterminate
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Characteristic Equation
SR Q 00 0 0 1 1 01 0 0 11 10 x x 1 1 S RQ
Q ( t +1 ) = S + RQ
S and R cannot equal to 1 simultaneously @ SR = 0 must be include as a part of the characteristic equation.
Q ( t +1 ) = S + RQ SR = 0
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Graphic symbol
S CP R Q
CP 0 1 1 1 1
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S x 0 0 1 1
R Q x Q0 0 Q0 1 0 0 1 1 ?
Q Q0 Q0 1 0 ?
Operation Hold (Disable) Hold Reset Set Unstable

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Gated D Latch ( D flip-flop )

Logic diagram
Q
CP Q
D CP
S CP R
Q Q
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Q D 0 0 1 1 0 1 0 1

Characteristic equation
D Q 0 0 0 1 0 1 1 1 D
Q ( t+1 ) 0 1 0 1
Q ( t+1 ) = D
Graphic Symbol
D CP Q Q
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TTL Latch IC
Latch Type Gated D latch Gated D latch SR latch Gated D latch Gated D latch
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TTL No. 7475 74116 74279
DIP
Description
16-pin 4-bit latch, true and complement outputs 24-pin Dual 4-bit latch, true outputs with clear input 16-pin Quad SR latch
74LS373 20-pin Octal 3-state outputs Active low enable 74LS375 16-pin 4-bit latch, true and complement outputs
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CMOS Latch IC
Latch Type Gated D latch Gated D latch Gated D latch Gated D latch TTL No. DIP Description
74HC75 16-pin 4-bit latch, true and 74HCT75 complement outputs 74HC77 14-pin 4-bit latch, true outputs 74HCT77 74HC373 20-pin Octal 3-state outputs 74HCT373 Active low enable 74HC573 20-pin 8-bit latch, complement 74HCT573 outputs with 3-state
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Latch IC Parameters : D
tSU
CP Q

Setup time tSU : The amount of time that the inputs must be stable before the device is enable
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D
tSU tH
CP Q

Hold time tH : The amount of time that the inputs must be stable after the device has completed its operation.
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D
tSU tH tW tPLH
CP Q

Pulse width (Enable) tW : The amount of time that the enabling pulse must be active for the device to be properly enabled. Propagation delay time, Low-to-high tPLH .
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TTL Latch IC 74116

4 6 8 10 1 2 3 1D1 1D2 1D3 1D4 5 1Q1 7 1Q2 9 1Q3 11 1Q4 16 18 20 22 13 14 14 2D1 2D2 2D3 2D4

17 2Q1 19 2Q2 21 2Q3 23 2Q4
1CLR 1C1 1C2 74116-1 Inputs CLR C1 C2 D 1 1 1 1 0 0 0 x 1 x 0 0 1 x x 0 1 x x x
2CLR 2C1 2C2 74116-2
Outputs Q 0 1 Q0 Q0 0
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TTL Latch IC 7475

7475
1D 2D 1C, 2C 3D 4D 3C, 4C 1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q
2 3 13 6 7 4
16 1 15 14 10 11 9 8
Inputs D 0 1 x C 1 1 0
Outputs Q Q 0 1 1 0 Q0 Q0
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Application Switch Debounce Circuit :

Voltage bounce Due to the physical vibration of the contacts of the mechanical switch upon closure.
Vcc
Output waveform Ideal

Output
Actual
bounce
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Debounce Circuit
Vcc
Vcc
R Debounced output
R S R R Q Q
Debounced output
R Vcc Vcc
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JK Flip-Flop (FF) :
A refinement of RS FF. Logic Diagram : J is for set, K is for reset.

R J CP K S
R Q
Q S
The internal R and S are never simultaneously 1.

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Q ( t+1 ) 0 0 1 1 1 0 1 0 J K Q 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q ( t+1 ) 0 1 0 0 1 1 1 0
Hold Reset Set Toggle
Q J K 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
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Characteristic Equation
JK Q 00 0 0 1 1 01 0 0 11 10 1 0 1 1 JQ KQ
Q ( t +1 ) = JQ + KQ
Note: CP=1, J=K=1 Q(t+1) = Q Toggle Oscillation. How to avoid oscillation : The clock pulse duration must be shorter than the propagation delay time of the FF.
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T Flip-Flop :
Tie the inputs of JK type together. T Toggle, change state. Logic diagram

T CP
R Q
Q S
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Characteristic table and characteristic equation

Q T Q ( t+1 ) 0 0 1 1 0 1 0 1 0 1 1 0
Q T 0 0 0 1 1 1 1 0
Q ( t+1 ) = TQ + TQ
Note : CP = 1, T = 1 Oscillation
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Flip-Flop Operation
Flip-Flop :
Bistable storage device Differ from latch in method triggering

Flip-Flop triggering :

FF changes its output state base on :

Data inputs Transition of the clock input : edge-triggered device.

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The timing input Clock (CLK)

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Definition of clock-pulse transition :

Positive pulse Negative pulse
Positive- Negativeedge edge
Negative- Positiveedge edge
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Types of triggering :

Level triggered. Edge-triggered :

Positive ( Leading ) edge-triggered Respond to the inputs when the clock make a transition from LOW to HIGH. Negative ( Trailing ) edge-triggered Respond to the inputs when the clock make a transition from HIGH to LOW.
Pulse-triggered :
Respond to the inputs when the clock make a transition from LOW to HIGH, than back to LOW.
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1 J K 1 CLK Q 1 1 J K CLK Q 1 1 J K CLK Q
clock Q (leading) Q (trailing) Q (pulse)

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MasterMaster-Slave Flip-flop Design FlipMethodology

Input Clock X Master Latch CLK Y Slave Latch CLK Z Output
When Clock is LOW, the Master Latch is Disabled & Slave Latch is Enabled. Hence, the path from the input to the output is broken. Great! When the Clock is High, if the value of X changes, only the value of Y changes. Value of Z will not be affected. State (value) of the flip-flop is the state (value) of the slave latch.
Master-slave FF :

RS Master-slave FF
Logic diagram :
Y S C Q C Y R Q R Q Q S Q Q
Master
Slave
CP
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Timing relationship :
S 1 C Y S Q C Y 0 R Q R S

Q Q
Master
Slave
Q Q
CP
CP S Y Q Pulse-triggered device.
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Master-slave JK FF
Logic diagram : Master Slave
5
J K
Q Q
Clock
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J 1
S Q
Master K 2
R Q
Slave 4
R Q
Clock
Clock J K Y Q
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Edge-triggered Flip-flop :

D-type positive-edge -triggered FF :

1 S 5 Q
2 Clock 3
6 R
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NAND gate latches : NAND 1 and 2. NAND 3 and 4. NAND 5 and 6. S = 0, R = 1 Q ( t+1 ) = 1 S = 1, R = 0 Q ( t+1 ) = 0 S = 1, R = 1 Q ( t+1 ) = Q ( t )
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Synchronous Sequential Logic Operation of D-type edge-triggered FF : 1. Clock = 0 1). D = 0

1 0 S 1 Q(t+1) = Q(t) Clock 3 1 R 1 1 Clock 3 0
2). D = 1
1 1 S 1 Q(t+1) = Q(t) 1 R 0
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2 0
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2. Clock = 0 p 1 1). D = 0
D Clock 1 1 o 0 Clock 3 0 00 S 1 11 Q(t+1) = 0 1 00 R 1 11 Clock 1 o 0
Synchronous Sequential Logic 2). D = 1 p 0

D Clock 1 111 S 100 Q(t+1) = 1 3 0 o 1 111 R 011
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0 D
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Synchronous Sequential Logic 3). D = 1

D Clock 1 1 o 0 Clock 3 1 11 S 1 00 Q(t+1) = 1 1 11 R 0 00 Clock 3 1 o 0 1 o 0
4). D = 0 p 1
D Clock 1 0010 1 S 1110 1 Oscillation 1010 1 R 1010 1
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1 D
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3. Clock = 1 1). D = 1 p 0
D Clock 1 1 11 S 0 00 Q(t+1) = 1 Clock 3 0 o 1 D
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D Clock 1 1 0 1 01 S 1 0 1 01 Oscillation Clock 3 0 o 1 1 0 1 01 R 1 1 1 11
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2 1
2 1
1 11 R 0 11

D Clock 1 0 1 0 10 S 0 1 0 10 Oscillation Clock 3 0 o 1 0 1 0 10 R 0 1 1 11
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2 1
D
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D Clock 1 1 11 S 0 00 Q(t+1) = 1 Clock 3 1 o 0 D
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5). D = 0 p 1
D Clock 1 000 S 111 Q(t+1) = 0 Clock 3 1 o 0 000 R 111
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2 1
2 1
1 11 R 1 00
Setup Time for HIGH

D Clock 1
0 1 11 0 0 11
00 111 S 11 100 Q(t+1) = 1 11 111 R 10 000

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2 00 11 Clock 3 01 11 D
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Setup Time for LOW

D Clock 1
1 0 00 0 0 11
D Clock 1
1 0 00 0 0 01
11 010 S 11 010 Oscillation 11 010 R 01 111 10 00 D 00 01 Clock
11 000 S 11 111 Q(t+1)=0 11 100 R 01 111

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2 00 11 Clock 3 10 00 D
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Hold Time for LOW

D Clock 1
0 0 11 0 1 11
D Clock For HIGH : no hold time For LOW : no setup time
00 00 S 11 11 Q(t+1) = 0 10 00 R 11 11
2 01 11 Clock 3 00 11 D
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D Clock For HIGH : no setup time For LOW : no hold time

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Graphic symbols for Flip-Flop :

S CLK R Q Q J CLK K Q Q
SR Flip-Flop
D CLK Q
JK Flip-Flop
T CLK Q
D Flip-Flop
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T Flip-Flop
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Direct input (Asynchronous input) :

Direct preset : Setting the flip-flop asynchronously. Direct clear : Clearing the flip-flop asynchronously.

Inputs
Clear Q K Q J
Outputs Q 1 Q0 1 0 Q0
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CLK
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Clear CLK J K Q 0 x x x 0 1 q 0 0 Q0 1 q 0 1 0 1 q 1 0 1 1 q 1 1 Q0
D Flip-Flop
Delay or Data Flip-Flop
D Q D Q
CLK Q Standard Symbol (leading edge)
CLK Q IEEE Symbol (leading edge)
Have the ability to store 1 bit of data.

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The operation of leading edge-triggered D Flip-Flop

D Q
CLK Q
D CLK Q Q
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D Flip-Flop IC
IC 74 174 Type Dual D Hex D Outputs Q, Q Q Features Preset, Clear Clear Clear Clear Output enable Output enable Output enable
171/175 Quad D Q, Q 273 Octal D Q 374/377 Octal D Q 378 Hex D Q 379 Quad D Q, Q
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74LS273 D Flip-Flop IC
3 4 7 8 13 14 17 18 1 11
74273
1D 2D 3D 4D 5D 6D 7D 8D CLR CLK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
2 5 6 9 12 15 16 19
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1D CLK
D R
2D
3D
4D
5D
6D
7D
8D
D R
D R
D R
D R
D R
D R
D R
CLR 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
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SR Flip-Flop
Set-Reset Flip-Flop
S R CLK Q Q S R CLK Q Q
S R CLK Q Operation 0 0 1 1 0 1 0 1 x o o o Q0 0 1 ? Hold Clear Set Unstable
S R CLK Q Operation 1 1 0 0 1 0 1 0 x o o o Q0 0 1 ? Hold Clear Set Unstable

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SR FF wired as a D FF
S R
CLK Q
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Example
A B S R CLK Q Q Qa A B S R CLK Q Q Qb A B S R CLK Q Q Qc
A B CLK Qa Qb Qc
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JK Flip-Flop
J K CLK Q Q
J K CLK Q Operation 0 0 1 1
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0 1 0 1
o Q0 o 0 o 1 o Q 0
Hold Clear Set Toggle

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JK FF wired as a D FF
D
J K CLK Q Q
JK FF wired as a T FF
1
J K CLK Q Q
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Example : IC 7476
4 16 1 3 2 1J 1K

9 12 6 8 7 Q Q 1 0 1 Q0 0 1 Q0 0 1 1 Q0 1 0 Q0 Preset Clear nonstable Hold Reset Set Toggle
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7476 1Q
1Q
15 14
2J 2K
7476 2Q
2Q
11 10
1CLK 1CLR 1PRE PRE CLR CLK J K 0 1 0 1 1 1 1 1 0 0 1 1 1 1 x x x x x x 0 0 1 1 x x x 0 1 0 1
2CLK 2CLR 2PRE
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JK Flip-Flop ICs :
no. of FF Trigger 7470 74H71 7473 74LS73 7476 74LS76 74LS107 74LS109 74111 74LS114 74276 74376
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Synchronous Sequential Logic Preset Clear Yes Yes No No Yes Yes No Yes Yes Yes Yes No Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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1 1 2 2 2 2 2 2 2 2 4 4
Leading Pulse Pulse Trailing Pulse Trailing Pulse Leading Pulse Trailing Trailing Leading
Realizing Circuits with Different Kinds of FFs

Choosing a Flipflop R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types
J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ?In,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!!
Realizing Circuits with Different Kinds of Flipflops

Characteristic Equations R-S: D: J-K: T: Q+ = S + R Q Q+ = D Q+ = J Q + K Q Q+ = T Q + T Q E.g., J=K=0, then Q+ = Q J=1, K=0, then Q+ = 1 J=0, K=1, then Q+ = 0 J=1, K=1, then Q+ = Q Derived from the K-maps for Q+ = F(Inputs, Q)
Implementing One FF in Terms of Another
J D
Q Q
Q D J Q Q
D implemented with J-K
J-K implemented with D

Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?
Q Q+ 0 0 0 1 1 0 1 1
X 0 1 0
S 0 1 0 X
J K 0 X 1 X X 1 X 0
T 0 1 1 0
D 0 1 0 1
Q
D 0 0 1 0 0 1 1 1
Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = F(D, Q) 2) Create K-maps for J and K with same inputs (D, Q)
Q+ = D
3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map
D D 0 0 1 0 X 1 1 X Q 0 1 0 X 1 1 X 0
E.g., D = Q= 0, Q+ = 0 then J = 0, K = X
J= D
K =D

Design Procedure (Continued) Implementing J-K FF with a D FF: 1) K-Map of Q+ = F(J, K, Q) 2,3) Revised K-map using D's excitation table its the same! that is why design procedure with D FF is simple!
J 00 01 0 1 0 0 0 0 11
J 10
J
Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF.
Analysis of Clocked Sequential Circuits

Sequential circuit example :
x Ax Bx CLK Q A Ax+Bx D Q A
Ax CLK A+B
B B y
CLK Q (A+B)x
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Next State Equation :

A(t+1) = A(t) x(t) + B(t) x(t) = Ax + Bx B(t+1) = A(t) x(t) = Ax
Present State of the Output :

y(t) = [A(t) + B(t)] x(t) = [A + B]x
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State Table :
Consist of 4 section :
present input next
1st form of the state table

Present state A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Next Input state Output x 0 1 0 1 0 1 0 1 A B 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 y 0 0 1 0 1 0 1 0
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state
state output
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2nd form of the state table :
Present state AB 00 01 10 11
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Next state x=0 x=1 AB AB 00 01 00 11 00 10 00 10
Output x=0 x=1 y y 0 0 1 0 1 0 1 0

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State Diagram
A state is represent by a circle. Direct lines : transition between the states. Examples:

0/0 00
Input/Output
0/1 0/1
1/0 10 1/0 11
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1/0 01
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0/1
1/0
Flip-flop Input Functions

The logic diagram of a sequential circuit consists of flip-flops and gates. Circuit Output Functions The parts of the combinational circuit that generates external outputs are described algebraically by a set of Boolean functions. Flip-flop Input Functions (Input Equation) The parts of the circuit that generates the inputs to flip-flops are described algebraically by a set of Boolean functions.
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Ax Ax+Bx D Bx Q CLK Q

A A
Ax
B B y
CLK A+B(A+B)x CLK Q

Flip-flop Input Function :

DA = Ax + Bx DB = Ax
Circuit Output Function :

y = ( A + B ) x
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B y B C x B C x

K CLK CLK J
Flip-flop Input Function :

JA = BCx + BC x KA = B + y
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Characteristic Tables :
JK Flip-flop J K Q(t+1) 0 0 1 1 0 1 0 1 Q(t) No change 0 Reset 1 Set Q(t) Complement D Flip-flop D Q(t+1) 0 1
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RS Flip-flop S R Q(t+1) 0 0 1 1 0 1 0 1 Q(t) 0 1 ? No change Reset Set Unpredictable
T Flip-flop T Q(t+1) 0 1 Q(t) Reset Q(t) Set

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0 1
Reset Set
Analysis with JK and Other Flip-flop

Step : Obtain the binary value of each flip-flop input function in terms of the present states and input variables. Use characteristic table to determine the next states.
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Example :
J CLK CLK K Q Q A
J CLK K
Flip-flop Input Functions : JA = B KA = Bx JB = x KB = A x

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Synchronous Sequential Logic State Table : Present state A B 0 0 0 0 1 1 1 1

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Next Input state x 0 1 0 1 0 1 0 1 A B 0 0 1 1 1 1 0 1 1 0 1 0 1 0 0 1
Flip-flop Inputs JA KA JB KB 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0
JA = B KA = Bx JB = x KB = A x
0 0 1 1 0 0 1 1
JK Flip-flop J K Q(t+1) 0 0 1 1 0 1 0 1 Q(t) 0 1 Q(t)
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Synchronous Sequential Logic State Diagram : 1 00 0 01 0 10 1 1 11 0
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Two types of clocked sequential networks :

Moore Network, Moore Machine, Moore Model Mealy Network, Mealy Machine, Mealy Model
Moore Machine :
The outputs depend only on the present state.
xi
Combinational Logic
Flip Flops
Combinational Logic for Outputs
yk
CLK The Outputs change synchronously with the clock.

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Mealy Machine :
The outputs depend only on the present state and the present value of the inputs. xi yk
Combinational Logic Flip Flops
CLK The Outputs change asynchronously with the clock.

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State Reduction and Assignment

State Reduction reduce the number of flip-flops. Example : State diagram
0/0 a 0/0 1/0 b 1/0 g 0/0 1/1
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0/0 0/0 1/0 d 1/1 f 1/1 0/0 c
0/0
1/1
1. Example of input sequence 01010110100 start from initial state a. state a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0
0/0 a 0/0 1/0 b 1/0 g 0/0 1/1
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0/0 0/0 1/0 d 1/1 f 1/1 0/0 c
0/0
1/1
Synchronous Sequential Logic 2. State Table :
Present state a b c d e f g
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Next state x=0 x=1 a b c d a d e f a f g f a f
Output x=0 x=1 0 0 0 0 0 0 0 1 0 1 0 1 0 1

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3. Two states are said to be equivalent if, for each member of the set of the inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state. Reducing the state table : Present state a b c d e f g
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Next state x=0 x=1 a b c d a d e fd a fd ge f a f
Output x=0 x=1 0 0 0 0 0 0 0 1 0 1 d, f equivalent 0 1 e, g equivalent 0 1

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Synchronous Sequential Logic 4. The final reduced state table :
Present state a b c d e
Next state x=0 x=1 a b c d a d e d a d
Output x=0 x=1 0 0 0 0 0 0 0 1 0 1
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Synchronous Sequential Logic 5. The final reduced state diagram : 0/0 a 0/0 1/0 0/0 e 1/1 0/0 d 1/1
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0/0 b 1/0 1/0 c
Compare: state a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 state a a b c d e f f g f g a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0
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State Assignment :
Reduce the cost of combinational circuit part of a sequential circuit : 1). Using simplification method for combinational circuit. 2). Appropriate state assignment : The complexity of combinational circuit obtained depends on the binary state assignment chosen.
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Synchronous Sequential Logic Challenging Problem : No state-assignment procedures that guarantee a minimal-cost combinational circuit. Example : Three possible binary state assignments State Assignment1 Assignment2 Assignment3 a b c d e
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001 010 011 100 101
000 010 011 101 111
000 100 010 101 011

9-105
Present Next state Output state x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 Reduced state table with binary state assignment 1 Present state 001 010 011 100 101
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Next state x=0 x=1 001 010 011 100 001 100 101 100 001 100
Output x=0 x=1 0 0 0 0 0 0 0 1 0 1

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Flip-flop Excitation tables

A table that lists the required inputs for a given change of state. Characteristic table Useful for analysis and defining the operation of the flip-flop. Excitation table : Useful for design process.
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Flip-flop Excitation tables

RS flip-flop Q(t) Q(t+1) 0 0 0 1 1 0 1 1 S 0 1 0 x R x 0 1 0
JK flip-flop Q(t) Q(t+1) 0 0 0 1 1 0 1 1 J 0 1 x x K x x 1 0
D flip-flop Q(t) Q(t+1) 0 0 0 1 1 0 1 1

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T flip-flop D 0 1 0 1 Q(t) Q(t+1) 0 0 0 1 1 0 1 1 T 0 1 1 0

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Design Procedures
Recommended Steps :
1. Word description of the circuit behavior

May be accompanied by a state diagram, a timing diagram, . . . Example 0 1 01 1 0
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00
1 11 1
10 0
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2. Obtain the State Table

Next state x=0 x=1 A B A B 0 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0
Present state A B 0 0 0 1 1 0 1 1
3. State reduction if needed. 4. State assignment if needed.

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5. Determine the number of flip-flop and assign a letter symbol to each. 4 states 2 flip-flops letter symbol : A and B 6. Choose the type of flip-flop.
Example : choose JK flip-flops.
A Q K
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A Q J
B Q K
B Q J
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The block diagram of sequential circuit

A A B B
Q K KA A A B B
Q J JA
Q K KB
Q J JB Clock External outputs (none)
Combinational Circuit
x External input
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9-112
7. Derive the circuit excitation tables and output tables

Inputs of Combinational Circuit Present state Input A B x 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
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Outputs of Combinational Circuit Next state Flip-flop Inputs A B JA KA JB KB 0 0 0 x 0 x 0 0 1 0 x 1 x 1 0 1 x x 1 0 1 0 x x 0 1 0 x 0 0 x 1 1 x 0 1 x 1 1 x 0 x 0 0 0 x 1 x 1

9-113
8. Derive circuit output function and flip-flop input function

Bx A 00 0 0 1 x
JA
01 0 x 11 10 0 x 1 x
Bx A 00 0 x 1 0
KA
01 x 0 11 10 x 1 x 0
JA=Bx
Bx A 00 0 0 1 0
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KA=Bx
Bx A 00 0 x 1 x
JB
01 1 1 11 10 x x x x
KB
01 x x 11 10 0 1 1 0
9-114
JB=x
KB= ( A x )
9. Draw logic diagram

A A B B
Q K KA
Q J JA
Q K KB
Q J JB Clock
x
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Design with D Flip-flop :

1. State Table :
Present state Input A 0 0 0 0 1 1 1 1
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Next state Output A 0 0 1 0 1 1 1 0 B 0 1 0 1 0 1 1 0 y 0 1 0 0 0 1 0 0

9-116
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
2. Derive circuit output function and flip-flop input function : Since DA = A(t+1), DB = B(t+1) Excitation = Next state DA(A, B, x) = (2, 4, 5, 6) DB(A, B, x) = (1, 3, 5, 6) y(A, B, x) = (1, 5)
Bx A 00 0 0 1 1
DA
01 0 1 11 10 0 0 1 1
Bx A 00 0 0 1 0
DB
01 1 1 11 10 1 0 0 1
Bx A 00 0 0 1 0
y
01 1 1 11 10 0 0 0 0
DA=AB + Bx
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DB=Ax + Bx + ABx
y=Bx
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A A
CLK Q
D CLK
B B
CLK Q
y
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Design with unused states :

1. State Diagram
0/0 001 0/0 1/0 0/0 101 1/1 0/0 100 1/1
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0/0 011 1/0 1/0 010
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2. State Table :
Present state Input Next state A 0 0 0 0 0 0 1 1 1 1 B 0 0 1 1 1 1 0 0 0 0 C 1 1 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 0 1 A 0 0 0 1 0 1 1 1 0 1 B 0 1 1 0 0 0 0 0 0 0 C 1 0 1 0 1 0 1 0 1 0 Flip-flop Inputs SA RA 0 x 0 x 0 x 1 0 0 x 1 0 x 0 x 0 0 1 x 0 SB RB SC RC 0 x x 0 1 0 0 1 x 0 1 0 0 1 0 x 0 1 x 0 0 1 0 1 0 x 1 1 0 x 0 x 0 x x 0 0 x 0 1 Output y 0 0 0 0 0 0 0 1 0 1
9-120
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Unused states : ( 000, 110, 111) For variables : A B C x m0 , m1 , m12 , m13 , m14 , m15 unused treat as dont care condition.
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3. Derive circuit output function and flip-flop input function :

SA
Cx 00 AB 00 x 01 11 x 10 x 01 x 1 x x 1 x x x 11 10 Cx 00 AB 00 x 01 x 11 x 10 x x 01 x 11 10 x x x x 1
RA
SA = B x
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RA = C x
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Cx 00 AB 00 x 01 x 11 x 10
SB
01 x 11 10 1
Cx 00 AB 00 x 01
RB
01 x 1 x x 1 x x 11 10 x 1 x x
11 x 10 x
SB = A B x
Cx 00 AB 00 x 01 1 11 x 10 1
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RB = B C + B x
Cx
SC
01 x 11 10 x x x x x x
RC
01 x x x x 11 10 1 1 x 1
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00 AB 00 x 01 11 x 10
SC = x
RC = x
y
00 AB 00 x 01 11 x 10 x 1 x 1 x Cx 01 x 11 10
y=Ax
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x S

y Q Q A A
CLK R
S CLK R
Q Q B
S CLK
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Q Q
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CLK R
5. Problem : What if a circuit is not reset to a initial valid state ? Check unused state : A=B=C=0, x=0 (m0) from filp-flop input function : SA=RA=0, SB=RB=0, SC=1, RC=0, y=0 Flip-flop C : set , i.e. 000
0/0
001
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A=B=C=0, x=1 (m1) from filp-flop input function : SA=RA=0, SB=1, RB=0, SC=0, RC=1, y=0 Flip-flop B : set , i.e. 000
1/0
010
The other unused states : 110 110 111

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0/0 1/1 0/0 1/1
111 100 001 100

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111
Synchronous Sequential Logic 0/0 001 0/0 1/0 0/0 101 1/1 0/0 100 1/1 011 1/0 1/0 1/1 010 1/1 111 110 0/0 1/0 0/0 000
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Design of Counter
Counter : A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses (count pulse). Binary Counter : A counter that follows the binary sequence.
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Binary Counter : 1. State Diagram

000 001 111
010
110
011 100
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101
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2. Choose the type of Flip-flop T Flip-flop 3. Derive the circuit excitation table and output table :
Present state A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
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Next state A2 A1 A0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0
Flip-flop Input TA2 TA1 TA0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1

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4. Derive the circuit output function and flip-flop input function :

TA2
A 1A 0 A 00
2
TA1
A1A0 A 00
2
TA0
A 1A 0 A 00
2
01 0 0
11 10 1 1 0 0
01 1 1
11 10 1 1 0 0
01 1 1
11 10 1 1 1 1
0 0 1 0
0 0 1 0
0 1 1 1
TA2=A1 A0
TA1= A0
TA0= 1
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A2 A1 A0
Q T
Q T
Q T Count pulse
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Counter with Nonbinary Sequence : 1. State Diagram

000 001 110
010 100
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101
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2. Choose the type of Flip-flop JK Flip-flop 3. Derive the circuit excitation table and output table :
Present state A2 A1 A0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0
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Next state A2 A1 A0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0
Flip-flop Input JA2 KA2 JA1 KA1 JA0 KA0 0 x 0 x 1 x 0 x 1 x x 1 1 x x 1 0 x x 0 0 x 1 x x 0 1 x x 1 x 1 x 1 0 x

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4. Derive the circuit output function and flip-flop input function : m3 and m7 : dont care condition. JA2 = B JA1 = C JA0 = B KA2 = B KA1 = 1 KA0 = 1
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A2 A1 A0
Q K
Q J
Q K
Q J
Q K
Q J Count pulse
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6. Check m3 ant m7
011 p 100 111 p 000
A2 A1 A0
0 1
Q K Q J Q K Q J
1 0
Q K Q J
1 0
Count pulse
1
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000 001 110
111
010 100
101 011
2011/3/30
9-139

Sequential Logic

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Sequential Logic

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IT06IU -- Digital Logic Design

Chapter 4 Sequential Logic Design

Synchronous Sequential Logic

Asynchronous latches Synchronous latches

Synchronous Sequential Logic

True Output Complement Output D Q Q 0 1 0 1 1 0

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

Q0 Q0 Hold (no change) 0 1 Reset 1 0 Set Unstable Unstable

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous sequential Logic

Synchronous Sequential Logic

Set state ( 1 state ) Q = 1, Q = 0. Clear state ( 0 state ) Q = 0, Q = 1. Example:

Synchronous Sequential Logic

 SR Latch : NAND gate latch

Q0 Q0 Hold (no change) 0 1 Reset 1 0 Set Unstable Unstable

Synchronous  Gated SR Latch ( RS flip-flop ) Sequential Logic

Logic diagram (1)

Synchronous Sequential Logic

Logic diagram (2)

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

Operation Hold (Disable) Hold Reset Set Unstable

Synchronous Sequential Logic

 Gated D Latch ( D flip-flop )

Synchronous Sequential Logic

Synchronous Sequential Logic

TTL No. 7475 74116 74279

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

 TTL Latch IC 74116

Synchronous Sequential Logic

1CLR 1C1 1C2 74116-1 Inputs CLR C1 C2 D 1 1 1 1 0 0 0 x 1 x 0 0 1 x x 0 1 x x x

2CLR 2C1 2C2 74116-2

Synchronous Sequential Logic

 TTL Latch IC 7475

Synchronous Sequential Logic

 Application Switch Debounce Circuit :

Output waveform Ideal

Synchronous Sequential Logic

Synchronous Sequential Logic

The internal R and S are never simultaneously 1.

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

Synchronous Sequential Logic

Characteristic table and characteristic equation

Synchronous Sequential Logic

FF changes its output state base on :

The timing input Clock (CLK)

Synchronous Sequential Logic

 Definition of clock-pulse transition :

Positive- Negativeedge edge

Negative- Positiveedge edge

Synchronous Sequential Logic

Level triggered. Edge-triggered :

Synchronous Sequential Logic

clock Q (leading) Q (trailing) Q (pulse)

SR Latch : NAND gate latch

Synchronous Gated SR Latch ( RS flip-flop ) Sequential Logic

Gated D Latch ( D flip-flop )

TTL Latch IC 74116

TTL Latch IC 7475

Application Switch Debounce Circuit :

Definition of clock-pulse transition :

Graphic symbols for Flip-Flop :

Direct input (Asynchronous input) :

Have the ability to store 1 bit of data.

The operation of leading edge-triggered D Flip-Flop

Flip-flop Input Functions