VLSI Design Project 2010/11

Microprocessor Research Topic 4: Instruction Set Coding

By: Manraj Singh Gujral Id: msg1g10 Team B7 msg1g10@soton.ac.uk

Table of Contents
1. Introduction ................................................................................................................................ 1 2. Instruction Fields ....................................................................................................................... 1 3. Orthogonality & Code Density .................................................................................................. 1 a. Orthogonality Principles .............................................................................................. 1 b. Code Density................................................................................................................. 3 4. Conclusion ................................................................................................................................. 4 5. References .................................................................................................................................. 5 6. Bibliography .............................................................................................................................. 5

1. Introduction
A CPU works on a set of Instructions which details it interact & schedule other system modules. This is known as Machine/Computer Instructions and a collection of instructions that a CPU can execute is called the Instruction Set for that CPU

2. Instruction Fields
An Instruction, in general, must specify the CPU with full information required to complete that instruction. There are a wide variety of Instructions types but we will list out the basic elements. Figure 1 shows a sample 16-Bit Instruction.
32 -Bit 6 -Bits Opcode 6-bit Operation Code 5 -Bits rs Source Register 5 -Bits rt Destination Register 16-Bits immediate 16-bit signed immediate for Logical/Arithemetic. Load/store address, PC relative Branch

Fig 1. A sample MIPS32 32-Bit CPU Instruction Register Format

An Instruction usually consists of: [1] a. b. c. d. Opcode: Instructs the CPU about the type of operation to be performed. For Eg: ADD, SUB etc. Source Operand(s): Instructions usually process data from a source. It could be a source address containing data, a register address, or a data value (immediate) itself. Result Operand: Specifies the result storage element. Next Instruction: Guides the CPU for next instruction. This can be provided by a Program Counter (PC) also.

The types of Instructions possible are shown in figure 2.

Description Function Op1 Op2 D Next -i n-bits IR Size =( f + 4x n) bits 3-address instructions Function f-bits Op1 n-bits Op2 n-bits D n-bits 2-address instructions Function f-bits Op1 n-bits Op2 n-bits 1-address instructions Function f-bits Op1 n-bits 0-address instructions Function f-bits IR Size = f bits IR Size =( f + n)bits JR RS MIPS32 Instruction Example: JR RS Schematic: PC := Rs IR Size=( f + 2x n) bits MVN Rd Rm Example: MVN Rd,Rn Schematic: Rd := Rm IR Size=( f + 3x n)-bits MUL Rd Rm Rs Example: MUL Rd,Rm,Rs Schematic: Rd := Rm*Rs 4-address instructions ADD d s1 Example instructions s2 Next_i Example: ADD d,s1,s2,next_i Schematic: d := s1+s2 pc := next_i

f-bits n-bits n-bits n-bits Example: ADD Op1, Op2, D, Next-i

16 bit MU0 Instruction

ARM32 Instruction

ARM Thumb Instruction

STC
8086 Instruction

Example: STC Schematic: DF = 1 (To set Carry Flag)

Fig 2. IR types

3. Orthogonality and Code Density

a. Orthogonality Principles We will first look at an example of an Instruction Register from a RISC Processor family, SPARC (Scalable Processor ARChitecture).[3]

32 -Bits Format 1 (op =1) : CALL Format op

31 29

disp30
0

Format 2 (op =0) : SETHI & Branches op

31 29

rd rd

op2
24 21

imm22
0

op a
31 29

op2
24 21

disp22
0

Format 3 (op =2 or 3) : Folating point & General formats op

31 29

rd
24

op2
18

rs1 rs1
18

i=0 13 i=1 13 12 12

asi
4

rs2
0

op
31 29

rd
24

op2 op2
24 18

simm13
0

op
31 29

rd

rs1
13

opf
4

rs2
0

32 -Bits
Legends: op , op2 : 2- and 3- bit fields, encoding three major formats of Instruction Register disp30, disp22 : 30-bit and 22-bit fields. Word aligned, sign-extended, PC-relative displacements Imm22: 22-bit field for Constant (used for SETHI specific instructions) rd: A 5-bit field address for source (or destination) r- or f- or co-processor registers. IU has r-registers and FPU has f-registers a, i : 1-bit select signals for conditional branching inst. and second ALU operand selection resp.

Fig 3. SPARC Instruction formats

A SPARC (Ver.8) processor uses 72 Instructions in the 3 given Instruction formats. rs and rd bit fields allow us to select the Source and Destination operands which could be any of the following, as shown in the figure 4.
32 -Bits op
31 29

rd
24

op2
18

rs1

i=0 13 12

asi
4

rs2
0

R-regsiters IU

A SPARC Processor has different set of register banks. Field rd, rs1 , rs2 can use any of the rregisters in the IU (or even F-Registers/CP-Registers in certain SPARCs) . Figure 5, gives a basic block diagram of a SPARC Ver.8 processor emphasizing the large number of registers available with it.

F-regsiters FPU

Fig 4. SPARC Orthogonality

.
2

CP-regsiters CP

Interger Unit (IU)

Floating Point Unit (FPU)

Coprocessor (CP)

8- Local 8-Ins

CWP +1
8-Outs 8-Local 8-Ins

32-bit reg 32-bit reg

32-bit reg 32-bit reg 32-bit reg 32-bit reg 32-bit reg

CWP
8-Outs 8-Local 8-Ins

32-bit reg 32-bit reg

8-Outs 8-Local

8-Globals

Total of 40 to 520 general purpose called R-Registers (32-bit registers)

Total of 32 registers called the F-Registers (32-bit registers)

Total number of registers is Appplication specific. Coprocessor-Registers (32-bit registers)

Even though Orthogonality, i.e., elements in the Operand being independent of the Opcode, is exhibited by this RISC Based SPARC Processor to a large extent, it is essential to note that not all the instructions are always orthogonal. Considering the Opcode in Instruction shown in figure 6, disp22 encodes only a 22-bit word, or PC-relative displacement for call or jump resp. And no other operands are permitted.
op a
31 29

rd

op2
24 21

Fig 5. SPARC Ver.8 Architecture with Registers

disp22
0

22-bit word-aligned, signextended,PC relative value for Branch Opcode

R-regsiters IU

F-regsiters FPU

CP-regsiters CP

Fig 6. SPARC Architecture with Registers

As CISC architecture uses custom Op-codes for specialized registers for specific operations, therefore Orthogonality between Op-codes and Operands decreases. b. Code Density RISC processors suffer from code density issues. The issue of code density can be explained by an example if figure 7.
Assembly Level Representation Program for RISC Memory Instructions Location 1 LD Rs,mem(16) 2 LD Rs2 , mem(20) 3 ADD Rs,Rs 4 SUB Rs2 5 JMPNZ Rs2, mem(3) 6 ST mem(16), Rs Program Memory Location 1 2 Assembly Level Representation for CISC Instructions LDA mem(16)
MUL mem(20),mem(16)

Semantics Rs mem[16] Rs2 mem[20] Rs Rs +Rs Rs2 Rs2-1 PC [3] if Rs2 0 mem[20] Rs

.
Semantics Acc mem[16] Acc Acc * mem[16] mem[16] Acc

CWP -1

32-bit reg

...
49 50

JMPZ mem (32) ST mem(44) CISC Instructions

...

PC [57] if Acc 0 mem[44] Acc

...
98 99

JMPNZ Rs8, mem(57) ST mem(44),Rs7 RISC Instructions

A sample program for a certain set of Arithemetic Operations in RISC coding and CISC coding

...

PC [57] if Rs8 0 mem[44] Rs7

Fig 7.Code density Illustration between a RISC and CISC program

Since Complex Instructions can be written to perform complex task over many clock cycles, the entire program code memory is greatly reduced. In figure 6, the same multiplication and storing of the value to a memory location is achieved in one Instruction Cycle by CISC and it takes RISC 6 instructions to do so. Pl note it does not mean the program runs any faster than a RISC code since Complex Instructions would mean a complex Datapath to achieve it & over multiple clock cycles too. Its only the description of the program which takes a lot less memory therefore Increasing the Code Density [4].
Table.1 : Example of 8086 microprocessor Instruction set (CISC)

Instruction Algorithm JA JAE JB if (CF = 0) and (ZF = 0) then jump if CF = 0 then jump if CF = 1 then jump

Explanation Jump if 1st operand is Above second operand Jump if Above or Equal Jump if below

Remarks two Conditions checked one condition checked one condition checked 4-byte address may be entered

JMP

jump

Unconditional Jump

Table.1 shows just 4 out of 32 possible Jump Instructions in 8086 microprocessor, each performing a JUMP based on different conditions. In a RISC code the programmer will have to write the individual Compare or other Flag checks in a separate line of code therefore increasing the number of lines of codes.[5] Although RISC processors are not known for high code Density but ARM Thumb architecture, which uses 16-bit compressed Instructions form of a 32-bit ARM Instruction Set, has a very high Code Density [2]

ARM Instruction Stream

Switch back If Explicit Thumb BX or Exception Switch to

cond
31 28 27 5 43

Rm
0 16 0

32-bit ARM Instructions

If Rm[0]=1

16-bit Thumb Instructions

Fig 8.32-bit ARM Instruction stream can switch to 16-bit Thumb Instruction stream for low power routines for the same processor.

4. Conclusion
Both RISC and CISCs have certain advantages over one other. It is therefore the designers choice whether working on program memory constraint or a performance or ease of datapath implementation etc , to understand these different aspects when designing a microprocessor. (Words :776)

5. References
[1] [2] [3] [4] [5] William Stallings, Computer Organization & Architecture, 5th edition, Princte Hall, Chapter 9: Machine Instruction Characteristics Steve Furber,(2000), ARM system-on-chip architecture , 2nd Edition, Pearson Education Limited SPARC International, Inc , The SPARC Architecture Manual, Version 8, Revision SAV080SI9308 . Gajski D D,( 1997) Principles of Digital Design, Prentice Hall, pp388-433. Dr. Philip Leong , 8086 Instructions , Lecture Notes Computer Architecture, Imperial College London.

6. Bibliography
David A. Patterson, David R. Ditzel , The Case for the Reduced Instruction Set Computer, ACM SIGARCH Computer Architecture News Homepage archive Volume 8 Issue 6, October 1980 Luca Benini , Giovanni De Micheli , Alberto Macii , Enrico Macii, Massimo Poncino, Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding, VLSI, Proceedings of the 8th Great Lakes Symposium 1998, Pages 8 12 MIPS64 Architecture for Programmers Volume IV-a: The MIPS16e Application- Specific Extension to the MIPS64 Architecture, Revision 2.60 (2008), Copyright MIPS Technologies Inc. Ozan Aktan (PhD. Student), The Scalable Processor Architecture (SPARC) & The Supersparc Microprocessor, Lecture notes, Department of Electrical and Electronics Engineering ,Boazii University, Istanbul Robert B. Garner, Anant Agrawal, Fay6 Briggs, Emil W. Brown, David Hough, Bill Joy, Steve Kleiman, Steven Muchnick, Masood Namjoo, Dave Pattersont, Joan Pendleton, & Richard Tuck, The Scalable Processor Architecture (SPARC) , Future Generation Computer Systems , Volume 7, Issues 2-3, April 1992, Pages 303-309