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FEATURES
10 MHz multiplying bandwidth INL of 0.25 LSB @ 8 bits 20-lead and 24-lead TSSOP packages 2.5 V to 5.5 V supply operation 10 V reference input 21.3 MSPS update rate Extended temperature range: 40C to +125C 4-quadrant multiplication Power-on reset 0.5 A typical current consumption Guaranteed monotonic Readback function AD7528 upgrade (AD5428) AD7547 upgrade (AD5447)
Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface AD5428/AD5440/AD5447
GENERAL DESCRIPTION
The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit, dual-channel, current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered and other applications. As a result of being manufactured on a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz. The DACs use data readback, allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s, and the DAC outputs are at zero scale. The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. The AD5428 is available in a small 20-lead TSSOP package, and the AD5440/AD5447 DACs are available in small 24-lead TSSOP packages.
1
APPLICATIONS
Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming
AD5428/AD5440/AD5447
VDD DATA INPUTS DB0 DB7 DB9 DB11 R RFBA IOUTA
INPUT BUFFER
LATCH
AGND DAC A/B R CS R/W LATCH DGND CONTROL LOGIC 8-/10-/12-BIT R-2R DAC B RFBB IOUTB
POWER-ON RESET
04462-001
VREFB
Figure 1. AD5428/AD5440/AD5447
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20042011 Analog Devices, Inc. All rights reserved.
Data Sheet
Divider or Programmable Gain Element................................ 20 Reference Selection .................................................................... 20 Amplifier Selection .................................................................... 20 Parallel Interface......................................................................... 22 Microprocessor Interfacing....................................................... 22 PCB Layout and Power Supply Decoupling ........................... 23 Evaluation Board for the AD5447............................................ 23 Power Supplies for the Evaluation Board................................ 23 Bill of Materials............................................................................... 27 Overview of AD54xx Devices....................................................... 28 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29
REVISION HISTORY
8/11Rev. B to Rev. C Changes to CS Pin Description, Table 6 ........................................ 9 3/11Rev. A to Rev. B Changes to Evaluation Board For the AD5447 Section ............ 23 Changes to Figure 47 Caption....................................................... 24 Changes to Figure 49...................................................................... 25 Change to U1 Description in Table 12......................................... 27 Change to Ordering Guide............................................................ 29 7/05Rev. 0 to Rev. A Changed Pin DAC A/B to DAC A/B................................Universal Changes to Features List .................................................................. 1 Changes to Specifications ................................................................ 3 Changes to Timing Characteristics ................................................ 5 Change to Figure 2 ........................................................................... 5 Change to Absolute Maximum Ratings Section........................... 6 Change to Figure 13, Figure 14, and Figure 18........................... 11 Change to Figure 32 Through Figure 34 ..................................... 14 Changes to General Description Section .................................... 16 Changes to Figure 37...................................................................... 16 Changes to Single-Supply Applications Section......................... 19 Changes to Figure 40 Through Figure 42.................................... 19 Changes to Divider or Programmable Gain Element Section .... 20 Changes to Figure 43...................................................................... 20 Changes to Table 9 Through Table 11 ......................................... 21 Changes to Microprocessor Interfacing Section ........................ 22 Added Figure 44 Through Figure 46 ........................................... 22 Added 8xC51-to-AD5428/AD5440/AD5447 Interface Section ........................................................................ 22 Added ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface Section ........................................................................ 22 Changes to Power Supplies for the Evaluation Board Section.... 23 Changes to Table 13 ....................................................................... 28 Updated Outline Dimensions....................................................... 29 Changes to Ordering Guide .......................................................... 29 7/04Revision 0: Initial Version
Rev. C | Page 2 of 32
AD5428/AD5440/AD5447
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: 40C to +125C. All specifications TMIN to TMAX, unless otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE AD5428 Resolution Relative Accuracy Differential Nonlinearity AD5440 Resolution Relative Accuracy Differential Nonlinearity AD5447 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Output Leakage Current REFERENCE INPUT Reference Input Range VREFA, VREFB Input Resistance VREFA-to-VREFB Input Resistance Mismatch Input Capacitance Code 0 Code 4095 DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE Reference-Multiplying BW Output Voltage Settling Time Measured to 1 mV of FS Measured to 4 mV of FS Measured to 16 mV of FS Digital Delay 10% to 90% Settling Time Digital-to-Analog Glitch Impulse VDD 1 VDD 0.5 0.4 0.4 1 10 Min Typ Max Unit Conditions
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV ppm FSR/C nA nA V k %
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
13 2.5
pF pF V V V V V V V V A pF MHz VDD = 3.6 V to 5.5 V VDD = 2.5 V to 3.6 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V VDD = 4.5 V to 5.5 V, ISOURCE = 200 A VDD = 2.5 V to 3.6 V, ISOURCE = 200 A VDD = 4.5 V to 5.5 V, ISINK = 200 A VDD = 2.5 V to 3.6 V, ISINK = 200 A
4 10
VREF = 3.5 V p-p, DAC loaded all 1s RLOAD = 100 , CLOAD = 15 pF, VREF = 10 V DAC latch alternately loaded with 0s and 1s
80 35 30 20 15 3
120 70 60 40 30
ns ns ns ns ns nV-sec
Interface delay time Rise and fall times, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V
Rev. C | Page 3 of 32
AD5428/AD5440/AD5447
Parameter Multiplying Feedthrough Error Min Typ Max 70 48 17 30 Unit dB dB pF pF nV-sec nV/Hz dB dB dB AD5447, 65k codes, VREF = 3.5 V 55 63 65 50 60 62 dB dB dB dB dB dB AD5447, 65k codes, VREF = 3.5 V 73 80 87 70 75 80 72 65 2.5 0.5 Power Supply Sensitivity
1
Data Sheet
Conditions DAC latches loaded with all 0s, VREF = 3.5 V 1 MHz 10 MHz DAC latches loaded with all 0s DAC latches loaded with all 1s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s @ 1 kHz VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz Clock = 10 MHz, VREF = 3.5 V
Output Capacitance Digital Feedthrough Output Noise Spectral Density Analog THD Digital THD 100 kHz fOUT 50 kHz fOUT SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50k Hz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion f1 = 40 kHz, f2 = 50 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD
12 25 1 25 81 61 66
dB dB dB dB dB dB dB dB 5.5 0.7 10 0.001 V A A %/% AD5447, 65k codes, VREF = 3.5 V Clock = 10 MHz Clock = 25 MHz
TA = 25C, logic inputs = 0 V or VDD TA = 40C to +125C, logic inputs = 0 V or VDD VDD = 5%
Rev. C | Page 4 of 32
Data Sheet
TIMING CHARACTERISTICS
AD5428/AD5440/AD5447
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: 40C to +125C. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter 1 Write Mode t1 t2 t3 t4 t5 t6 t7 t8 t9 Data Readback Mode t10 t11 t12 t13 Update Rate Limit at TMIN, TMAX 0 0 10 10 0 6 0 5 7 0 0 5 25 5 10 21.3 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns typ ns max ns typ ns max MSPS Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time Address setup time Address hold time Data setup time Data hold time R/W high to CS low CS min high time Address setup time Address hold time Data access time Bus relinquish time Consists of CS min high time, CS low time, and output voltage settling time
R/W
t1
t2
t8
t2
t9
CS
t3 t4 t5 t10 t11
DACA/DACB
t8
DATA DATA VALID
DATA VALID
200A
IOL
TO OUTPUT PIN
Rev. C | Page 5 of 32
04462-002
t7
t12
t13
Data Sheet
Rating 0.3 V to +7 V 12 V to +12 V 0.3 V to +7 V 0.3 V to VDD + 0.3 V 40C to +125C 65C to +150C 150C 143C/W 128C/W 300C 235C
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ESD CAUTION
Rev. C | Page 6 of 32
AD5428/AD5440/AD5447
AD5428
TOP VIEW (Not to Scale)
18 17 16 15 14 13 12 11
DB2 DB3
Rev. C | Page 7 of 32
AD5428/AD5440/AD5447
Data Sheet
AGND 1 IOUTA 2 RFBA 3 VREFA 4 DGND 5 DAC A/B 6 DB9 7 DB8 8 DB7 9 DB6 10 DB5 11 DB4 12
24 23 22
AD5440
TOP VIEW (Not to Scale)
21 20 19 18 17 16 15 14 13
DB2 DB3
NC = NO CONNECT
Rev. C | Page 8 of 32
Data Sheet
AD5428/AD5440/AD5447
AGND 1 IOUTA 2 RFBA 3 VREFA 4 DGND 5 DAC A/B 6 DB11 7 DB10 8 DB9 9 DB8 10 DB7 11 DB6 12
24 23 22
IOUTB RFBB VREFB VDD R/W CS DB0 (LSB) DB1 DB2 DB3
04462-006
AD5447
TOP VIEW (Not to Scale)
21 20 19 18 17 16 15 14 13
DB4 DB5
21
VDD
Rev. C | Page 9 of 32
Data Sheet
INL (LSB)
04462-007
DNL (LSB)
200
250
DNL (LSB)
INL (LSB)
0.1
0 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
04462-009
DNL (LSB)
INL (LSB)
0.2
0.2 0 0.2 0.4 0.6 0.8 1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
1.0
Rev. C | Page 10 of 32
04462-010
Data Sheet
0.6
8
AD5428/AD5440/AD5447
TA = 25C 7
6 5 4 3 2 1 VDD = 3V VDD = 2.5V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
04462-022
INL (LSB)
VDD = 5V
TA = 25C VDD = 5V
0.50
DNL (LSB)
0.55
10
04462-014
20
20
40
60
80
100
120
TEMPERATURE (C)
5 4 3 2 VDD = 5V
CURRENT (A)
ERROR (mV)
ALL 0s 0.30 0.25 0.20 0.15 0.10 ALL 1s ALL 0s VDD = 2.5V ALL 1s
1 0 1 2 3 4 5 60 VREF = 10V
04462-015
VDD = 2.5V
0.05
04462-024
40
20
20
40
60
80
100
120
140
0 60
40
20
20
40
60
80
100
120
140
TEMPERATURE (C)
TEMPERATURE (C)
Rev. C | Page 11 of 32
04462-023
AD5428/AD5440/AD5447
14 TA = 25C LOADING ZS TO FS VDD = 5V
3
Data Sheet
TA = 25C VDD = 5V
12
10
IDD (mA)
GAIN (dB)
8 6
VDD = 3V
4 VDD = 2.5V 2
6
04462-025
10
100
1k
10k
100k
1M
10M
100M
100k
FREQUENCY (Hz)
1M FREQUENCY (Hz)
10M
100M
Figure 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor
04462-026
6 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 96 102 1
TA = 25C LOADING ZS TO FS
ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AMP = AD8038
1M 10M 100M
GAIN (dB)
VDD = 3V
0x800 TO 0x7FF 0.010 0.005 0 0.005 0 20 40 60 80 100 120 140 160 180 200
04462-041 04462-042
VDD = 3V
ALL OFF 10
100 1k 10k 100k FREQUENCY (Hz)
0.010
VDD = 5V
TIME (ns)
0.2
1.68 0x7FF TO 0x800 1.69 TA = 25C VREF = 3.5V AMP = AD8038 CCOMP = 1.8pF
0
OUTPUT VOLTAGE (V)
VDD = 5V 1.70 1.71 1.72 1.73 1.74 1.75 1.76 0x800 TO 0x7FF
1k 10k 100k 1M 10M 100M
04462-027
GAIN (dB)
0.2
0.4
0.6
Rev. C | Page 12 of 32
04462-028
VREF = 2V, AD8038 CC 1.47pF VREF = 2V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1pF VREF = 0.15V, AD8038 CC 1.47pF VREF = 3.51V, AD8038 CC 1.8pF
9 10k
Data Sheet
90
20 0 20 TA = 25C VDD = 3V AMP = AD8038
AD5428/AD5440/AD5447
80 MCLK = 5MHz 70 60 MCLK = 10MHz
SFDR (dB)
PSRR (dB)
50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 TA = 25C VREF = 3.5V AMP = AD8038
04462-046
40
FULL SCALE
60 80 100 120
04462-043
MCLK = 25MHz
ZERO SCALE
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
fOUT (kHz)
0 10 20
65
70 THD + N (dB)
30
SFDR (dB)
40 50 60 70
75
80
85
80
04462-044
90
0 2 4 6 8 FREQUENCY (MHz) 10 12
100
0
MCLK = 1MHz
10
80
20 30
SFDR (dB)
60
40 50 60 70
40
80 90 100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) 4.0 4.5 5.0
04462048
fOUT (kHz)
Rev. C | Page 13 of 32
04462-047
AD5428/AD5440/AD5447
0 10 20 30
IMD (dB)
SFDR (dB)
Data Sheet
TA = 25C VDD = 5V AMP = AD8038 65k CODES
0 10 20 30 40 50 60
40 50 60 70 80
04462-049
90
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
0 10 20 30 40
SFDR (dB)
0 10 20 30
IMD (dB)
40 50 60 70 80 90
50 60 70 80 90
100 250
04462-050
100 0 50 100 150 200 250 FREQUENCY (kHz) 300 350 400
300
350
400
650
700
750
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
20 0 20
300 ZERO SCALE LOADED TO DAC 250 MIDSCALE LOADED TO DAC FULL SCALE LOADED TO DAC 200
SFDR (dB)
40 60 80
150
100
100
04462-051
50
120 50
60
70
80
130
140
150
0 100
1k
100k
Figure 36. Output Noise Spectral Density Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. C | Page 14 of 32
AD5428/AD5440/AD5447
Digital Feedthrough When the device is not selected, high frequency logic activity on the devices digital inputs is capacitively coupled through the device and produces noise on the IOUT pins and, subsequently, on the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics are included, such as second to fifth harmonics.
THD = 20 log
V 2 2 + V3 2 + V4 2 + V5 2 V1
Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones digitally generated by the DAC and the second-order products at 2fa fb and 2fb fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonic or nonharmonic spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fs/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50%, of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.
Rev. C | Page 15 of 32
Data Sheet
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 38. When an output amplifier is connected in unipolar mode, the output voltage is given by
VOUT = VREF D / 2n
where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5428) = 0 to 1023 (10-bit AD5440) = 0 to 4095 (12-bit AD5447) n is the resolution of the DAC. Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the on and off states of the DAC switches. These DACs are also designed to accommodate ac reference input signals in the range of 10 V to +10 V. With a fixed 10 V reference, the circuit in Figure 38 gives a unipolar 0 V to 10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table 7 shows the relationship between digital code and the expected output voltage for unipolar operation using the 8-bit AD5428.
Table 7. Unipolar Code
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) VREF (255/256) VREF(128/256) = VREF/2 VREF (1/256) VREF (0/256) = 0
Access is provided to the VREF, RFB, and IOUT terminals of DAC A and DAC B, making the devices extremely versatile and allowing them to be configured in several operating modes, such as unipolar output mode, 4-quadrant multiplication bipolar mode, or single-supply mode. Note that a matching switch is used in series with the internal RFBA feedback resistor. If users attempt to measure RFBA, power must be applied to VDD to achieve continuity.
04462-029
Rev. C | Page 16 of 32
Data Sheet
VINA (10V) R11
AD5428/AD5440/AD5447
AD5428/AD5440/AD5447
VDD
DATA INPUTS
DB0 INPUT BUFFER DB7 DB9 DB11 LATCH 8-/10-/12-BIT R-2R DAC A
IOUTA VOUTA
AGND
AGND
DAC A/B CS R/W LATCH DGND CONTROL LOGIC 8-/10-/12-BIT R-2R DAC B
RFBB
R41 C22
IOUTB VOUTB
R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. C2 PHASE COMPENSATION (1pF TO 2pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Rev. C | Page 17 of 32
04462-030
AD5428/AD5440/AD5447
Bipolar Operation
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can easily be accomplished by using another external amplifier and some external resistors, as shown in Figure 39. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from Code 0 (VOUT = VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). When connected in bipolar mode, the output voltage is given by
VOUT = (V REF D / 2 n 1 ) V REF where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (AD5428) = 0 to 1023 (AD5440) = 0 to 4095 (AD5447) n is the number of bits. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 8 shows the relationship between digital code and the expected output voltage for bipolar operation using the 8-bit AD5428.
VINA (10V)
Data Sheet
Table 8. Bipolar Code
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 VREF (127/128) VREF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout techniques must be used. Because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (GBP) and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in the closedloop applications circuit. An optional compensation capacitor, C1, can be added in parallel with RFBA for stability, as shown in Figure 38 and Figure 39. Too small a value of C1 can produce ringing at the output, whereas too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation.
R11 VREFA R62 20k R72 10k C13 DATA INPUTS DB0 DB7 DB9 DB11 IOUTA INPUT BUFFER LATCH 8-/10-/12-BIT R-2R DAC A A1 AGND AGND
R5 20k
AD5428/AD5440/AD5447
VDD
A2 VOUTA R11 5k
RFBA
R21
AGND
DAC A/B CS R/W LATCH DGND 8-/10-/12-BIT R-2R DAC B CONTROL LOGIC
RFBB
R41 C23
R102 20k
A4 VOUTB R12 5k
R31
AGND
VINB (10V)
1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V OUTA = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR VOUTB = 0V WITH CODE 10000000 IN DAC B LATCH. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
04462-031
Data Sheet
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching mode. The reference voltage, VIN, is applied to the IOUTA pin, and the output voltage is available at the VREFA terminal. In this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is voltage at constant impedance (the DAC ladder resistance). Therefore, an op amp is necessary to buffer the output voltage. The reference input no longer sees constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. Note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs and degrades the integral linearity of the DAC. Also, VIN must not go negative by more than 0.3 V, or an internal diode turns on, causing the device to exceed the maximum ratings. In this type of application, the full range of multiplying capability of the DAC is lost.
+5V 2.5V
AD5428/AD5440/AD5447
VDD = 5V
ADR03
VOUT VIN GND VDD VREFA RFBA C1
VOUT = 0V to 2.5V
5V
NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
ADDING GAIN
In applications where the output voltage must be greater than VIN, gain can be added with an additional external amplifier, or it can be achieved in a single stage. Consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 42 shows the recommended method for increasing the gain of the circuit. R1, R2, and R3 should have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required.
VDD
VDD R1 R2
NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
VIN
04462-033
R2R3 R1 = NOTES R2 + R3 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Rev. C | Page 19 of 32
04462-035
04462-034
AD5428/AD5440/AD5447
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to many applications. If this type of DAC is connected as the feedback element of an op amp and RFBA is used as the input resistor, as shown in Figure 43, the output voltage is inversely proportional to the digital input fraction, D. For D = 1 2n, the output voltage is VOUT = V IN / D = V IN /( 1 2 n )
VDD VIN RFBA VDD IOUTA AGND GND
Data Sheet
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of current output DACs, pay attention to the references output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0 to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/C. Choosing a precision reference with low output temperature coefficient minimizes this error source. Table 9 lists some references available from Analog Devices that are suitable for use with these current output DACs.
VREFA
AMPLIFIER SELECTION
VOUT
As D is reduced, the output voltage increases. For small values of the digital fraction D, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0x10 (0001 0000)that is, 16 decimalin the circuit of Figure 43 should cause the output voltage to be 16 times VIN. However, if the DAC has a linearity specification of 0.5 LSB, D can have a weight in the range of 15.5/256 to 16.5/256 so that the possible output voltage is in the range of 15.5 VIN to 16.5 VIN an error of 3%, even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Because only a fraction, D, of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage changes as follows: Output Error Voltage Due to DAC Leakage = (Leakage R )/ D
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. A change in the noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. The input offset voltage should be <1/4 LSB to ensure monotonic behavior when stepping through codes. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. Common-mode rejection of the op amp is important in voltageswitching circuits, because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 8-, 10-, and 12-bit resolution. Provided that the DAC switches are driven from true wideband, low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance at the VREF node (the voltage output node in this application) of the DAC by using low input capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. Analog Devices offers a wide variety of singlesupply amplifiers (see Table 10 and Table 11).
where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV.
04462-040
Rev. C | Page 20 of 32
Data Sheet
Table 9. Suitable ADI Precision References
Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temp Drift (ppm/C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12
AD5428/AD5440/AD5447
Output Noise (V p-p) 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23
Rev. C | Page 21 of 32
AD5428/AD5440/AD5447
PARALLEL INTERFACE
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or 12-bit parallel word format. Control lines CS and R/W allow data to be written to or read from the DAC register. A write event takes place when CS and R/W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word to the DAC register. The DAC latches are not transparent; therefore, a write sequence must consist of a falling and rising edge on CS to ensure that data is loaded into the DAC register and its analog equivalent is reflected on the DAC output. A read event takes place when R/W is held high and CS is brought low. Data is loaded from the DAC register, goes back into the input register, and is output onto the data line, where it can be read back to the controller for verification or diagnostic purposes. The input and DAC registers of these devices are not transparent; therefore, a falling and rising edge of CS is required to load each data-word.
Data Sheet
8xC51-to-AD5428/AD5440/AD5447 Interface
Figure 45 shows the interface between the AD5428/AD5440/ AD5447 and the 8xC51 family of DSPs. To facilitate external data memory access, the address latch enable (ALE) mode is enabled. The low byte of the address is latched with this output pulse during access to the external memory. AD0 to AD7 are the multiplexed low order addresses and data bus, and they require strong internal pull-ups when emitting 1s. During access to external memory, A8 to A15 are the high order address bytes. Because these ports are open drain, they also require strong internal pull-ups when emitting 1s.
A8 TO A15 ADDRESS BUS
WR 8-BIT LATCH
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD5428/ AD5440/AD5447 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx familys user manual for details).
ADDR0 TO ADRR13 ADDRESS BUS
ALE
1ADDITIONAL
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/ AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The asynchronous memory write cycle of the processor drives the digital inputs of the DAC. The AMSx line is actually four memory select lines. Internal ADDR lines are decoded into AMS30, and then these lines are inserted as chip selects. The rest of the interface is a standard handshaking operation.
ADDR1 TO ADRR19 ADDRESS BUS
WR
ADSP-BF5xx1
DATA 0 TO DATA 23
1ADDITIONAL
04462-055
DATA BUS
AMSx
ADDRESS DECODER
CS
AWE
1ADDITIONAL
Rev. C | Page 22 of 32
04462-056
DATA 0 TO DATA 23
DATA BUS
04462-057
AD0 TO AD7
DATA BUS
Data Sheet
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5428/AD5440/AD5447 is mounted should be designed so that the analog and digital sections are separate and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-toDGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close as possible to the package, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), like the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A
AD5428/AD5440/AD5447
microstrip technique is by far the best method, but its use is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. It is good practice to use compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close as possible to the device.
Rev. C | Page 23 of 32
VCC
VDD1 C5 10F +
C1 0.1F
U4 VCC 24 U1 AD5447
21 C23 10F C22 1.8pF 23 24 3 3 2 TP3 TP2 22 4 C26 0.1F C9 10F J2 J5 C7 1.8pF + VSS EXT REF B B 2 3 LK1 A 4
V V+
C6 0.1F
P14 P13
P12
AD5428/AD5440/AD5447
TP4 6 J6 O/P B 7
23 15 16 17 18 19 20 21 22 14 13
VCC
74ABT543
U7
VDD
C25 10F +
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11
DGND
U6-A
CS RW
5 DGND
VCC
P18
Y0
18 17 16 15 14 13 12 11 10 9 8 7 6 19 20
VDD DB0 DB1 DB2 DB3 DB4 RFBB DB5 IOUTB DB6 DB7 DB8 RFBA DB9 DB10 IOUTA DB11 DAC_A/B CS VREFA R/W VREFB DGND AGND 1
A0
P19
Y1
U5 VCC 24
A1
Y2
P136
EXT REF A
Y3
C10 0.1F 6
TP1 J1 O/P A
U3
VDD
1 2 3 4 5 6 7 8 9 10 11 12 23 15 16 17 18 19 20 21 22 J3
VDD
C11 10F +
3 +V IN
J4
C3 10F C4 0.1F +
Rev. C | Page 24 of 32
74ABT543 1 2
C8 0.1F
C12 0.1F
P131
P11
P114
U6-B
Y0 A0 Y1 Y2 Y3 P21 VSS P24 VDD1 + A1 E
12 11 10 9
C15 0.1F
+ P22 P23
VDD
14
13
C14 10F
15
DGND
C17 0.1F
P26
C18 10F
VCC
C19 0.1F
P25
C20 10F
Data Sheet
04464-037
P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130
Data Sheet
AD5428/AD5440/AD5447
04462-036
Rev. C | Page 25 of 32
04462-038
AD5428/AD5440/AD5447
Data Sheet
Rev. C | Page 26 of 32
04462-039
AD5428/AD5440/AD5447
Stock Code FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-130 FEC 499-675 FEC 721-876 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 721-876 FEC 197-427 FEC 499-675 FEC 197-427 FEC 499-675 FEC 240-345 (Pack) FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 310-682 FEC 511-791 and FEC 528-456 FEC 147-753 FEC 151-792 FEC 240-345 (Pack) FEC 240-345 (Pack) AD5447YRU ADR01AR AD8065AR Fairchild 74ABT543CMTC CD74HCT139M AD8065AR FEC 148-922
Rev. C | Page 27 of 32
Data Sheet
Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16
No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2
INL (LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2
Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel
Package1 RU-16, CP-20 RM-10 RU-20 RU-10 UJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 UJ-8 RM-10 RM-8 RU-24 CP-40 RU-20, CP-20 RU-24 RU-16 UJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38
Features 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width
Rev. C | Page 28 of 32
AD5428/AD5440/AD5447
7.90 7.80 7.70
13
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
SEATING PLANE
0.20 0.09
8 0
Figure 51. 20-Lead Thin Shrink Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters
ORDERING GUIDE
Model1 AD5428YRU AD5428YRU-REEL AD5428YRU-REEL7 AD5428YRUZ AD5428YRUZ-REEL AD5428YRUZ-REEL7 AD5440YRU AD5440YRU-REEL AD5440YRU-REEL7 AD5440YRUZ AD5440YRUZ-REEL AD5440YRUZ-REEL7 AD5447YRU AD5447YRU-REEL AD5447YRUZ AD5447YRUZ-REEL AD5447YRUZ-REEL7 EVAL-AD5447EBZ
1
Resolution 8 8 8 8 8 8 10 10 10 10 12 12 12 12 12 12 12
INL (LSB) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 1 1 1 1
Temperature Range 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C 40 C to +125C
Package Description 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP Evaluation Kit
Package Option RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24
Rev. C | Page 29 of 32
AD5428/AD5440/AD5447 NOTES
Data Sheet
Rev. C | Page 30 of 32
AD5428/AD5440/AD5447
Rev. C | Page 31 of 32
AD5428/AD5440/AD5447 NOTES
Data Sheet
20042011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04462-0-8/11(C)
Rev. C | Page 32 of 32