Dynamic and PassTransistor Logic

Prof. Vojin G. Oklobdzija

References (used for creation of the presentation material):

1. 2. 3. Masaki, Deep-Submicron CMOS Warms Up to High-Speed Logic, IEEE Circuits and Devices Magazine, November 1992. Krambeck, C.M. Lee, H.S. Law, High-Speed Compact Circuits with CMOS, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982. V.G. Oklobdzija, R.K. Montoye, Design-Performance Trade-Offs in CMOSDomino Logic, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986.

References:
4. Goncalves, H.J. DeMan, NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures, IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983. L.G. Heller, et al, Cascode Voltage Switch Logic: A Differential CMOS Logic Family, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984. L.C.M.G. Pfennings, et al, Differential Split-Level CMOS Logic for Subnanosecond Speeds, IEEE Journal of Solid-State Circuits, Vol. SC20, No 5, October 1985. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.

5.

6.

7.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

References:
Pass-Transistor Logic: 8. S. Whitaker, Pass-transistor networks optimize n-MOS logic, Electronics, September 1983. 9. K. Yano, et al, A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic, IEEE Journal of Solid-State Circuits, Vol. 25, No 2, April 1990. 10. K. Yano, et al, Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 11. M. Suzuki, et al, A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993. 12. N. Ohkubo, et al, A 4.4-ns CMOS 54x54-b Multiplier Using Passtransistor Multiplexer, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

References:
13. V. G. Oklobdzija and B. Duchne, Pass-Transistor Dual Value Logic For Low-Power CMOS, Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995. 14. F.S. Lai, W. Hwang, Differential Cascode Voltage Switch with the PassGate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995 15. A. Parameswar, H. Hara, T. Sakurai, A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994. 16. T. Fuse, et al, 0.5V SOI CMOS Pass-Gate Logic, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Dynamic CMOS Logic

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

(a)

Dynamic CMOS Latch (a), Dynamic CMOS Master-Slave Latch (b)

Dynamic Node

In

I1

X Cx

I2

Out

In

I1

X Cx

I2

Y Cy

I3

Out

Store (a)

Clock (b)

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Dynamic Manchester Carry Chain

precharge

+ Vdd

+ Vdd

+ Vdd

+ Vdd

pi
Ci

p i 1

pi 2

pi3

C i3
Gi
G i 1

Gi 2

Gi3

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Radiation induced charge

1 + + 0 + + Cin + +

-particle
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits

Accidental charge caused by capacitive or inductive coupling between the signal lines Y and Z. (a) Prevention by inserting and inverter between the affected line and the passtransistor switch (b) v(Z)
Z Line1 Line2
charge

1
MP1 (open)
X=0

v(Y)
MP1
ON

+++
MN1
Cin

0" (a)

Z Y
Inserted invertor

MP1

MN1

Cin

(b)
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 9

CMOS Domino Logic

+Vcc +Vcc
p-type transistor network

fD

f
n-type transistor network

n-type transistor network

Clk
GND GND

(a)

(b)

CMOS logic block (a), Domino Logic (b)

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 10

CMOS Domino Logic

Precharge phase

Operation

Evaluation phase

+Vcc
Q1
ON + ++ ++

+Vcc
Q2

0
F
1 1 Inputs 1
N

1
F

++ N 0 0 Inputs 0 Clock 0

Discharge ON

Q3
OFF

Clock

Q4
ON

GND

GND

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

11

CMOS Domino Logic Operation

+Vcc
Q2

+Vcc

+Vcc
Q2

0 1

Q2

+Vcc
Q2

1 0 1 0
1
1 Inputs 1
N

1 0
N

1
1

f
Inputs 1

1 1 Inputs 1 Clock

Q4

Inputs 1

Q4

Q4

GND

Q4

GND GND

1 0

GND

Dominos
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 12

CMOS Domino Logic: Charge Re-Distribution

+Vcc
Q1
N + + +1 ++ Charge

+Vcc
Q2

0
F ++

1
F

++

0 0 Inputs 0 Clock

1 1 Inputs 0

Charge Re-distribution

Q3

Clock

Q4

GND

GND

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

13

Variations of CMOS Domino Logic: NORA Logic

+Vcc
Q1

F1
Q2

+Vcc

F2
Q3

+Vcc

n-type transistor network

p-type transistor network

n-type transistor network

Clock 0

Q4

Clock GND
1

Q5

Clock
0

Q6

GND

GND

F1

F2

F3

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

14

CVS and DCVS Logic IBM (Heller et al. 1984)

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

15

Cascode Voltage Switch Logic CVS +Vcc IBM

small keeper transistor

Input Signals Clock

Precharge evaluation

n-type transistor network

GND
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 16

DCVS Logic (IBM)

+Vcc

Q1

Q2

Diff. inputs

Combinational logic network n- MOS

Diff. inputs

GND

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

17

DCVS Logic (IBM)

Vdd Vdd

N1

N2

N1

Clock

N2

differential inputs

n-fet trees

differential inputs

n-fet trees

Clock

(a)

(b)

Differential Cascode Voltage Switch Logic: (a) Static DCVLS (b) Dynamic DCVSL
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 18

DCVS Logic vs CMOS

VDD VDD

f f
N1 N2

f
n-MOS transistor switching trees f f inputs

differential inputs

f
Shared Transistors

DCVS Logic consisting of two shared nMOS transistor switching networks

Prof. V.G. Oklobdzija

CMOS consisting of two separate: nMOS and pMOS transistor switching networks
19

Advanced Digital Integrated Circuits

Transistor sharing in DCVS Logic:

Implementation of 3-input XOR function

B C

C Q = a b c
20

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

Switching Asymmetry in DCVSL

VDD VDD VDD

a ON 1 1 1 ++++ ++++ + + A ON + 0 B 0 OFF a 0 OFF 0 C

a b A B C 1 + 1 1 + A ON + 0 B 0 ON + + ON b +a ++ OFF 0 C

a OFF b c 0 A B ON C A B ON b ++ 1 a ++ ++++ OFF

A B C

Vdd

This asymmetry causes current spikes and increased power consumption !

b c
Both paths ON time

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

21

Pass-Transistor Logic

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

22

Pass-Transistor Logic
A B F B A
(a)
B

F
0

0 1 B
(b)

1 0

(a) XOR function implemented with pass-transistor circuit, (b) Karnaough map showing derivation of the XOR function
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 23

Pass-Transistor Logic
A X F Y A
General topology of pass-transistor function generator
X 0 0 1 1 0 0 1 1 B B B B B B B B Y 0 1 0 1 B F 0 A 1 AB

B
B 0 1 0 1

AB AB AB AB AB
A+B

A B

B
B

B
A B A B
B
24

Karnaough map of 16 possible functions that can be realized

Prof. V.G. Oklobdzija

B
B

Advanced Digital Integrated Circuits

Pass-Transistor Logic
Function generator implemented with passtransistor logic
P0 A A B B

P1

F(A,B)

P2

P3

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

25

Pass-Transistor Logic
A=Vdd + V th B=Vdd B A (a) (b) Fmax = Vdd-Vth Cout Vdd Vdd Vdd + V V + th th --

Fmax = Vdd-Vth Cout

Threshold voltage drop at the output of the pass-transistor gate

Voltage drop does not exceed Vth when there are multiple transistors in the path

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

26

Pass-Transistor Logic
A=Vdd + V th In=Vdd ON
+

+Vdd Vdd + V th Vdd Cin

Fmax= Vdd Cout

Vdd A=0V (a) (b)

Elimination of the threshold voltage drop by: (a) pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 27

Complementary Pass-Transistor Logic (CPL)

Pass Variables

Inputs
Control Variables

F
Prof. V.G. Oklobdzija

F
28

Advanced Digital Integrated Circuits

Basic logic functions in CPL

A
B B B

A B
B
B

A B

A
A
C B

A B

A C B C
B
B

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

29

CPL Logic
A A A B
n1 n2

B
n3 n4

B C
Q Qb

C S
(a)

(b)

XOR gate

Sum circuit CPL provides an efficient implementation of XOR function

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 30

CPL Inverter
Level Restoration Transistor Output Inverter

Input

Output

Feedback Inverter

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

31

Double Pass-Transistor Logic (DPL):

VDD
A B B

AND/NAND
A B
B
A

XOR/XNOR
A

A B

A
B A

B
A

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

32

Double Pass-Transistor Logic (DPL):

A A A B
n1 p2 n1 p2

B
p1 n2 p1 n2

B
Q Qb

C C O S S

(a)

XOR

(b)

One bit full-adder: Sum circuit

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 33

Double Pass-Transistor Logic (DPL):

AND/NAND
Vcc A A B B C C Vcc S Vcc A A B B S

DPL Full Adder

Multiplexer

Buffer

OR/NOR
Prof. V.G. Oklobdzija

The critical path traverses two transistors only (not counting the buffer)
Advanced Digital Integrated Circuits 34

Formal Method for CPL Logic Derivation

Markovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed) (b) Express the value of the function in each cube in terms of input signals (c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

35

Formal Method for P-T Logic Derivation

Complementary function can be implemented from the same circuit structure by applying complementarity principle:

Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL.
By applying duality principle, a dual function is synthesized:

Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed. Following pairs of basic functions are dual:
AND-OR (and vice-versa) NAND-NOR (and vice-versa) XOR and XNOR are self-dual (dual to itself)
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 36

Derivation of P-T Logic

A B AND A B NAND A B B B OR A B B OR

0 0

0 0

0
A 0

0 0
L1 A L2

0 1
L2 B L1

1 1
L1 A L2

1 0
L2 B L1

1 1
L1 A L1

1 0
L2 B L2

A 1

A 1

B B

B B

B B

AND

NAND (OR)

OR

Copmplementarity: AND NAND;

Prof. V.G. Oklobdzija

Duality: AND OR
37

Advanced Digital Integrated Circuits

Derivation of CPL Logic

Complementarity: AND NAND
B B

A L 2 B B

B L1

0 0
L1
(a)

0 1
L2

B B

A 1

AND (b)

NAND

OR (c)

NOR

Duality: AND OR NAND NOR

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 38

Derivation of CPL Logic

A B B

A L2 B B

A L1

0 1
L1
(a)

1 0
L2

A 1

XOR (b)

XNOR

(a) XOR function Karnaugh map, (b) XOR/XNOR circuit

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 39

Synthesis of three-input CPL logic

A BC A C L1 C L2 B L3 A C B

00 0

01

11

10

A L1 A B

0 0
L3

0 0

0 1
B

0 0

A 1

L2

AND (a) (b)

NAND

(a) AND function Karnaugh map, (b) AND/NAND circuit

Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 40

Double Pass-Transistor Logic (DPL): Synthesis Rules

1. Two NMOS branches can not be overlapped covering logic 1s. Similarly, two PMOS branches can not be overlapped covering logic 0s. 2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches. 3. At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

41

Double Pass-Transistor Logic (DPL): Synthesis Rules

Complementarity Principle: Complementary logic function in DPL is generated after the following modifications: Exchange PMOS and NMOS devices. Invert all pass and gate signals Duality Principle: Dual logic function in DPL is generated when:

PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

42

DPL Synthesis:
B A B B L 4 L3 A B AND A L2 B L3 GND (a) L1 GND (b) +VDD +VDD A B A L2 A B NAND B A

0 0
L1

0
L4

A 1

(a) AND function Karnaugh map

(b) AND/NAND circuit

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

43

DPL Synthesis: OR/NOR circuit

+VDD +VDD B A

B OR

B NOR

GND

GND

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits

44

DPL Synthesis:
B A B B L 4 L3 A B AND A L2 B L3 GND (a) L1 GND (b)
+VDD

A L2 A

B NAND

0 0
L1

0
L4

A 1

Complementarity Principle: Exchange PMOS and NMOS devices. Invert all pass and gate signals AND NAND

+VDD

+VDD

AND function Karnaugh map

+VDD

AND/NAND circuit
B A

B OR

B NOR

GND

GND

Duality Principle: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged: AND OR NAND NOR
45

Prof. V.G. Oklobdzija

Advanced Digital Integrated Circuits